JPS5923558A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the influence of variations in a power source to be affected to other block such as a logic unit by individually connecting a circuit block and a power pad on the same semiconductor chip, supplying power from individual power sources, and isolating the wells formed in every block. CONSTITUTION:Aluminum wirings La, Lb, Lc,... are connected from a power pad 1 to circuit blocks 2a, 2b, 2c,... and power voltage is applied to the wells 3a, 3b, 3c,.... The wirings La, Lb, Lc are respectively connected to the common lines 1a, 1b, 1c of the source electrodes of an FET in each block. Thus, when the voltage of the power source varies in the well 3b due to the operation of the logic unit 2b, the variation in the power source is transmitted to other blocks from Lb via the pad 1 and the other La, Lb, the influence is hardly affected, thereby improving the reliability of the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that prevents other circuits from being affected by power fluctuations in a logic section or the like within the integrated circuit.

Conventionally, in semiconductor integrated circuits such as ICs for watches,
As shown in FIG. 1(A), one oscillation circuit 2a and a logic part 2 are connected to a common power supply 2in L connected to a power supply pad 1.
When the power supply voltage is supplied to multiple circuit blocks such as b or analog circuits 2c such as A/D converter circuits, as shown in FIG. , other circuit blocks were connected to the power supply line L' coming out from here, so that power was supplied from one line.

Therefore, in conventional semiconductor integrated circuits, when the current flowing in the logic section 2b changes with the logic operation in the logic section 2b and the power supply voltage fluctuates, the power supply voltages of other circuits are also affected by the change. It has changed due to the reception,
For example, oscillation in the 11 oscillation circuit stopped. 9. A/
There was a fear that the accuracy in analog circuits such as D conversion circuits would be reduced.

In particular, C consisting of complementary viO8F'FJT
In MOS IC, generally P channel type M
The O8FET is formed directly on the N-type semiconductor substrate, and the N-channel MO8FET is formed in the P-well region formed on the N-type semiconductor substrate, whereas conventional CMOS IC
In this case, one of the circuits such as the oscillation circuit 2a, the logic section 2b, and the analog circuit 2C? area was shared. That is, conventionally, the well regions of each circuit block were formed continuously and connected to each other. The substrate is connected to ground potential, and the well region has a power line L.
was connected to supply power supply voltage.

Therefore, when a large current flows through the internal elements in the logic section 2b, the current also flows in the well region, causing the power supply voltage of the circuit to fluctuate, which causes other circuits that share the well region to It had a direct impact on Block.

Accordingly, the present invention connects each of a plurality of circuit blocks formed on the same semiconductor chip and a power supply pad by separate wiring lines, and supplies power from separate power lines to the semiconductor chip. By separating the well region formed above into each circuit block, the purpose is to prevent the influence of power supply fluctuations in the logic section etc. from reaching other circuit blocks.

The present invention will be explained below based on the drawings.

FIG. 2 shows an embodiment of the present invention, and shows an outline of each circuit block and wiring pattern on a semiconductor chip.

In this embodiment, a power supply pad 1 to which a power supply voltage is supplied from a power supply bin, and each circuit block 2a, 2b+2c
+, . . . are formed by separate aluminum wirings La, Lb, Lc, . In addition, each circuit block 2a
Well region 3a of +2 b * 2 c * ・””・
+3b+3c.

. . . are formed separately from each other on the semiconductor chip.

And each of the above wirings La * Lb + Lc +...
... is each circuit block 2 a + 2
Well region 3a + of b + 2 c +...
Connected to 3 b + 3 c +...

Each well region 3a r 3 b + 3 c +...
... is applied with a power supply voltage. In addition, each of the 5 wirings L a + L b + L c +...
. . . represents each circuit block 2a.

2b, 2c, . . . Internal power supply line-ea to which the source electrodes of internal MOSFETs are commonly connected.

-gb, -gcl..., respectively.

Note that the well region may be separated not only from each circuit block but also from each element.

As described above, in the above embodiment, the power supply line is drawn out separately from the trunk of the power supply pad for each circuit block, and the well region is separated and formed for each circuit block.

Therefore, for example, the through flow flowing to the internal element (0MO8) increases or decreases with the logic operation of the logic section 2b, which causes the well region 3b of the logic section 2b to
Even if the power supply voltage fluctuates, this power supply fluctuation will be caused by the wiring (power line) Lb connecting the logic section 2b and the power supply pad 1, through the power supply pad 1, and then to another wiring (power line) La.

Lc,... through other circuit blocks 2a, 2
It will be transmitted to cν...

Therefore, if the well area is shared between each circuit block, or even if the well areas are separated, the power line is shared and each well area is connected to a single wire drawn out from the power pad. In this case, the influence of power supply fluctuations in the logic section is more likely to directly affect other circuits via the common well region or to adjacent circuit blocks via the common power supply line. In the embodiment, the influence of fluctuations in the power supply 1u voltage in one circuit block is made extremely difficult to affect other circuit blocks.

As explained above, the present invention connects a plurality of circuit blocks formed on the same semiconductor chip, such as an oscillation circuit, a logic section, and an analog circuit, to a power supply pad using separate wiring, so that each circuit block is In addition to receiving power from a separate power supply line, the well region of each circuit block is formed separately for each circuit block at least, so that the influence of power supply fluctuations in the logic section etc. is extremely severe on other circuit blocks. and be made difficult. Furthermore, this eliminates the risk of the oscillation circuit being stopped or the precision of the analog circuit being degraded due to power fluctuations in the logic section, etc., thereby improving the reliability of the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing how power lines are wired in a conventional semiconductor integrated circuit, and FIG. 2 is a schematic explanatory diagram showing an example of a power line wiring pattern in a semiconductor integrated circuit according to the present invention. 1...Power pad, 2 a * 2 b * 2 c
*・・・Circuit block, 3a13b13el・
...Well region, La, Lb, Lc+...
・Wiring (power line). Agent Patent Attorney Susuki 1) Toshiyuki” ,;, it Figure 1 and A) (B) /

Claims (1)

[Claims] In a semiconductor integrated circuit in which a plurality of circuit blocks are formed on the same semiconductor chip, each of the circuit blocks and power supply pads are connected by separate wiring, and each circuit block is supplied with power from a separate power supply line. 1. A semiconductor integrated circuit, wherein the well region of each circuit block is formed separately for at least each circuit block.