JPS592377A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a semiconductor device, and more specifically, it relates to a method for manufacturing a semiconductor device. The present invention relates to a method of manufacturing a semiconductor device having the present invention.

(2) Background of the technology A diode that has a rectifying property by utilizing an energy barrier formed on the surface of a semiconductor when a metal and a semiconductor are brought into full contact with each other, that is, a barrier of energy formed on the surface of the semiconductor.i7. Parrier diode (hereafter referred to as 8
It is well known that the BD is called BD. usually,
For the formation of SHD, for example aluminum (HT) and its alloys, platinum (Pt), tungsten (W), gold (
Metals such as Au), nichrome (Nl-Cr), and semiconductors such as silicon (81) have been used. SBDs have excellent characteristics such as extremely fast switching operation and good heat dissipation, so they can be advantageously used in various semiconductor integrated circuit devices.

(3) Prior Art and Problems In this technical field, it is often the case that two or more 8BD=i barrier hide metal fittings are present in one integrated circuit device. In such cases, the main methods used by those skilled in the art are: 1. Changing the type of metal of the metal electrode wiring layer, which is one component of 8BD = 1, for each of all 8BDs, and 2. The second method is to change the density of impurities diffused into the semiconductor substrate (mainly the St substrate) for each SBD, which is another element. However, the former is because the wiring process is very complicated.
Not easy to implement. Furthermore, when implementing the latter, it is essential to perform a very shallow impurity diffusion, so advanced processes must be used.

(4) Purpose of the Invention The present invention aims to solve all the problems of the prior art as described above. In other words, it is an object of the present invention to solve all the problems of the prior art as described above.
- It is an object of the present invention to provide an improved manufacturing method for manufacturing a semiconductor device having tlffi, which is easy to implement and does not require a complete advanced process.

(5) Structure of the Invention The present inventors recently discovered that when forming 8BD, (metal electrode wiring layer) On (polysilicon layer; that is, polycrystalline silicon layer, hereinafter referred to as poly 8 layer) On (Semiconductor substrate) Structural components and (Metal electrode wiring layer) On (
combination f with a structure of a semiconductor substrate]
It has been found that the above objective can be achieved in the case of IC.

The present inventors further discovered that poly 8.
1. It has been found that when a layer is interposed, the barrier high tra of 8BD can be controlled even if it is doped with impurities or not, and even if it is heat-treated from rC and then heat-treated without heat treatment. . In this case, therefore, the SBD with intervening poly84 layer
It is also possible to control the barrier hide by using only one.

(6) Examples of the invention The present invention will now be set forth with reference to all of the accompanying drawings.

FIG. 1 shows one preferred method for manufacturing semiconductors according to the present invention. A sectional view is shown below.

First, in the process (al), after thermally oxidizing the 84 substrate 1, a CVD oxide film is added, and the oxide film (8402) is grown as the insulating layer 2, and then this layer is controlled etched to form the PN junction forming part. The windows of the PN-J and SBD forming areas 5BD-1 and 8BD-2 are completely opened. Control etching is performed using two types of masks, first to the depth of 5BD-2 and then to the area of 8BD-2. Mask and etch to the depth of PN-J and 5BD-1.-For example, when the thickness of layer 2 is 4000 mm deep and the depth of 5BD-2 is 301) O
It is A. Creating a difference in the depth of the 8BD forming portions in this way is necessary in order to stabilize the poly 81 layer etching layer 8' of 5BD-2 in the subsequent step (d). A dry process such as reactive ion etching (referred to as RIII) can be used for this etching.

Next, poly-Si is placed above the insulating layer 2 where the window opening has been completed.
Layer 5 is completely coated (step (b)). This can be done according to conventional methods, for example by CVD.

(c) VC>Ec, forming a window PN-Jog KPNm combination. This provides a suitable diffused impurity source inside the window,
For example, this can be achieved by introducing PSG or the like or by implanting impurity ions. 4 in the diagram
indicates that impurities have diffused into the Si substrate 1. General heat treatment conditions are: temperature 900-1200℃;
And the time is 30 seconds or more. Through this heat treatment, 8B
The D-forming part can be stabilized. Further, this heat treatment may also be performed as a heat treatment for forming a PN junction type, or may be performed subsequent to a heat treatment for forming a PNMI bond.

In step C, a window 5BD is formed as a preliminary step for forming an SBD having a (wiring layer) on (81 substrate) structure.
-2 portion of the insulating layer 2 and poly-Si layer 3 are removed.

Similar to the window opening in the previous step (a), a dry process can be used for this.

Finally, there is a wiring step (e). First, as in the conventional method, a wiring metal (in this case, At, which contains S in a total amount of 1π),
/8j) 5 'i Completely overturn. Here, the At/St film 5 was formed using all magnetron sputtering equipment. Next, patterning of the A wiring, that is, A
The t/St film 5 and poly-Si layer 3 are etched. In this way, a wiring having a cross section as shown in step (e) is obtained. In the figure, from the left: PN junction, At/
Sl on poly 81 layer on Si substrate (7) SBD
, and an SBD with an A4/81 on81 board.

This manufacturing method is notable for its good process stability.

FIG. 2 shows another preferred method for manufacturing semiconductors according to the present invention. This method also has the same basic 1c as the method shown in FIG. 1, so the same components are given the same numbers and symbols.

In step (a), the 81 substrate 1 is oxidized to form an insulating layer (S
i02)2, then PN-J, 8BD-1
and open the window of 19BD-2. These windows have
Make sure that no residue remains on the insulating layer 2.

In step (b), a poly S1 layer 3 is formed over the entire surface of the subsequent 81 substrate 1.

In step (C), a PN junction is formed in the window PN-J. This is similar to step (C) in Figure 1, and the impurity sound S+
This is done by diffusing it onto the substrate 1.

In step (d), the insulating layer 2 and poly-Si layer 3 in the window 5BD-2 are etched. Etching in this case is carried out in two stages: first, dry etching is carried out for a rough finish, and etching is carried out almost to the final dimension, and then a slight (3.
00 Å or more), for example, nitric acid 30
This is carried out using a 70% decahydrofluoric acid crab solution. By using such an etching method, the characteristics of the resulting 8BD can be completely stabilized.

Finally, patterning of At wiring? Let's do it. even here,
As in step (e) of FIG. 1, A4/5t (811%) was used as the wiring metal. The configuration of the obtained wiring is also the same as the first one.
The process is the same as step (e) in the figure. This manufacturing method is particularly
It is noteworthy that it greatly contributes to the improvement of f*maro.

(7) Effects of the Invention According to the present invention, it is possible to use the conventional process as is, so it is very easy and simple to produce a plurality of Ss with different barrier hides.
A semiconductor device having a BD can be manufactured. Furthermore, according to the present invention, the stability of the process is good, and
The degree of integration can be completely increased.

[Brief explanation of drawings]

FIGS. 1 and 2 each illustrate, in sequential cross-section, a preferred method for manufacturing semiconductors in accordance with the present invention. In the figure, 1 is an 81 substrate, 2 is an insulating layer, 3 is a poly layer, 4 is an impurity diffusion region, 5 is an htisi wiring layer, PN-J is a PN
The joint forming part, and 8BD-1 and 8BD-2 are 8BD
It is formed in the formation part. Patent Applicant: Fujitsu Limited, Patent Attorney: Akira Misaki, Patent Attorney, Kazuyuki Nishidate, Patent Attorney: 1) Yukio, Patent Attorney: Akira Yamaguchi, Figure 1, Figure 2

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device having a Schottky barrier diode of at least 2FFI with different barrier heights, wherein when forming the diode, a polysilicon layer is formed between a metal electrode wiring layer and a semiconductor substrate. A method of manufacturing a semiconductor device characterized by forming a semiconductor device in combination with and without intervening layers. 2. When a polysilicon layer is interposed between the metal electrode wiring layer and the semiconductor substrate, the semiconductor device according to claim 1, wherein the polysilicon layer is doped or not doped with an impurity. Production method.