JPS5929462A - Hetero-junction element - Google Patents
Hetero-junction elementInfo
- Publication number
- JPS5929462A JPS5929462A JP57140105A JP14010582A JPS5929462A JP S5929462 A JPS5929462 A JP S5929462A JP 57140105 A JP57140105 A JP 57140105A JP 14010582 A JP14010582 A JP 14010582A JP S5929462 A JPS5929462 A JP S5929462A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- superlattice
- hetero
- type
- heterojunction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
Landscapes
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はへテロ接合を用いる半導体装置においてその接
合界面の平坦性を増して電子の高移動度化を図ったヘテ
ロ接合素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a heterojunction element in a semiconductor device using a heterojunction, in which the flatness of the junction interface is increased to achieve high electron mobility.
バンドギャップの異なる2つの半導体のへテロ接合にお
いて、バンドギャップの大きい半導体のみを選択的にN
型にドープすることにより、ヘテロ接合界面に移動度の
大きい二次元電子が生じることが知られている。通常、
N型AtxGa (+ −x )AII とG a
A s とのへテロ接合が利用され、マイクロ波素子及
びGaAgICへの研究、開発がなされている。以下、
ヘテロ接合としてN型ALxGa(1−x)AIl
GaAs を例にとって説明する0第1図は従来のこの
種のへテロ接合断面を示し、図において、(1)は半絶
縁性G a A s基板、(2)は高品質ノンドープG
1As−、(3)はN型AtxGa (1−x )As
。In a heterojunction of two semiconductors with different bandgaps, only the semiconductor with a large bandgap is selectively N
It is known that two-dimensional electrons with high mobility are generated at the heterojunction interface by doping the mold. usually,
N-type AtxGa (+ -x)AII and Ga
Heterojunctions with A s are being utilized to conduct research and development into microwave devices and GaAg ICs. below,
N-type ALxGa(1-x)AIl as a heterojunction
Taking GaAs as an example, Figure 1 shows a cross section of a conventional heterojunction of this type. In the figure, (1) is a semi-insulating GaAs substrate, and (2) is a high quality non-doped
1As-, (3) is N-type AtxGa (1-x)As
.
(4)は前記c a A l (2)とAtx Ga
(1−x ) As (3)とのへテロ接合界面に生じ
る二次元電子である。(4) is the above c a A l (2) and Atx Ga
(1-x) These are two-dimensional electrons generated at the heterojunction interface with As (3).
このような従来のへテロ接合においては、Nuhtx
Ga < 1− X )All (3)の下にGILA
ll(2)がある場合は接合界面での二次元電子(4)
は高移動度金有するが、逆にN型AtxGa (1−x
)AII (3)の上にG a A 5(2)がある
場合には高移動度を有さない。これは、c a A 1
1 (2)の上にAtX GIL < s −x >
As(3)を成長した時のへテロ接合界面は平坦である
が、AtxGIL(1−x ) A 8(3)の上にG
a A s (2)を成長したときのへテロ接合界面
は」′″坦でなくなり、その結果として移動度の高速化
が阻止されている0
本発明は以上の点に鑑みてなされたもので、バンドギャ
ップの異なる2つの半導体の超格子と、この超格子を構
成する半導体のうちバンドギャップの狭い半導体とのへ
テロ接合を用いる半導体装1?tにおいて超格子のみを
選択的にN型にドープし、ヘテロ接合界面に生じる電子
をキャリヤとして用いることにニジ、ヘテロ接合界面の
平坦性金増して電子の高移動度化を図ったヘテロ接合素
子を提供することを目的としている。In such a conventional heterojunction, Nuhtx
Ga < 1-X) GILA under All (3)
If there is ll (2), two-dimensional electrons at the junction interface (4)
has a high mobility metal, but on the contrary, N-type AtxGa (1-x
) A II (3) with G a A 5 (2) does not have high mobility. This is c a A 1
1 On top of (2) AtX GIL < s - x >
When As(3) is grown, the heterojunction interface is flat, but GIL(1-x)A8(3)
When a A s (2) is grown, the heterojunction interface is no longer flat, and as a result, the increase in mobility is prevented.The present invention was made in view of the above points. In a semiconductor device 1?t that uses a heterojunction between a superlattice of two semiconductors with different band gaps and a semiconductor with a narrow band gap among the semiconductors constituting this superlattice, only the superlattice is selectively made into N type. The object of the present invention is to provide a heterojunction element in which the flatness of the heterojunction interface is increased by doping and using electrons generated at the heterojunction interface as carriers, thereby increasing the mobility of electrons.
以下、本発明の実施例を図に基いて説明する。Embodiments of the present invention will be described below with reference to the drawings.
第2図は本発明による一実施例を示すヘテロ接合断面図
である。この実施例では、半絶縁性G&As基板(11
)にノンドープG mA s 、 kl Am超格子(
12)を形成するとともに、このGaA3 、AtA内
超内子格子2)上にN型のGaAs、AtAs超格子(
13)を形成し、さらに前記GaAs 、 ALA!I
超格子(13)上に高品質ノンドープGaAg (14
)を形成することによυ、N型GaAs 、AtAl1
超格子(13〕とG a A 5(14)間においてへ
テロ接合を作成したものである。FIG. 2 is a sectional view of a heterojunction showing an embodiment according to the present invention. In this example, a semi-insulating G&As substrate (11
) with undoped G mAs , kl Am superlattice (
12), and on this GaA3, AtA superinner lattice 2), an N-type GaAs, AtAs superlattice (2) is formed.
13) and further the GaAs, ALA! I
High quality undoped GaAg (14) on superlattice (13)
) by forming υ, N-type GaAs, AtAl1
A heterojunction is created between the superlattice (13) and G a A 5 (14).
なお、(15)ij二次元電子である。Note that (15) ij is a two-dimensional electron.
このように、上記実施例のへテロ接合によると、Atx
Ga(1−x)Asと同じバンドギャップを有するG
a A s とA I A 11 との超格子(13
)の上にG RA n(14)を成長した場合のへテロ
接合界面は平坦となるため、第2図に示す如く、N型A
txGa (1−x)A8の代りにN型のG a A
s とAtARとの超格子(13) ffi用いること
により、Ga A s (14)が土の11/を造にお
いても電子の移動度の高速化を達成することができる。Thus, according to the heterojunction of the above embodiment, Atx
G with the same bandgap as Ga(1-x)As
A superlattice of a A s and A I A 11 (13
) When GRA n(14) is grown on top of ), the heterojunction interface becomes flat, so as shown in Figure 2, N-type A
txGa (1-x) N-type Ga A instead of A8
By using the superlattice (13) ffi of s and AtAR, high-speed electron mobility can be achieved even when Ga As (14) is 11/1 of the soil.
なお、上述ではGaAl1+ AtxGa(1−x)A
sへテロ接合の場合について説明したが、本発明はこれ
に限定されるものでVよないことはいうまでもない。In addition, in the above, GaAl1+ AtxGa(1-x)A
Although the case of s heterojunction has been described, it goes without saying that the present invention is limited to this and is not limited to V.
以上説明したように、本発明によれば、/ζンドギャッ
プの異なる2つの半導体の超格子とこの超格子を構成す
る半導体のうちノくンドギャップの狭い半導体とのへテ
ロ接合において、超格子のみを選択的にN型にドープし
、ヘテロ接合界面に生じる電子をキャリヤとして用いる
ことにより、ヘテロ接合界面の平坦性が増して電子の高
移動度化を図ることができる効果がある0As explained above, according to the present invention, in a heterojunction between a superlattice of two semiconductors with different /ζ band gaps and a semiconductor with a narrow band gap among the semiconductors constituting this superlattice, the superlattice By selectively doping only N-type atoms and using the electrons generated at the heterojunction interface as carriers, the flatness of the heterojunction interface increases and electron mobility can be increased.
第1図は従来の一例を示すヘテロ接合の断面図、第2図
は本発明にLる一実施例を示すヘテロ接合の断面図であ
る。
(11)・・・・半絶縁性G a A s基板、(12
)・・・・ノンドープGa A s + A tA 8
超格子、(13) −−−・NuMGaAg 、AtA
s超格子、−(14)・・・・高品質ノンドープGaA
s、 (15)・φ・の二次元電子〇代理人 葛 野
侶 −
第1図
第2図FIG. 1 is a sectional view of a heterojunction showing a conventional example, and FIG. 2 is a sectional view of a heterojunction showing an embodiment of the present invention. (11)...Semi-insulating GaAs substrate, (12
)...Non-doped Ga As + AtA 8
Superlattice, (13) --- NuMGaAg, AtA
s superlattice, -(14)...High quality non-doped GaA
s, (15)・φ・Two-dimensional electron 〇 agent Kuzuno
- Figure 1 Figure 2
Claims (1)
格子を構成する半導体のうち/(ンドギャップの狭い半
導体とのへテロ接合を用いる半導体装置において、前記
超格子のみを選択的にN型にドープし、ヘテロ接合界面
に生じる電子をキャリヤとして用いることを特徴とする
ヘテロ接合素子0In a semiconductor device using a heterojunction between a superlattice of two semiconductors with different bandgaps and a semiconductor with a narrow bandgap among the semiconductors constituting the superlattice, only the superlattice is selectively converted to N-type. A heterojunction element 0 characterized in that it is doped and uses electrons generated at the heterojunction interface as carriers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57140105A JPS5929462A (en) | 1982-08-10 | 1982-08-10 | Hetero-junction element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57140105A JPS5929462A (en) | 1982-08-10 | 1982-08-10 | Hetero-junction element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5929462A true JPS5929462A (en) | 1984-02-16 |
| JPH0243341B2 JPH0243341B2 (en) | 1990-09-28 |
Family
ID=15261050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57140105A Granted JPS5929462A (en) | 1982-08-10 | 1982-08-10 | Hetero-junction element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5929462A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5963769A (en) * | 1982-10-05 | 1984-04-11 | Agency Of Ind Science & Technol | high speed semiconductor device |
| JPS61289673A (en) * | 1985-06-18 | 1986-12-19 | Sumitomo Electric Ind Ltd | Compound semiconductor device |
| JPS624366A (en) * | 1985-07-01 | 1987-01-10 | Fujitsu Ltd | Hot electron transistor |
| JPS6251266A (en) * | 1985-08-30 | 1987-03-05 | Sony Corp | Semiconductor device |
| CN115207089A (en) * | 2022-07-19 | 2022-10-18 | 江苏华兴激光科技有限公司 | Radio frequency chip epitaxial wafer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132074A (en) * | 1979-04-02 | 1980-10-14 | Max Planck Gesellschaft | Hetero semiconductor and method of using same |
| JPS5676581A (en) * | 1979-11-26 | 1981-06-24 | Ibm | Semiconductor device |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
-
1982
- 1982-08-10 JP JP57140105A patent/JPS5929462A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132074A (en) * | 1979-04-02 | 1980-10-14 | Max Planck Gesellschaft | Hetero semiconductor and method of using same |
| JPS5676581A (en) * | 1979-11-26 | 1981-06-24 | Ibm | Semiconductor device |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5963769A (en) * | 1982-10-05 | 1984-04-11 | Agency Of Ind Science & Technol | high speed semiconductor device |
| JPS61289673A (en) * | 1985-06-18 | 1986-12-19 | Sumitomo Electric Ind Ltd | Compound semiconductor device |
| JPS624366A (en) * | 1985-07-01 | 1987-01-10 | Fujitsu Ltd | Hot electron transistor |
| JPS6251266A (en) * | 1985-08-30 | 1987-03-05 | Sony Corp | Semiconductor device |
| CN115207089A (en) * | 2022-07-19 | 2022-10-18 | 江苏华兴激光科技有限公司 | Radio frequency chip epitaxial wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0243341B2 (en) | 1990-09-28 |
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