JPS5931993B2 - semiconductor rectifier - Google Patents
semiconductor rectifierInfo
- Publication number
- JPS5931993B2 JPS5931993B2 JP15201376A JP15201376A JPS5931993B2 JP S5931993 B2 JPS5931993 B2 JP S5931993B2 JP 15201376 A JP15201376 A JP 15201376A JP 15201376 A JP15201376 A JP 15201376A JP S5931993 B2 JPS5931993 B2 JP S5931993B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- single crystal
- type
- silicon single
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は高速でしかも順方向電位降下を低くした高信頼
度の電力用ダイオードの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a highly reliable power diode that is fast and has a low forward potential drop.
コンピュータの端末機器等の安定化電源用として、高速
かつ低損失の電力用ダイオードの需要が高まつてきてい
る。ところで従来高速ダイオードを得るには、pn接合
ダイオードに金などの再結合中心となる不純物(ラィフ
タィムキラー)を添加し、少数キャリヤのライフタイム
を小さくすることにより高速化を図つてきた。ところが
この方法によるとライフタイムキラーを導入した半導体
層のバルク抵抗が大きくなるため、ダイオード全体の順
方向電位降下が大きくなるという欠点がある。このため
ダイオードの電力損失が増大するのみならずジュール熱
発生が大きくなり、冷却用フィンが大型化するなどコス
ト高の原因にもなつていた。これらの問題を解決するた
めに金属一半導体接触整流層を用いたいわゆるショット
キーバリヤダイオードが、高速かつ低損失のダイオード
として知られている。しかしこのショットキーバリヤダ
イオードは従来のpn接合ダイオードに比べ逆方向洩れ
電流が3桁ほど大きく、また逆耐圧も大きくないという
欠点がある。またショットキーバリヤダイオードはpn
接合ダイオードに比べ許容される最大接合温度が低いの
で熱放散を良くするために特別の配慮が要求される欠点
をも有している。本発明の目的は上記した従来技術の欠
点を除去し、低損失、高速、かつ高信頼性を有する新規
なpn接合ダイオードを提供することである。Demand for high-speed, low-loss power diodes for stabilizing power supplies for computer terminal equipment and the like is increasing. Conventionally, in order to obtain a high-speed diode, high speed has been achieved by adding an impurity such as gold to a pn junction diode that becomes a recombination center (lifetime killer) to shorten the lifetime of minority carriers. However, this method has the disadvantage that the bulk resistance of the semiconductor layer into which the lifetime killer is introduced increases, and the forward potential drop across the diode increases. This not only increases the power loss of the diode, but also increases Joule heat generation, which increases the size of the cooling fins and increases costs. To solve these problems, a so-called Schottky barrier diode using a metal-semiconductor contact rectifying layer is known as a high-speed and low-loss diode. However, this Schottky barrier diode has disadvantages in that its reverse leakage current is three orders of magnitude larger than that of conventional pn junction diodes, and its reverse breakdown voltage is also not large. Also, the Schottky barrier diode is pn
They also have the disadvantage that the maximum allowable junction temperature is lower than that of junction diodes, requiring special consideration to improve heat dissipation. An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and provide a new pn junction diode that has low loss, high speed, and high reliability.
以下本発明の一実施例ダイオードの製法について第1図
を用いて説明する。まず不純物としてアンチモンを3×
1018at0mS/CliL含む厚さ200Itm(
7)n+型基板11上に、不純物として燐を1×101
5at0ms/(−d含み厚さ8μMf)n型ベース層
12を気相成長法により形成する(a)。A method of manufacturing a diode according to an embodiment of the present invention will be described below with reference to FIG. First, add antimony 3× as an impurity.
1018at0mS/Thickness 200Itm including CliL (
7) On the n+ type substrate 11, 1×101 phosphorus is added as an impurity.
5at0ms/(thickness 8μMf including -d) n-type base layer 12 is formed by vapor phase epitaxy (a).
次にn型ベース層12の表面にジボランを含むトリクロ
ロシランを用いた900℃、60分の気相成長法によつ
て硼素を5×1018at0ms/CTL含み厚さ25
μm(7)p型多結晶層13を形成する。Next, boron was deposited on the surface of the n-type base layer 12 at 5×10 18 at0 ms/CTL by vapor phase growth using trichlorosilane containing diborane at 900° C. for 60 minutes to a thickness of 25
μm(7) p-type polycrystalline layer 13 is formed.
1この時p型多結晶層13の形成と同時にp型多結晶層
13から硼素が。1 At this time, boron is released from the p-type polycrystalline layer 13 simultaneously with the formation of the p-type polycrystalline layer 13.
型ベース層12に拡散され、不純物濃度が1X1017
at0ms/d、厚さ0.05μm(7)p型単結晶層
14が形成される(b)。つぎにn+型基板11の露出
主表面に9000C1で燐を30分拡散し、不純物濃度
1×1020at0ms/CTL、厚さ1μMOn+十
型単結晶層15を形成する(c)。つぎに真空蒸着法で
Cr層16を厚さ0.1μmに、Ni層17を厚さ0.
8μmに、Ag層18を21.6μmに、p型多結晶層
13とn+型単結晶層15の両面にそれぞれ形成する(
d)。Diffused into the mold base layer 12, the impurity concentration is 1X1017
At 0 ms/d and a thickness of 0.05 μm (7) a p-type single crystal layer 14 is formed (b). Next, phosphorus is diffused on the exposed main surface of the n+ type substrate 11 at 9000 C1 for 30 minutes to form an impurity concentration of 1×1020 at0 ms/CTL and a thickness of 1 μM On+10 type single crystal layer 15 (c). Next, the Cr layer 16 is formed to a thickness of 0.1 μm using a vacuum evaporation method, and the Ni layer 17 is formed to a thickness of 0.1 μm.
The Ag layer 18 is formed to a thickness of 8 μm and the Ag layer 18 is formed to a thickness of 21.6 μm on both sides of the p-type polycrystalline layer 13 and the n + type single-crystalline layer 15 (
d).
つぎにサンドカツト法でベベルを有するペレツトにペレ
タイズし、Pn接合露出端部を含むペレツト端面をシリ
コーンゴム19でコーテイングす2る。Next, the pellets are pelletized into beveled pellets by a sand cut method, and the end faces of the pellets, including the exposed ends of the Pn junction, are coated with silicone rubber 19.
次にp型多結晶層13側の電極層16乃至18上に半田
層20を介して主電極21を取付けてダイオードが完成
する(e)。Next, the main electrode 21 is attached on the electrode layers 16 to 18 on the p-type polycrystalline layer 13 side via the solder layer 20, and the diode is completed (e).
このようなダイオードは通常、金属缶内に封入されて用
いられる。その場5合、n+十型単結晶層15側の電極
層16乃至18が半田層を介して金属缶底部に接着され
、この金属缶が他方の主電極となる。本発明の構造で重
要な点はp型多結晶層13の不純物濃度αをどうコント
ロールするかというこ 5とである。Such diodes are typically used sealed in metal cans. In the case of in-situ 5, the electrode layers 16 to 18 on the side of the n+ type single crystal layer 15 are bonded to the bottom of the metal can via a solder layer, and this metal can becomes the other main electrode. An important point in the structure of the present invention is how to control the impurity concentration α of the p-type polycrystalline layer 13.
第2図は本発明ダイオードに順電流を通電した時の各部
の電位降下を示す図であるが、この構造のダイオードの
順方向電位降下VFは、で表わされる。ここで、
Vc;p型多結晶層13と電極層16乃至1とのコンタ
クトドロツプVp+;p型多結晶層13内での電位降下
VJ:接合での電位降下とn型ベース層12内での電位
降下の和VN+:n+型基板11内での電位降下
Vσ;n+十型単結晶層25と電極層16乃至18との
コンタクトドロツプである。FIG. 2 is a diagram showing the potential drop at various parts when a forward current is applied to the diode of the present invention, and the forward potential drop VF of the diode with this structure is expressed as follows. Here, Vc: Contact drop between the p-type polycrystalline layer 13 and the electrode layers 16 to 1 Vp+: Potential drop within the p-type polycrystalline layer 13 VJ: Potential drop at the junction and within the n-type base layer 12 Sum of potential drops VN+: Potential drop Vσ within the n+ type substrate 11; Contact drop between the n+ single crystal layer 25 and the electrode layers 16 to 18.
ここでp型多結晶層13の不純物濃度αが影響するのは
VCVP+VJの3項目である。Here, the impurity concentration α of the p-type polycrystalline layer 13 influences three items: VCVP+VJ.
従つてαの値はC,Vp+,Jの和を最小にするよう選
ぶのがよい。以下この点について説明する。第3図は本
発明者等が実験によつて得たαとVc,Vp+の関係を
示す図である。一般に多結晶半導体層は金属とのコンタ
クトは良好であるが、不純物濃度が1018at0ms
/へ以下になるとコンタクトドロツプVcは急速に大き
くなる。一方p型多結晶層13内での電位降下Vp+も
不純物濃度αが小さくなると、大きくなる。一方n型ベ
ース層12の厚さを30μm以下にしてしかもp型単結
晶層14の不純物総量Qを1011〜1014at0m
s/dにするとダイオードの低損失と高速化が同時に達
成できることをすでに本発明者等は提案している(特願
昭50−93109号)。Therefore, the value of α should be selected so as to minimize the sum of C, Vp+, and J. This point will be explained below. FIG. 3 is a diagram showing the relationship between α, Vc, and Vp+ obtained through experiments by the inventors. In general, polycrystalline semiconductor layers have good contact with metal, but the impurity concentration is 1018at0ms.
/ below, the contact drop Vc increases rapidly. On the other hand, the potential drop Vp+ within the p-type polycrystalline layer 13 also increases as the impurity concentration α decreases. On the other hand, the thickness of the n-type base layer 12 is set to 30 μm or less, and the total amount of impurities Q of the p-type single crystal layer 14 is set to 1011 to 1014at0m.
The present inventors have already proposed that low loss and high speed of the diode can be achieved at the same time by using s/d (Japanese Patent Application No. 50-93109).
そこで述べているようにQを下げると、接合での電位降
下とn型ベース層12内での電位降下の和VJは小さく
なる。従つてαが小さくなるとQも小さくなるので、V
Jは減少する。これを示したのが第4図の曲線aである
。第3図と第4図の曲線aとからC,VP+,VJの和
を求めると第4図中曲線bの如くなり、αとしては5×
1018at0Ins/〜近傍を選ぶのが最も好ましい
ことがわかる。次にN+を小さくするためにはn+型基
板11の不純物濃度を上げることが必要となる。As stated therein, when Q is lowered, the sum VJ of the potential drop at the junction and the potential drop within the n-type base layer 12 becomes smaller. Therefore, as α becomes smaller, Q also becomes smaller, so V
J decreases. Curve a in FIG. 4 shows this. If we calculate the sum of C, VP+, and VJ from curves a in Figures 3 and 4, we get curve b in Figure 4, and α is 5×
It can be seen that it is most preferable to select a value in the vicinity of 1018at0Ins/. Next, in order to reduce N+, it is necessary to increase the impurity concentration of the n+ type substrate 11.
ところがn+型基板11の不純物濃度を大きくしすぎる
と、n型ベース層12へn型不純物がn+型基板11か
ら拡散し、ダイオードの逆耐圧が小さくなる。例えば耐
圧150Vを得るためのn+型基板21の不純物濃度の
上限は3X1018at0ms/〜である。ところで3
×1018at0ms/CTilの不純物濃度では電極
層16乃至18とのコンタクト、ドロツプVσを0.0
1以下にすることができない。従つてVσを小さくする
ためにn+型基板21の表面に新たにn+十型半導体単
結晶層15を形成する必要がある。n+十型単結晶層1
5の不純物濃度としては1019at0ms/〜以上必
要である。一対のオーミツクコンタクト電極用金属とし
てはCrが好ましく、第2層、第3層にそれぞれNl,
Agを選ぶことにより、外部リード端子と半田付け可能
な多層電極層16乃至18を形成できる。However, if the impurity concentration of the n+ type substrate 11 is made too high, the n type impurity will diffuse from the n+ type substrate 11 into the n type base layer 12, and the reverse breakdown voltage of the diode will decrease. For example, the upper limit of the impurity concentration of the n+ type substrate 21 to obtain a breakdown voltage of 150 V is 3×10 18 at0 ms/~. By the way 3
At an impurity concentration of ×1018at0ms/CTil, contact with electrode layers 16 to 18 and drop Vσ are 0.0.
It cannot be lower than 1. Therefore, in order to reduce Vσ, it is necessary to newly form an n+ type semiconductor single crystal layer 15 on the surface of the n+ type substrate 21. n+10 type single crystal layer 1
The impurity concentration of 5 is required to be 1019 at0 ms/~ or more. Cr is preferable as the metal for the pair of ohmic contact electrodes, and Nl and Nl are used in the second and third layers, respectively.
By selecting Ag, it is possible to form multilayer electrode layers 16 to 18 that can be soldered to external lead terminals.
これらの電極層とn+十型単結晶層、n+型基板を採用
することによりVN+とVσの和は0.02以下にする
ことができるので、トータルとしてのVFは0.8V以
下にすることができる。By using these electrode layers, an n+ type single crystal layer, and an n+ type substrate, the sum of VN+ and Vσ can be made 0.02 or less, so the total VF can be made 0.8V or less. can.
以上の様に、本発明の構造によればダイオードの順方向
電位降下を0.8V以下にすることができ、これにより
従来の金拡散方式の高速ダイオードの順方向電位降下の
平均値である1,2Vに比べ大幅な低減が可能になつた
。As described above, according to the structure of the present invention, the forward potential drop of the diode can be reduced to 0.8 V or less, which is the average value of the forward potential drop of the conventional gold diffusion type high-speed diode. , it has become possible to significantly reduce the voltage compared to 2V.
次に本発明の素子が従来のPn接合ダイオードと同等の
逆耐圧と信頼性をもつことを説明する。Next, it will be explained that the element of the present invention has reverse breakdown voltage and reliability equivalent to that of a conventional Pn junction diode.
すでに述べたようにダイオードの順方向電位降下を下げ
るにはp型単結晶層14の不純物総量Qを小さくすれば
よいが、Qを小さくするためにはp型単結晶層の厚さを
小さくする必要がある。この層の厚さを薄くするとPn
接合面が表面の多層電極層の熱的歪の影響を受けるため
耐圧低下の原因となるが、第1図eに示すように薄いp
型単結晶層14が厚いp型多結晶層13によつて電極層
16,17,18から隔てられているため、多層電極層
の歪を受けることはなく、十分な逆耐圧特性を得ること
ができる。またPn接合端面を保護するシリコーンゴム
19は、Pn接合部の最大電界強度に耐えるためには1
01tm以上の厚さが必要である。As already mentioned, the forward potential drop of the diode can be reduced by reducing the total amount of impurities Q in the p-type single crystal layer 14, but in order to reduce Q, the thickness of the p-type single crystal layer is reduced. There is a need. If the thickness of this layer is reduced, Pn
The bonding surface is affected by the thermal strain of the multilayer electrode layer on the surface, which causes a decrease in breakdown voltage.
Since the type single crystal layer 14 is separated from the electrode layers 16, 17, and 18 by the thick p-type polycrystalline layer 13, it is not affected by the strain of the multilayer electrode layer, and sufficient reverse breakdown voltage characteristics can be obtained. can. In addition, the silicone rubber 19 that protects the Pn joint end face must be
A thickness of 0.01 tm or more is required.
Qを小さくするためにp型単結晶層の厚さを薄くし、か
つp型多結晶層13が存在しない場合には第5図aに示
す如く、Pn接合露出端部でのシリコーンコムの厚さD
は1〜2μ程度と薄くなり、十分な耐圧を得ることがで
きない。これに対し本発明による構造では厚さ25μM
O)p型多結晶層13の存在により、接合端面でのシリ
コーンゴムの厚さDは15μ程度となり(第5図b)十
分な耐圧を得ることができる。耐圧を得るためにはp型
多結晶層13の厚さは15μm以上が好ましい。このよ
うに本発明によれば、従来のPn接合ダイオードと同等
の逆耐圧と信頼性を得ることができる。In order to reduce Q, when the p-type single crystal layer is thinned and the p-type polycrystalline layer 13 is not present, the thickness of the silicone comb at the exposed end of the Pn junction is reduced as shown in FIG. 5a. SaD
is as thin as about 1 to 2 μm, making it impossible to obtain sufficient withstand voltage. In contrast, the structure according to the present invention has a thickness of 25 μM.
O) Due to the presence of the p-type polycrystalline layer 13, the thickness D of the silicone rubber at the joint end face is approximately 15 μm (FIG. 5b), making it possible to obtain a sufficient withstand voltage. In order to obtain a breakdown voltage, the thickness of the p-type polycrystalline layer 13 is preferably 15 μm or more. As described above, according to the present invention, it is possible to obtain reverse breakdown voltage and reliability equivalent to those of conventional Pn junction diodes.
試作ダイオードの逆耐圧は150V、順方向電位降下は
30Aの順電流時において0.78V、逆回復時間80
nsecであり、逆耐圧については従来のPn接合と同
程度の水準を維持しつつ、低損失と高速化の同時達成が
可能となつた。The reverse breakdown voltage of the prototype diode is 150V, the forward potential drop is 0.78V at a forward current of 30A, and the reverse recovery time is 80V.
nsec, making it possible to simultaneously achieve low loss and high speed while maintaining the same level of reverse breakdown voltage as conventional Pn junctions.
以上詳細に説明したように本発明によれば低損失、高速
でかつ高信頼性を有するPn接合ダイオードを得るのに
効果がある。As described above in detail, the present invention is effective in obtaining a Pn junction diode having low loss, high speed, and high reliability.
第1図は本発明の一実施例ダイオード及びその主要製造
工程を示す図、第2図は本発明ダイオードの各部の順方
向電位降下を示す説明図、第3図はp型多結晶層不純物
濃度αと、Vc,p+との関係を示す図、第4図はp型
多結晶層不純物濃度αとJ(a)、及びVc+p+VJ
(b)との関係を示す図、第5図はp型多結晶層の存在
しない場合(a)、及び本発明ダイオード(b)のペレ
ツト端面のシリコーンゴムのコーテイングの様子を示す
図、である。Fig. 1 is a diagram showing a diode according to an embodiment of the present invention and its main manufacturing process, Fig. 2 is an explanatory diagram showing the forward potential drop of each part of the diode of the present invention, and Fig. 3 is a diagram showing the impurity concentration of the p-type polycrystalline layer. Figure 4 shows the relationship between α, Vc, and p+.
FIG. 5 is a diagram showing the state of silicone rubber coating on the end face of the pellet of the present invention diode (b) in the case (a) where no p-type polycrystalline layer is present. .
Claims (1)
1のシリコン単結晶層の一方の面に隣接しそれより高い
不純物濃度を有するn型導電型の第2のシリコン単結晶
層と、第1のシリコン単結晶層の他方の面に隣接しそれ
より低い不純物濃度を有する厚さ30μm以下のn型導
電型の第3のシリコン単結晶層と、第3のシリコン単結
晶層に隣接して第3のシリコン単結晶との間にpn接合
を形成しかつ10^1^1〜10^1^4atoms/
cm^2の不純物総量を有するp型導電型の第4のシリ
コン単結晶層と、第4のシリコン単結晶層に隣接しこの
層へのp型不純物の拡散源となり5×10^1^8at
oms/cm^3近傍の不純物濃度を有するシリコン多
結晶層と、第2のシリコン単結晶層およびシリコン多結
晶層表面にそれぞれ形成されシリコン層側から順に第1
層がCr、第2層がNi、第3層がAgから成る多層オ
ーミック電極層と、少なくともpn接合の露出端部をお
おうシリコーンゴムとを具備することを特徴とする半導
体整流装置。1 a first silicon single crystal layer having an n-type conductivity type; a second silicon single crystal layer having an n-type conductivity type adjacent to one surface of the first silicon single crystal layer and having a higher impurity concentration; , a third silicon single crystal layer of n-type conductivity type having a thickness of 30 μm or less and having a lower impurity concentration adjacent to the other surface of the first silicon single crystal layer; and adjacent to the third silicon single crystal layer. to form a pn junction with the third silicon single crystal, and 10^1^1 to 10^1^4 atoms/
A fourth silicon single crystal layer of p-type conductivity type having a total amount of impurities of cm^2 and a layer adjacent to the fourth silicon single crystal layer serving as a diffusion source of p-type impurities to this layer are 5×10^1^8at.
A silicon polycrystalline layer having an impurity concentration near oms/cm^3, a second silicon single crystal layer, and a silicon polycrystalline layer formed on the surfaces of the silicon polycrystalline layer and the first silicon layer in order from the silicon layer side.
A semiconductor rectifier comprising: a multilayer ohmic electrode layer consisting of a layer of Cr, a second layer of Ni, and a third layer of Ag; and silicone rubber covering at least an exposed end of a pn junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15201376A JPS5931993B2 (en) | 1976-12-20 | 1976-12-20 | semiconductor rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15201376A JPS5931993B2 (en) | 1976-12-20 | 1976-12-20 | semiconductor rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5376764A JPS5376764A (en) | 1978-07-07 |
| JPS5931993B2 true JPS5931993B2 (en) | 1984-08-06 |
Family
ID=15531144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15201376A Expired JPS5931993B2 (en) | 1976-12-20 | 1976-12-20 | semiconductor rectifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5931993B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6376063U (en) * | 1986-11-07 | 1988-05-20 | ||
| JPS6447872U (en) * | 1987-09-18 | 1989-03-24 |
-
1976
- 1976-12-20 JP JP15201376A patent/JPS5931993B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6376063U (en) * | 1986-11-07 | 1988-05-20 | ||
| JPS6447872U (en) * | 1987-09-18 | 1989-03-24 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5376764A (en) | 1978-07-07 |
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