JPS5932194A - Manufacturing method of electronic component mounting body - Google Patents

Manufacturing method of electronic component mounting body

Info

Publication number
JPS5932194A
JPS5932194A JP14114382A JP14114382A JPS5932194A JP S5932194 A JPS5932194 A JP S5932194A JP 14114382 A JP14114382 A JP 14114382A JP 14114382 A JP14114382 A JP 14114382A JP S5932194 A JPS5932194 A JP S5932194A
Authority
JP
Japan
Prior art keywords
resistor
conductor layer
paste
layer
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14114382A
Other languages
Japanese (ja)
Other versions
JPH0430199B2 (en
Inventor
恒雄 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14114382A priority Critical patent/JPS5932194A/en
Publication of JPS5932194A publication Critical patent/JPS5932194A/en
Publication of JPH0430199B2 publication Critical patent/JPH0430199B2/ja
Granted legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】[Detailed description of the invention]

本発BAtIまセラミック基板、特に抵抗素子盆組み込
んだセラミック基板および七の製造方法に関する。 従来、アルミナ粉末にシリカ等のフランクス勿加え、さ
らに有機バインダで周めてシート状V(シたグリーンシ
ートに抵抗素子(単に抵抗とも称丁、、)?内蔵する場
合、(1)、り゛リーンシート孕還元性σ曲気で焼成し
て得たセラミンク板に低湛焼成の導体ペースト(fc1
1!:えは銅ペースト〕忙印刷した後、酸化性低崗与囲
気で焼成してη層抵抗を形成する方法、(2)、クリ−
シートを鋼元性券曲気で焼成して得たセラミック板の表
面のモリブデンい40 )−マンガン(Mn)あるイハ
タンクステン(W)等からなる導体層表面にめっ@
The present invention relates to a ceramic substrate, particularly a ceramic substrate incorporating a resistive element tray, and a manufacturing method thereof. Conventionally, in the case of incorporating a resistance element (also simply called resistance) into a green sheet, (1) A conductor paste (fc1) with a low firing rate is applied to a ceramic board obtained by firing with lean sheet reducing
1! :Eha copper paste] Method of forming η layer resistor by baking in oxidizing low granite atmosphere after printing, (2),
Molybdenum (40)-manganese (Mn), Ihattansten (W), etc. are plated on the surface of a conductive layer of a ceramic plate obtained by firing the sheet in a steel-making process.

【施
して金めっき8(、+ T Mつた後、抵抗形成領域に
カーボンペースト葡印4iilI L、かつ焼成するこ
とによって抵抗音形成する方法、が知ら)1−ている。 しかし、前者の方法は焼成後のセラミック板上(tc4
体ペーストケ印刷するため、導体ペーストはセラミック
板上に滲むようにして拡がる傾向があり、精緻なパター
ンが作り難い。したがって、フェイスタウン・ボンナイ
ングチツブ用の接続用ランドのパターンも精緻とブlす
φB、チップのJk ib’4が稚しい、’Ifこ、導
体ペースト(011ペースト)1:f :// 5スτ
君lirため配線層の抵抗が人きくなる欠点があるとと
もに、’l’ Ellの濡才しが悪く、チップ搭載時の
接合M:が低い欠点がある。 !F1こ、f(台の導体層六面葡金めっき膜で被い酸化
4囲気1・の抵わ1、形JJy、時lC導体層が酸化す
るの〒+Vj IL′Tる)j法Tb、f、高仙jな金
r用イルタメコスト7/’1i4 < lる岬点がある
とともに、カーボンペーストによる抵抗は信頼性が低い
欠点がある。 しkがつ′C1木ウヘ明の目的社高品質の抵抗素子(抵
抗)葡イイするセラミック基板r安価に提供することに
らる。 葦た、本発明の他の目的は抵抗素子Ti[する十ラミッ
ク基板の製造方法におい一〇、精緻な導体層パターンを
製造することができる七ラミック基板の製造方法r提供
することにある。 さらに、本発明の曲の目的は抵抗素子tイ1する十ラミ
ック基板において、抵抗値が小Aくかつ半田の濡れ性が
良好な導(+層ケ・角するセラミック基板km供するこ
とにある。 このような目的?達成するために本発明は、グリーンシ
ー トのp面に導体ベースNrI′)’を望パターンに
印刷するとともに還元性51F、囲気で焼成して導体ノ
曽を有するセラばツク板を形J&する工4里と、前記セ
ンミック板の7(面に露出する導体層の少なくとも抵抗
接続端子となる表面部分子餉め′)さ層こ・被う王権と
、前6已セラミツク板の抵抗形成領域にランタンポライ
ドr生成分とする抵抗ペーストケ印刷するとともに酸素
【苫″f、ない中性(小活性)あるいは還元性4囲気で
焼成して抵抗r形成する工程と、によって抵抗〒41′
Tるセラミック基板r製漬するものであって、以下実施
例により本発明r説明する。 第1図は本発明の一実施例妃よるセラミック基。 板の製造方法を示すフローチャート、第2図IRI〜l
clは同じく各製造段階でのワークの断面図、第3図d
同1;〈→てラミツク基板の一部を示す平面図である。 セラミック条板f?4造するには、先ずグリーンシート
および1体ペーストならびに絶縁ペーストを川面した後
、第2図(8)に示すように、グリーン−7−ト1上に
導体ペースト2および絶縁ペースト3を杼り返しで印刷
しく第1図のフローチャート参照)、多層板4を形成す
る。そして、この多層板4を常用のH元疼囲気で焼成し
て第2図1b+で示すような焼成板5を形jji L、
第3図1c下すように、対となる抵抗接続端子63部品
搭載用ランド7を名む配線層8を焼l戊板5の内部およ
び表面に亘つ−C設りる。 +Stl Nt2グリーンシートlはアルミナ粉末にシ
リカなどのフラツクスを加え、有(幾バインダによって
シート状にしたものである。この結果、絶縁・導体ヘ−
Xl−の印刷時ニクリーンシートltjペースト中の溶
剤を吸収し易くなり、印刷層の側方への滲みが少なくな
る。したがって、印刷パターンの微細化、精緻化が可能
となり、前Hじ部品搭載用ランド7の各間隙の縮小化も
可能となる。 1’lf記導体ペーストはグリーンシート1の焼J戊現
度によっても劣化しないM□ −Mn、 P、l−Ag
 。 W等の高耐熱拐料を主成分としでいる。そしで、前記部
品搭載用ランド7の111Mは100/1m、ピッチは
1.0077mとなり、従来の七nぞれの数値200、
#mに対して大幅に小さくなる。なお、実施例でV、を
部品搭載用ランド7は多層板4の内部の414ペ一スト
層2にスルーホールに埋め込んだ導体ペーストによる接
続部9でFl、気的に接続筋れた4IIv造となってい
るが、多層板4上に延在させてQi定の導体ペースト層
に接続されるようにしてもよ−。また、各導体ペースト
層はたとえば20μm44ji度の1νさに、葎X縁ペ
ースト層は友とえは100μm程度の叶さに、グリーン
シート1はたとえば10071mのII 1361−、
 f(7)でいる。 つきに、このど層仮4を常用の焼成処理、T々わち1■
元t’i、多’、:囲気Tで焼IJい2、硬化式せる。 導体ベース1ノr/iu、 7!f、体層1 (B:f
xす、りII −y ’y −)1すrよび11・1・
4ペ一スト層り、一体化さ7′1.たセラミック板11
となる。 つ@’&’?’、 +i・1めつき処理を施して、セラ
ミック板11の上面VtJオ出している導体層】0の表
面に2μm程度の1−さに銅めつき膜12を形成する〔
第2図fbl参照〕。 つ^pv、同図1clに示rように、対となる抵抗接子
1七9渚t” 6間に亘ってランタンポライド(La)
311)を主成分とする抵抗ペーストを印刷しに後、中
、性(不活(jl、)あるl/1は還元性雰囲気で焼I
戎(801,1〜90 (l C−I: 50分すし、
抵抗(tit抗素子)13y)ヒDv、する。この1+
 (I B 6は印刷にょる銅jψ膜に接続I′i1能
なIa抗ペーストとして開発市販路れ1いるものであり
、木づ^明者等にζよって銅めっ@膜との間でも艮tl
(な市、夕(的接続が行えること?実験によって確イぢ
しでいるものである。このLaB6は酸素を含ま々い不
活性(中性)ガス、あるいは還iしガス纒囲気で焼成処
理さn、るl臣長がある。この結果、抵抗形成時には、
W等からなる前記導体層10の酸化は防止できることに
なり、4体層IOの劣化tよ生しない。 このようなセラミック基板14にあってtま、表面の部
品搭載用ランド7に半田15を弁してICチップ16を
フェイスダウンΦボンディングによって固定する。半田
15はあらかじめICチップ1Gのit極部にバンプ電
極の形として形成しておく。 このような実施例によれは、導体層全形成するための導
電ペーストの印刷は、吸湿性のめるグリーンシート上に
行なわ7’Lる。この結果、ペースト中の溶剤がグリー
ンシートに印刷されてにじみが起きず、微粗パターン化
がoJ能となる。したがって、ICチップ等の部品をフ
ェイスダウン争ボンディングで実装する際の部品搭載用
ランドの縮小化、ランド間ピッチの狭小化がb」能とな
り、部品のバンプML極に各ランドllJ、適正に対応
できるようになって実装がIj]能となる。 また、配線層の入面は抵抗値が極めて小さい銅めつ@ 
714%でフルわjLでいることから、配線層の抵抗値
は従来に比較1.て小さくなる。また、銅めっき膜はゲ
:来の、しうなガラスフリット(シリカ)等ヲ含1ない
ピュアーな銅であることから、ICチップ実装時に用込
る”l’lllとの#Sれ性が良好となり、信Il1度
の高い実装が内油となる。 また、ランタンホライドは従来のカーボン抵抗に比較し
て良質の抵抗を形作る。また、ランタンポライドの焼成
は酸素を含1ない分囲気で行なえることから、従来のよ
うr(配線層を高価な金で被う必装もなく、少なくとも
ランタンポライドとの接続部にのみ安■1な帽を弁(E
さ−じればよくなる。 この結堅、コストの低減が図れる。なお、鋼めっさはラ
ンタンポライドとの接続のためには配線層の抵抗4軽続
端子部分にのみ形成丁れはよいわけであるが、へ用j〜
る配線層全長に亘って設けILは、前スホのよう(/L
配紳層の抵抗1utの減少化、半11JJの濡れ性向ト
化を1ソすることができるようになる。 なお、本発明は前記実施例に限定されない。 以上のように、本発明によ11ば、精緻で抵抗値が小さ
くかつ半田との濡れ性が艮好な部品5qの抵抗素子を有
するセラミック基板を安価に提供することができる。
[After applying gold plating, carbon paste is applied to the resistor forming area, and a method of forming a resistor by firing is known)1-. However, the former method uses a ceramic plate (TC4) after firing.
Since conductor paste is printed, the conductor paste tends to ooze and spread on the ceramic plate, making it difficult to create precise patterns. Therefore, the pattern of the connection land for the face town bone chip is also detailed and blank. φB, the Jk ib'4 of the chip is poor, 'If this, conductor paste (011 paste) 1: f :// 5th τ
It has the disadvantage that the resistance of the wiring layer is high due to the low voltage, and the 'I' Ell is not well-developed, resulting in a low bonding M: when mounting the chip. ! F1, f (6 sides of the conductor layer of the stand covered with gold plating film, oxidation 4, resistance 1, type JJy, when the IC conductor layer oxidizes 〒+Vj IL'Tru)j method Tb, There is a cape point where f, high quality metal cost 7/'1i4 < l, and the resistance by carbon paste has the drawback of low reliability. Our goal is to provide high-quality resistive elements (resistors) on ceramic substrates at low prices. Another object of the present invention is to provide a method for manufacturing a lamic substrate containing a resistor element (10) and a method for manufacturing a lamic substrate that can manufacture a precise conductor layer pattern. Furthermore, the object of the present invention is to provide a ceramic substrate with a low resistance value and good solder wettability in a ceramic substrate having a resistive element (layers and corners). In order to achieve this purpose, the present invention prints a conductor base NrI')' on the p-plane of a green sheet in a desired pattern, and then bakes it in an atmosphere of reducing 51F to produce a ceramic sheet having a conductor base. 4 pieces of work to shape the board, 7 pieces of the above-mentioned ceramic plate (at least the surface portion of the conductive layer exposed on the surface that will become the resistance connection terminal), the layer and the crown, and the front 6 pieces of the ceramic plate. The resistor is formed by printing a resistor paste containing lanthanum polide on the resistor-forming area and baking it in a neutral (small active) or reducing atmosphere without oxygen to form the resistor. 41'
The present invention will be explained below with reference to Examples. FIG. 1 shows a ceramic base according to one embodiment of the present invention. Flowchart showing the manufacturing method of the board, Figure 2 IRI~l
cl is also a cross-sectional view of the workpiece at each manufacturing stage, Figure 3d
FIG. 1 is a plan view showing a part of the lamic substrate. Ceramic strip f? To make a 4-piece structure, first spread the green sheet, one-piece paste, and insulating paste on the surface, and then pour the conductive paste 2 and insulating paste 3 onto the green sheet 1, as shown in Figure 2 (8). (See the flowchart in FIG. 1) to form the multilayer board 4. Then, this multilayer board 4 is fired in a commonly used H gas atmosphere to form a fired board 5 as shown in Fig. 2, 1b+.
As shown below in FIG. 3, a wiring layer 8 called a pair of resistor connection terminals 63 and component mounting lands 7 is provided over the inside and surface of the sintered plate 5. +Stl Nt2 green sheet l is made by adding flux such as silica to alumina powder and forming it into a sheet shape with a binder.
When printing Xl-, the solvent in the Nikleen Sheet ltj paste is easily absorbed, and the sideward bleeding of the printed layer is reduced. Therefore, it is possible to make the printed pattern finer and more precise, and it is also possible to reduce the gaps between the front H component mounting lands 7. 1'lf conductor paste does not deteriorate even depending on the degree of burning of green sheet 1 M□ -Mn, P, l-Ag
. The main ingredient is a highly heat-resistant additive such as W. Therefore, the 111M of the component mounting land 7 is 100/1m, the pitch is 1.0077m, and the conventional value of 7n is 200,
It becomes significantly smaller than #m. In the example, V is connected to the component mounting land 7 by connecting portion 9 made of conductive paste embedded in the through hole in the 414 paste layer 2 inside the multilayer board 4. However, it may be extended on the multilayer board 4 and connected to a conductive paste layer having a constant Qi. Further, each conductive paste layer has a thickness of, for example, 20 μm and 1ν of 44 degrees, the thickness of the green sheet 1 is approximately 100 μm, and the green sheet 1 has a thickness of, for example, II 1361- of 10071 m.
I am f(7). Finally, this layer 4 is subjected to the usual firing process, T2Wachi 1■
Original t'i, multi': Baked in the surrounding air T2, hardened. Conductor base 1 no r/iu, 7! f, body layer 1 (B: f
xsu, ri II -y 'y -)1sr and 11・1・
4 paste layers, integrated 7'1. ceramic plate 11
becomes. Tsu@'&'? A copper plating film 12 is formed on the surface of the ceramic plate 11 with a thickness of about 2 μm [1-].
See Figure 2fbl]. As shown in Figure 1cl, lanthanumolide (La)
After printing a resistive paste mainly composed of
Ebisu (801,1~90 (l C-I: 50 minutes sushi,
Resistance (tit resistance element) 13y) Dv. This 1+
(I B 6 has been developed and commercially available as an Ia anti-paste that can be connected to a copper film by printing, and it has been reported that it can be connected to a copper plating film by ζ. tl
(Is it possible to make a connection? This has been confirmed through experiments. This LaB6 can be fired in an atmosphere surrounded by an oxygen-containing inert (neutral) gas or a reduced gas. As a result, when resistance is formed,
Oxidation of the conductor layer 10 made of W or the like can be prevented, and no deterioration of the four-layer IO occurs. In such a ceramic substrate 14, solder 15 is applied to the component mounting land 7 on the surface and the IC chip 16 is fixed by face-down Φ bonding. The solder 15 is previously formed in the form of a bump electrode on the IT pole of the IC chip 1G. According to this embodiment, printing of the conductive paste for forming the entire conductor layer is performed on a hygroscopic green sheet. As a result, the solvent in the paste is printed onto the green sheet without bleeding, and fine and rough patterning becomes possible. Therefore, when mounting components such as IC chips by face-down bonding, it is possible to reduce the size of the component mounting land and narrow the pitch between lands, allowing each land to properly correspond to the bump ML pole of the component. Implementation becomes possible. In addition, the entrance surface of the wiring layer is made of copper metal with extremely low resistance.
Since it is full at 714%, the resistance value of the wiring layer is 1. becomes smaller. In addition, since the copper plating film is pure copper without any natural glass frit (silica), etc., it has good #S resistance to "l'llll" used when mounting IC chips. Therefore, the high-reliability mounting becomes the internal oil.In addition, lanthanumolide forms a high-quality resistance compared to conventional carbon resistance.In addition, lanthanumolide is fired in an atmosphere that does not contain oxygen. Since this can be done, there is no need to cover the wiring layer with expensive gold as in the past, and at least an inexpensive cap can be used only at the connection with lanthanumolide.
It will get better if you look. This solidification helps reduce costs. In addition, the steel plating is only formed on the resistor 4 light connection terminal part of the wiring layer for connection with lanthanumolide, but it is not necessary to use it.
The IL is provided over the entire length of the wiring layer, as in the previous photo (/L
It becomes possible to reduce the resistance of the men's layer by 1 ut and increase the wettability of half 11 JJ by 1 ut. Note that the present invention is not limited to the above embodiments. As described above, according to the present invention, it is possible to provide at a low cost a ceramic substrate having a resistive element of component 5q which is precise, has a small resistance value, and has excellent wettability with solder.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による七ラミック基板の製造
方法を示すフローチャート、 第2図+R1〜(clは同じく各製造段階でのワークの
断面図、 第3図は同じくセラミック基板の一部を示す平面図であ
る。 1・・・グリーンシート、2・・・導体ペースト、3・
・・絶縁ペースト、5・・・焼成板、6・・・抵抗接続
端子、7・・・部品搭載ランド、8・・・配+vi!層
、10・・・4体層、12・・・銅めつき膜、13・・
・抵抗、14・・・セラミック基板、15・・・半田、
16・・ICチップ。
FIG. 1 is a flowchart showing a method for manufacturing a lamic substrate according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of a workpiece at each manufacturing stage; FIG. It is a top view showing 1... green sheet, 2... conductor paste, 3...
... Insulating paste, 5... Baking board, 6... Resistance connection terminal, 7... Component mounting land, 8... Wiring +vi! Layer, 10... 4 body layers, 12... Copper plating film, 13...
・Resistor, 14...Ceramic board, 15...Solder,
16...IC chip.

Claims (1)

【特許請求の範囲】 1、導体層および導体層に接続さtする抵抗奮有するセ
ラミック基板において、前記抵抗はランタンポライドか
らなるとともに、抵抗は導体層−ヒに部分的または全体
的に形成された銅めっき膜ケ弁して導体)t4に接続さ
れてbること7脣徴とするセラミック基板。 2 前6【シ導体層の−f(Bは部品搭載用ランドとな
っていること盆11脣徴するlr!fN’f ii’J
求のヰ1」、開田1項記載の一トラミンク基板1. 3、 グリーンシートの身゛ぐ菌Iに導1本ペーストヶ
所望パターンに印刷するとともに点元性迩1111気で
焼成し、 −L L’f I’t’ 、I咄11−1−
る士うミンク板?形成する工程と、目11rt+、セラ
ミック板のp面にyに出する導体層のり2なくとも抵抗
接続ΔIA子となる表面部分ケ銅めっき層で被う」杵と
、…]U+、;セラミック板の抵抗形成i11″1城し
てランタンポライドを主成分とする抵抗ペーストヶ印刷
するとともに酸素葡含!ない中性るる因は還元性宵囲惣
で焼成して抵抗ケ形成する工444と、からなる七ラミ
ック基板のHj”lx方法。 4、前記導体層の一部は部品搭載用ランドとなっている
ことr特徴とする%Wl′−梢求の範囲第3項記載のセ
ラミック基板の段端方法。
[Claims] 1. A ceramic substrate having a conductor layer and a resistor connected to the conductor layer, wherein the resistor is made of lanthanide, and the resistor is formed partially or entirely in the conductor layer. A ceramic substrate with a copper plated film connected to the conductor (t4) and b (7). 2 Previous 6 [-f of the conductor layer (B is a land for mounting parts) Lr!fN'f ii'J
One track mink substrate 1 as described in Kaida 1. 3. Apply one paste to the green sheet containing the bacteria I, print it in the desired pattern, and bake it at a temperature of 1111.
Rushi's mink board? The process of forming, 11 rt+, the conductor layer applied to the y side on the p-plane of the ceramic plate, 2 at least the surface portion that will become the resistance connection ΔIA element is covered with a copper plating layer. Resistance formation process 444: A resistor paste containing lanthanumolide as a main component is printed, and the neutral base is fired in a reducing atmosphere to form a resistor. This is the Hj”lx method for seven ramic substrates. 4. The step edge method for a ceramic substrate according to item 3, characterized in that a part of the conductor layer is a land for mounting components.
JP14114382A 1982-08-16 1982-08-16 Manufacturing method of electronic component mounting body Granted JPS5932194A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14114382A JPS5932194A (en) 1982-08-16 1982-08-16 Manufacturing method of electronic component mounting body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14114382A JPS5932194A (en) 1982-08-16 1982-08-16 Manufacturing method of electronic component mounting body

Publications (2)

Publication Number Publication Date
JPS5932194A true JPS5932194A (en) 1984-02-21
JPH0430199B2 JPH0430199B2 (en) 1992-05-21

Family

ID=15285160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14114382A Granted JPS5932194A (en) 1982-08-16 1982-08-16 Manufacturing method of electronic component mounting body

Country Status (1)

Country Link
JP (1) JPS5932194A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02254785A (en) * 1989-03-29 1990-10-15 Ngk Insulators Ltd Manufacture of circuit board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56146201A (en) * 1980-04-14 1981-11-13 Matsushita Electric Industrial Co Ltd Alumina circuit board with glazed resistor
JPS58153394A (en) * 1982-03-08 1983-09-12 日立化成工業株式会社 Method of producing ceramic multilayer circuit board with resistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56146201A (en) * 1980-04-14 1981-11-13 Matsushita Electric Industrial Co Ltd Alumina circuit board with glazed resistor
JPS58153394A (en) * 1982-03-08 1983-09-12 日立化成工業株式会社 Method of producing ceramic multilayer circuit board with resistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02254785A (en) * 1989-03-29 1990-10-15 Ngk Insulators Ltd Manufacture of circuit board

Also Published As

Publication number Publication date
JPH0430199B2 (en) 1992-05-21

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