JPS593270A - Apparatus for inspecting disconnection of switching circuit - Google Patents

Abstract

PURPOSE:To make it possible to carry out the inspection of disconnection at low voltage, in a switching circuit connecting plural switches in series, by connecting a condenser to each switch in parallel to discriminate a logical state due to the difference in a wave form when a connecting wire is disconnected. CONSTITUTION:When a control circuit CC outputs a signal H, it is inverted by an inverter 1N1 to issue a signal L from a terminal P1 and, when all switches S1-S3 are closed, the signal of an input terminal P2 comes to L while the signal H is issued to the output side of an inverter 1N2. This signal H is detected to judge such a state that all switches are closed by a judge circuit JC. If either one of the switches S1-S3 and connecting wires L1-L4 is disconnected, the signal L is not obtained at the input terminal P2 while said signal L is issued to the output of the inverter 1N2 in a signal H state. The judge circuit JC receives this signal L to open either one of the switches or to judge the disconnection of a circuit. As mentioned above, the judge circuit JC discriminates the logical state of a detecting point to enable the judgement of the disconnection of the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of the Invention The present invention relates to a disconnection testing device for a switch circuit in which a plurality of switches are connected in series.

(1) ((b) Conventional technology and its problems FIG. 1 is a circuit connection diagram showing a conventional switch circuit.

In the figure, sl, s2. s3 is a switch pThese switches 81. S2. s3 is the connection line L1, L2 . L3.
They are connected in series through L4 to form a switch circuit SC. One end of this switch circuit SC is connected to a signal source -V, and the other end is connected to an electronic circuit EC via a control input terminal P. The input terminal P is connected to a high-level power supply +V by a pull-up resistor R, and is also connected to an inverter IN. In this circuit switch 8
1,82. When all s3 are closed, the terminal P is forced to the L level /I/(-V), and the input signal Is is introduced at "HJ (high)" to the internal circuit via the inverter IN, and conversely,
Switch S1. If either S2 or S3 is open, the input terminal P becomes H level and the input signal Is becomes rLJ.

However, in such a conventional circuit, the connection lines L1 . L2. L3. L4 is disconnected and switch s1. s2. It was not possible to distinguish between the cases where s3's Izufuda Riki was opened.

To solve this problem, the connection lines T, ;1, L2 . L3. Switch S to disconnect L4.
1, 82, 83 has already been proposed.

FIG. 2 is a circuit connection diagram of a disconnection testing device for a switch circuit that has already been proposed. In the same figure, switch circuit S
C represents each switch S1. S2. In parallel with S3 are diodes DI, D2. D3 is connected, and these parallel connections are further connected in series. Also, the reverse signal a from the electronic circuit EC is sent to the inverter INi and external terminal P1.
It is connected so as to be led out through the circuit and added to one end of the switch circuit SC. Furthermore, the switch circuit SC is connected to the input terminal P2 of the electronic circuit EC. Input terminal P2
is connected to the power supply +V and to the inverter IN2 by a pull-up resistor R. Further, the input terminal P2 is configured so that a signal 1] is applied from inside the electronic circuit EC via an inverter IN3.

In this circuit, when inspecting the switch circuit SC for disconnection, the signal a is set to rLJ and is connected to the external terminal P1 r.
The HJ signal is derived and this signal is applied to one end of the switch circuit SC, while the signal 1) is set to JHJ so that the input terminal P2 becomes rLJ. If the switch circuit SC is normal here, that is, the connection line L1. L2, L3
．． If L4 is not disconnected, diodes DI and D2
, p3, the external terminal P1 is also forced to "L", and normality is determined by taking this signal rLJ into the electronic circuit EC. However, if either the connecting wire Ll or L2゜L B is disconnected, the rL of input terminal P2
The J signal is not transmitted to the external terminal P1 and remains at "H". This signal rHJ is taken into the electronic circuit EC and connected to the connection line Ll of the switch circuit SC.

L2. L3. It is determined that T and 4 are disconnected. In this way, the switch circuit SC is tested for disconnection.

However, the disconnection testing device for switch circuits shown in Figure 2 has the disadvantage that it must apply a power supply voltage that takes into account the voltage drop caused by the diode, and that it must be equipped with a high-voltage power supply when the number of switches connected in series increases. be.

(c) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the above-mentioned conventional devices, and to solve the problems of the conventional devices, even in a switch circuit in which a large number of switches are connected in series.
An object of the present invention is to provide a disconnection inspection device for a switch circuit that can detect disconnection at low voltage.

B) Structure and Effect of the Invention In order to achieve the above object, the switch circuit disconnection inspection device of the present invention connects a capacitor in parallel to each switch connected in series, and connects a predetermined capacitor to one end of the series connection of the switches. A signal source for applying a logic state signal is provided, and a capacitor υ1mI is connected in parallel with the signal source at the other end. Depending on the logic state of the signal applied through the series connection of the switches, the series connection of the switches p@ is disconnected. A determining means is provided for identifying and determining whether the switch is in the "1-open" state or one of the switches is in the "1-open" state.

According to the disconnection inspection device for a switch circuit of the present invention, by connecting a capacitor in parallel to each switch, logical identification can be performed based on the difference in waveforms when a connection line is disconnected and when one of the switches is in the "open" state. Because the circuit detects disconnection, no voltage drop occurs no matter how many capacitors are connected in series, and no matter how many switches are connected in series.

Disconnection inspection can be performed at low voltage.

Description of 0 Embodiments (Embodiment 1) FIG. 3 is a circuit connection diagram of a disconnection testing device for a switch circuit showing an embodiment of the present invention. In the same figure, SC is a switch circuit and υ is a diode D1. D2゜D3K, t and capacitors C1, C2, C3 are respectively connected to switches S1. S2. S
3 are connected in parallel. the switch circuit SC is connected to the control circuit CC via the input terminal P2;
There is no difference from that shown in FIG. 2 in that the input terminal P2 is connected to the +V power supply via the pull-up resistor R and is also connected to the inverter IN2.

JC is a determination circuit connected to inverter IN2.

CC is a control circuit that outputs a predetermined amount, and the signal output from this control circuit CC is sent to an inverter (driver).
IN1 is connected to one end of the switch circuit SC via an external terminal P1.

Next, this embodiment will be explained with reference to the signal waveform shown in FIG. In Fig. 4, A, B.

C shows the waveform of terminal 7P1, the waveform of input terminal P2, and the waveform of the output of inverter IN2 of the embodiment shown in FIG. 6, respectively.

First, when the control circuit CC outputs the rHJ signal.

This signal is inverted by the inverter INK, and an "L" signal is derived from the terminal P1. At this time, all switches S1
．． S2. When S3 is closed, the signal at input terminal P2, that is, point B, becomes rLJ, and the output l11 of inverter IN2
The rHJ signal signal groove is output at 1j (Fig. 4 also shows 1 to t2).
). Upon receiving this HJ signal, the determination circuit JC determines whether the power switch is fully closed.

If switch S1. S2. S6 is in the "open" state, or the connection line L1. L2. If either L3 or L4 is disconnected, input terminal P2 will have r
Since the LJ signal is not obtained, the "H" signal remains, and the "L" signal is derived from the inverter IN2 output. This “L”
Upon receiving the ``signal'', the determination circuit JC determines that ``one of the switches is open'' or the power circuit is disconnected. In response to this determination, the control circuit CC outputs a pulse signal via the inverter INI. In this case, if any switch is open, a differential waveform is obtained at the inverse input terminal P2 due to the differential action of the capacitor connected in parallel to the open switch. (Here, if the protection diode D4 is connected to the input of the inverter IN2, the differential waveform will be cut in half as shown by the diagonal line in FIG. 4B.) The differential waveform of the input terminal P2 will be The pulse waveform is inverted by the inverter IN2, resulting in a pulse waveform as shown in FIG. 4C. Judgment circuit JC
In response to this pulse signal, one of the switches opens.
' (also refer to 6 to t4 in FIG. 4).

If the connection wire of the switch circuit SC is disconnected, the input terminal P2 remains the iHJ signal even if a pulse voltage is applied to the switch circuit SC (7).

The l'-HJ signal is inverted by inverter IN2 and r
It is derived from the LJ signal and applied to the judgment circuit JC.

Judgment circuit JC receives rLJ signal from ``Circuit breakage''.
(See t4 onwards in Figure 4) <Example 2> Figure '5 is a circuit connection diagram of a disconnection inspection device for a switch circuit showing another embodiment of the present invention. This embodiment device /< in place of the control circuit CC of the embodiment device shown in FIG.
, /Renu signal generator PG is used and the determination logic configuration of the determination circuit JC is different, but otherwise the device has the same connection configuration as the embodiment shown in FIG.

FIG. 6 is a circuit diagram showing the internal configuration of the determination circuit JC of this embodiment. In the figure, DF is a D flip-flop that performs a read operation using a clock signal CP, and its input terminal is connected to the output terminal of an inverter IN2. In addition, the input terminal of the D flip-flop DF, that is, the output terminal of the inverter IN2 is connected to CQ through the parallel connection of a resistor RJ and a diode DJ).
^^4(8) The input terminal of the inverter IN4 is connected to the ground via the capacitor CJ-i. This resistor RJ, diode DJ, and capacitor CJ constitute a peak hold circuit for the output of the inverter IN2. Further, the output terminal of the D flip-flop DF and the output terminals of the inverters I and N4 are both connected to the input terminal of the NOR gate GJ.

Next, the operation of this embodiment device will be explained with reference to the signal waveform shown in FIG.

When a pulse signal is generated by the pulse signal generator PG, a pulse signal shown in FIG. 7A is derived from the terminal P1 via the inverter IN1, and this pulse signal is applied to the switch circuit SC. Here, each switch S1 of the switch circuit SC
,82. When all of S3 are closed, the switch circuit S
The pulse signal applied to C is sent to input terminal P2 (point B)! , is transmitted (see also 1 to t2 in FIG. 7B). If switch 81. S2. When any of S3 is open, the pulse signal is differentiated by a capacitor (10) connected in parallel with the open switch.

The input terminal P2 obtains the signals shown at 2 to t3 in FIG. 7B (if the diode D4 is connected in parallel to the pull-up resistor R, the shaded portion is cut off).
. Well, if the connection line L1 of the switch circuit SC. L2. L
3. If any of L4 is disconnected, the switch circuit SC
The pulse signal applied to is not transmitted to input terminal P2,
Input terminal P2 inputs the rHJ signal directly to inverter IN2.
(See Figure 2 BcDt3 onwards).

The signal at input terminal P2 is applied to inverter IN2 and inverted by one. V37The inverted waveform of the signal shown in Figure B, that is, the output waveform of inverter IN2, is as shown in Figure 7C.
becomes. Note that the reason why the sharp portion of the differential waveform in the period 2 to 3 is cut off is due to the saturation characteristic of the inverter IN2.

The signal at the output end of the inverter rN2, that is, the 0 point, is held at its peak by a peak hold circuit 1 consisting of a resistor RJ, a diode DJ, and a capacitor CJ, and the signal is output to the inverter I.
It is added to the input terminal of N4, that is, point D. The signal waveform at point D is as shown in Figure 7. This signal is inverted by the inverter I N 4, resulting in the signal shown in FIG. 7F.

On the other hand, the output signal of inverter IN2 is the clock signal Cp
is read into the D flip-flop DF every time . Therefore, the signal shown in FIG. 7E is obtained at the output terminal (point E) of the D-type flip-flop DF which receives the signal shown in FIG. 7C as an input. The signal at point E is rHJ for only one to two periods even when all the switches of the switch circuit SC are closed, and the second judgment circuit JC detects that the signal E is rHJ. It is possible to determine whether all switches are closed.

The output signal of the D flip-flop DF (signal in Figure 7 E) and the output @ of the inverter IN4 (signal in Figure 7 F)
was added to Noah Gate GJ, and these two-person power signals became ``
In the case of "L", that is, the switches 81, 82 . s3 is open, GJ derives the II (J signal) at the output terminal (see Figure 7H).Therefore, the determination circuit JC determines that the signal at point E is rHJ. By being.

It can be determined that either switch is in the open state.

The output of inverter IN4, that is, the signal at point F, is still
Switch circuit connection line L1. L2. It becomes "H" only after t3 when L3 and L4 are disconnected, and the 1 determination circuit JC can determine that the circuit is disconnected because the signal at point F is "HJ".

In this embodiment, the falling signal of the pulse signal from the pulse signal generator PG may be used instead of the clock pulse CP as the read clock for the D flip-flop DF.

Moreover, the above-mentioned Example 1. Although the second embodiment shows only one switch circuit in which a plurality of switches are connected in series, the present invention can also be applied to a case where several switch circuits are arranged in parallel.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram of a conventional switch circuit, FIG. 2 is a circuit connection diagram of a conventional switch circuit disconnection inspection device, and FIG. 6 is a circuit connection diagram of a switch circuit disconnection inspection device showing an embodiment of the present invention. 4 is a signal waveform diagram for explaining the operation of the apparatus according to the embodiment shown in FIG. 6; FIG. 6 is a circuit connection diagram showing the internal structure of the judgment circuit of the embodiment shown in FIG. 5, and FIG. 7 is a signal waveform diagram for explaining the operation of the embodiment device shown in FIG. SC: switch circuit, si/S2/S6: switch, Ll/L2/L3/L4: connection line. C1/C2/03: Capacitor, Pl: External terminal,
P2: Input terminal, EC: Electronic circuit. CC: Control circuit, JC: Judgment circuit. lN1-lN2/lN4: Inverter. DF: D flip-flop. Patent Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Shigeru Nakamura (14) Male 4 Figure 7

Claims (1)

[Claims] (1) In a switch circuit in which multiple switches are connected in series. A capacitor is connected in parallel to each of the switches, a signal source for applying a predetermined logic state signal is provided at one end of the series connection of the switches, and the capacitor is connected in parallel from the signal source to the other end of the switch. A switch characterized in that it is provided with determination means for identifying and determining whether the series connection of the switches is disconnected, conductive, or one of the switches is in an "open" state, depending on the logic state of a signal applied through the series connection of the switches. Circuit breakage detection device.