JPS593485A - Automatic rhythm performer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

This invention relates to a waveform reading, automatic rhythm playing device,
The S/N ratio is improved by adjusting the level when storing and reproducing the rhythm sound waveform. Conventionally, each rhythm sound waveform of a number of machines was converted into a pulse code and stored in a waveform memory, and the rhythm sound was automatically generated by reading the waveform data from the waveform memory in accordance with the rhythm pulse. An automatic rhythm playing device has been proposed. However, in such an automatic rhythm performance device, the rhythm sound waveform obtained from a rhythm instrument is twisted and converted into a pulse code for storage and playback, so the S/N ratio is low, especially for low-volume rhythm sounds. There was a drawback that the ratio decreased. An object of the present invention is to provide an automatic rhythm performance device with a high S/N ratio. The automatic rhythm playing device according to the invention includes a memory storing volume control data regarding rhythm sound waveforms, a reading means for reading volume control data from the memory, and a reading means for reading out volume control data from the memory, and a system for controlling rhythm sounds according to the read volume control data. According to this feature, for example, for a low-volume rhythm sound, the waveform is converted into a pulse code while the volume level is increased. When the waveform data is read out from the waveform memory and the rhythm sound is played back, the S/N ratio is adjusted by lowering the volume of the rhythm sound in accordance with the volume control data read out from the memory. It can be improved. The invention will now be described in detail with reference to embodiments shown in the accompanying drawings. FIG. 1 shows an electronic musical instrument equipped with an automatic rhythm playing device according to an embodiment of the present invention, and this electronic musical instrument can generate manual playing sound signals and automatic rhythm sound signals with the help of a microcomputer. is now under control. The keyboard 10 includes a large number of keys and a large number of key switches that are linked to each key, and each key switch is a key switch (K
SW) interface 12. The key press results obtained by key scanning are then supplied to the key tone interface 16 via the bus 14. The panel 18 is provided with a number of musical tone selection operators 18A and a number of rhythm operators 18B.The rhythm operator 18E selects a specific rhythm from among the many rhythms as shown in FIG. A group of rhythm selection switches 2o for selecting rhythms, a rhythm start/stop switch 22, a volume control for adjusting the balance of noise-based (cymbal-based) rhythm sounds and drum-based rhythm sounds, and a total volume adjustment of rhythm sounds. A volume 26 and a rhythm tempo adjustment volume are provided. Operator 18
A and 18B are scanned via the panel interface (9), and among the operation data obtained by this scanning, tone selection operation data is provided to the key tone interface I6 via the bus 14. The key musical tone interface 16 converts the key press data and musical tone selection operation data into serial signals and sends them to the keyboard tone forming circuit 3.
Supply to 2. The keyboard sound forming circuit 32 forms a time-division multiplexed digital musical sound signal (manual performance sound signal) KT8 in response to the serial signal from the interface 16, and outputs a serial (S)/parallel (P) conversion/distribution circuit 34.
supply to. The S/P conversion/distribution circuit converts the digital musical tone signal KTS into parallel (i) and digital (D
)/Analog (A) conversion circuit 3G. and,
The analog musical tone signal from the D/A conversion circuit 36 is supplied to the central speaker 40C via an output amplifier and converted into sound. The central processing unit (C!PU) 42 is located in the working area 4.
This system uses a RAM (Random Access Memory) 4 and a program memory 46 consisting of a ROM (Read Only Memory) to control the generation of musical tone signals as described above, as well as the generation of rhythm tone signals as described below. ,
Contains general-purpose A, X, Y registers, etc. Regarding rhythm sound signal generation operation, working area 4
4 is provided with a large number of storage areas as shown in Table 1 below. The rhythm operation data obtained by scanning the rhythm operator +8B in Table 1 is transferred from the panel interface 30 to the bus 14.
The data is supplied to the working area 44 via the PCB and stored therein. That is, the operation data for adding the rhythm selection switch is stored in the register RHYPTH as rhythm designation data.
Operation data for the noise system/drum system balance adjustment volume 24 is divided into noise system volume data and drum system volume data and stored in the registers 4 RHOL Fi V and RHDLEV, respectively, and the total volume adjustment button 1
The operation data for the 1 neem 26 is stored as total volume data in the register TOTLEV, and the operation data for the rhythm tempo adjustment volume is stored as rhythm tempo data in the register TgMPO. The rhythm pattern memory 48 consisting of a ROM stores rhythm pattern data in a format as shown in FIG. 3 for various rhythms as shown in FIG. In each rhythm pattern data, 1-byte instrument group number data is first arranged corresponding to the start address, and the lower 3 bits are θ according to the rhythm classification shown in Figure 2.
It is designed to indicate one of the musical instrument group numbers GN to 7. After the instrument group number data and before the first beat end data BE, there are several event data K related to the rhythm sound to be generated within the first beat.
VTs are arranged in order of sound generation timing. Each event data KVT consists of 2 bytes of data,
The most significant bit of the first byte is not used, the lower 3 bits are the channel number CHN from 0 to 7 shown in Figure 2, and the lower 4 bits are the intra-beat timing from 0 to 11. Each TMG is shown. Here, the channel numbers OHN from 0 to 7 are assigned to [T
C! It corresponds to rhythm instruments indicated by codes such as YJ, ``HHJ, etc., and the correspondence between each code and each rhythm instrument is shown in Table 2 below.Table 2 Each event data EVT In the second byte, the upper 2 bits are not used, the lower 2 bits are the pitch P, the lower 3
The bits each indicate the volume level LKV. Here, the bit pitch T is for specifying, for example, whether a tom-tom should be a high-pitched or low-pitched tone, or whether a conga should be a high-pitched, low-pitched tone, or a crashing tone. Also, the volume level TJ E V
is used to specify the strength of each note in the range from pianissimo to fortissimo. Therefore, each event data EVT includes information regarding which rhythm instrument is to be sounded at which timing within a beat, at what pitch, and at what volume. The beat end data BE consists of 1 byte of data, the upper 4 bits of which are not used, and the remaining 4 bits are rllol.
J, and this content is conveniently expressed in hexadecimal notation as “OD
” After the first beat end data BE, the second beat event data FVT is placed sequentially, after which the second beat end data BITi is placed, and in the same manner, the required number of event data EVT and beat end data are placed. Data BE is placed. Then, return data RTN is placed in the place of the last event data EVT. Return data R
TN consists of 1 byte of data, the upper 4 bits of which are not used, and the remaining 4 bits are r ] 11 ], J, and for convenience, this content is expressed in hexadecimal notation as "OF". The pattern start address memory 50 consisting of a ROM stores the start address data for each rhythm of the rhythm pattern memory 48, and the stored contents are read out using the rhythm designation data from the register RHYPTN in the working area 44 as an address signal. It has become. The logarithm (LOG) volume table 52 is a register TOTL.
A first ROM for logarithmically converting the total volume data from EV, drum system volume data from register RHDLEV, and register RHOLF! A second ROM for logarithmically converting noise volume data from V is provided. The instrument level memory 54 consisting of a ROM stores volume level control data corresponding to each of the four types of rhythm instruments shown in FIG. 2 and Table 2, and the content of each volume level control data corresponds to the corresponding rhythm instrument. This is determined by taking into account the degree of volume level adjustment when recording or storing the rhythm sound waveform. The rhythm sound waveform memory 56, which is a ROM, stores waveform data L7 corresponding to each rhythm sound waveform of various types of rhythm instruments including the aforementioned different types. In this case, even instruments with the same name as the above-mentioned tom-tom or conga are treated as different instruments if they have different pitches.
More types of rhythm sound waveforms than the 28 types described above will be stored. Here, the waveform data corresponding to each rhythm sound waveform is obtained by sampling the rhythm sound waveform as shown in FIG. This was obtained by converting the imaging width into a pulse code. The rhythm interface 58 generates an interrupt command signal I'NT at each predetermined timing, and if there is event data to be generated at a specific timing, serial data opa as shown in FIG. This is supplied to the generation circuit 6o. In the serial data OPC shown in Fig. 5, NKON (first bit) indicates a sound production command signal, NKOF indicates a mute command signal, LEV (3 pits) indicates a volume level specification signal, and P/T (2 bits) indicates a pitch specification signal. . In addition, rhythm interface 5
Since rhythm tempo data is supplied to rhythm tempo 8 from register TKMPO when rhythm tempo is set, the rhythm tempo is determined based on this 11 rhythm tempo data. The panel data interface 62 supplies a volume control signal LV and a rhythm control signal PAN as shown in FIG. 5 to the rhythm sound generation port 60. Volume control signal L
V is a series arrangement of an 8-bit signal NLKV for specifying the volume level of noise-based rhythm instruments and an 8-bit signal DLEV for specifying the volume level of drum-based rhythm instruments, and is used to specify the noise-related volume level. Signal NLKV
The value of is expressed as tOf(TXB,), and the value of the drum sound level designation signal DLEV is expressed as tof(T x BD). Here, T indicates the total volume level due to the volume 26, BN and B. indicates the noise volume level and the drum volume level, respectively, depending on the volume. Therefore, the noise system volume level designation signal NLB
V is obtained by adding the total volume data from the first ROM of the logarithmic volume table 52 and the noise fundamental tone 9 data from the second ROM of the same table 52, and the drum system volume level designation signal DLKV is obtained from the logarithmic volume table 5.
It is obtained by adding the total volume data from the first ROM of Table 52 and the drum system volume data from the second ROM of the same table 52. There are two types of rhythm control signals PAN as shown in FIGS. 5(A) and (B), and the signal (A) is stored in the level memory 54 for each instrument.
It is formed by sequentially reading out the contents (volume level control data) of the volume level control signal vLa (5 bits) and giving an address (5 bits) corresponding to the instrument name for each volume level control signal vLa (5 bits). In this case, the signal (A) is sent out sequentially for different instruments,
The signal (B) is temporarily stored in the "lAM" in the II rhythm sound generation circuit 60.
3-bit instrument group number signal G
Address different from signal (A) for N (5 bits)
is formed by giving The signal (B) supplied to the rhythm sound generation circuit (A) enables time-divisional waveform data reading for eight rhythm instruments belonging to a specific musical instrument group indicated by musical instrument group numbers G and N. In this case, the rhythm sound generation circuit 60 supplies the address signal AD to the waveform memo 1J56 in a time-sharing manner in order to read the waveform data for one or more rhythm instruments to be sounded among the 89 rhythm instruments in the specific instrument group. do. One or more rhythm instruments to be sounded are serial data O
It is designated by the sound generation command signal NKON and pitch designation signal P and T in PO. The parallel waveform data VDT read out from the waveform memory 56 in a time-division manner is fed to the rhythm sound generation circuit 6o (IT), and the parallel (P)/serial (S)
) undergoes control processing for the after-sound of the conversion. M hand control processing uses volume control signal LV and serial data o
This is performed based on the sound string level designation signal LFiV in the PC and the volume level control signal VLC in the signal (A), and as a result, the volume of the sound of the 01 rhythm sound is adjusted according to the settings of the volumes U and 26. It is controlled in relation to the strength setting for each sound and the degree of level adjustment during waveform recording. The serial waveform data controlled last month is sent to the central speaker 40.
It is specified which of the C and left speaker 40L should produce the sound. To determine which speaker each rhythm instrument sound is produced by, please refer to Figure 2 "C" or "L" for each instrument group.
”, and the specified contents are stored in the ROM in the rhythm sound generation circuit 60 in advance. In FIG. 2, "C" and rLJ indicate that the sound should be produced from the center speaker and the left speaker, respectively. As a result of the above, the rhythm sound generation circuit 60 outputs a serial digital rhythm sound signal RTS in a time division multiplex format, and is supplied to the S/P conversion/distribution circuit 34. S/
The P conversion/distribution circuit 34 converts the rhythm sound signal RTS into S/
The signal is P-converted and distributed to either the D/A conversion circuit 36 or 64 in accordance with the above-mentioned speaker designation process. Therefore, the analog rhythm sound signal from the D/A conversion circuit 36 is sent to the central speaker 400 via the output amplifier 38.
while being supplied to the D/A conversion circuit 64 and being acoustically converted.
The analog rhythm sound signal from is supplied to the left speaker 4oL via the output amplifier 66 and is acoustically converted. Next, with reference to FIG. 6, the operation of the above-mentioned multiplex musical instrument will be explained in more detail. First, when the power switch is turned on, an initial clear signal for initialization is generated, and each register is cleared accordingly. And level memo for each instrument +
Volume level control data for each instrument is read from 154,
Each read data is transmitted via the panel data interface 62 as a signal as shown in FIG.
(IJ rhythm sound generation circuit 6). As a result, the volume level control signal V for the instrumental instrument is stored in the RAM in the circuit 6o.
LO is written, which means that the volume level for each instrument is initially set. Next, scanning of the keyboard 10 and panel operators 18A and 18B is started, and key information and operation information are detected. Then, the presence or absence of an event is determined (yes Y or no N), and if there is no event (if N), scanning is repeated. Here, if one of the rhythm selection switches A) is pressed to select a specific rhythm, rhythm designation data designating the selected rhythm is stored in the register RHYPTN of the working area 44. This is a note where events related to rhythm selection are detected.
There is an event (Y), and the rhythm set subroutine is executed. This rhythm set subroutine is executed in the rhythm pattern memory 48 according to the selected rhythm type.
This process performs processing such as setting the start address of , and will be described later with reference to FIG. Next, when setting the noise system/drum certain balance adjustment volume 24 and human-tal sound M' adjustment volume 26 to appropriate positions for rhythm volume setting, the noise system volume data is stored in the register RHOLEV, and the drum system volume data is stored in the register RHDLFiV, and the total -\fi data is stored in the register TOTLFV. Each volume data stored in this case indicates a value from 0 to 15 depending on the amount of operation of the corresponding volume. Also, since an event related to the rhythm volume setting is detected, the event is detected (Y), and the registers RHOLEV, RHDLEV and TOTLE are set as described above.
Volume control signal L using V and logarithmic volume table 52
Processing for generating V is performed. Next, when the rhythm tempo adjustment volume A is set to an appropriate position to set the rhythm tempo, rhythm tempo data corresponding to the set value is stored in the register TF3MPO. 1, an event related to the rhythm tempo setting is detected, so there is an event (Y), and the register TKM
PO rhythm tempo data is used in Rhythm Interface 5
8 is output. That is, in the rhythm interface 58 of FIG. 8, the decoder 72 that decodes the signal from the address bus 70 outputs the timing signal
When 1 is generated, this signal is supplied to the tempo register 74 as a load signal, so that the register 74 is loaded with rhythm tempo data of data bit 0=5 (6 bits) from the data bus 76. Rhythm tempo data from register 74 is converted by tempo ROM 78 into preset data PSD for counter 80. Next, when the rhythm start/stop switch η is set to the start position, an event related to the rhythm start is detected, an event is detected (Y), and the rhythm run flag is set. That is, register RHYRUN
"80" in hexadecimal format (rloooo in binary format)
ooo J) is set. In the rhythm interface shown in FIG. 8, an 11-rhythm tempo synchronization operation is performed. Specifically, the function register 8
2 is loaded with "01" in hexadecimal notation, and in response, register 82 generates a start signal 5TRT, which is then automatically cleared. Since the start signal STRT resets the frequency division counter 86 via the OR gate 84, the counter 86 receives the synchronization signal SY after being reset.
Start counting the clock signal φ from clock source 88 receiving N. The counter 86 counts the clock signal φ, and when it reaches a certain value, generates a carry signal CO. causes counter 86 to be reset via OR gate 84. Therefore, the carry signal CO, is repeatedly sent out from the counter at a constant period, and is supplied to the counter 80 as an OK input to be counted. The counter jump is the start signal 5TR from the OR gate 90.
The preset data PSD is loaded in accordance with the preset data PSD, and the carry signal CO1 of the counter is divided by a frequency division ratio corresponding to the preset data PSD. counter 8
Since the carry-out signal CO3 from 0 is supplied to the counter 80 as the load signal LD via the OR gate 90, the preset data PSD is preset to the counter 80 every time the carry-out signal C02 is generated. From 80, a carry signal CO is repeatedly sent out at a cycle corresponding to the set tempo. The OR gate 90 first generates the interrupt command signal INT in response to the start signal BTRT, and then generates the interrupt command signal NT every time the carry signal CO is generated. The interrupt command signal NT is generated 12 times within one beat, corresponding to the intra-beat timings 0 to 11, and each time the interrupt command signal NT is generated, as shown in FIG. A subroutine for generating rhythm sounds is executed as an interrupt process. Therefore, the frequency division counter 86
Rhythm sounds can be generated according to the set tempo immediately after being reset by the start signal 5TRT. The timing from which the rhythm sound is generated among the 12 interrupt timings within one beat varies depending on the type of rhythm, and is specifically determined according to the rhythm pattern data read from the rhythm pattern memory 48. After rhythm sound generation is started as described above, keyboard performance can be started in time with the automatic rhythm sound. Normally, prior to playing the keyboard, musical tone selection operations including tone color setting, volume setting, etc. are performed using the musical tone selection operator 18A before the rhythm starts. Each time such a musical tone selection operation is detected by panel scanning, an event is detected (Y
). Therefore, the musical tone selection operation data is processed, and the processed data is supplied to the key musical tone interface 16. Then, when the keyboard performance starts, an event occurs (Y) every time a key is pressed. Therefore, the key press data is processed, and the processed key press data is supplied to the interface 16. Therefore, as described above, the manual performance sound (No. It is done every now and then,
Every time the interrupt command signal INT is generated (12 times within one beat)
(times)) is interrupted for interrupt processing and restarted each time the interrupt processing is completed. When the rhythm start/stop switch 22 is set to the stop position during or after the keyboard performance, an event related to a rhythm stop is detected. For this reason,
An event has occurred (Y), and rhythm stop processing such as buffer clearing is performed. In FIG. 8, the function register 82 has a timing signal R.
In response to HYDFi04, "04" is loaded in the 16'a format, and in response, the register 82 generates a buffer clear signal BUFOL. This signal BUFOL is OR
The signal is supplied to a shift register (S/R) 94 via a gate 92 and to a shift register 98 via an OR gate 96. The shift registers 94 and 98 are both 8 stages/1 bit, and include a channel frequency divider circuit 3 that divides the frequency of the clock signal φ according to the synchronization signal SYN.
It is timed by the channel timing signal OhT from 00. The buffer clear signal BUFCL transfers the contents of shift registers 94 and 98 to 8 channels (8 instruments).
After that, the register 82 is automatically cleared. Next, the timing signal RHYDEC is stored in the register 82.
4, "2o" is loaded in hexadecimal notation, and in response to 1, the register 82 receives the data transfer command signal TRAN.
occurs. This signal TRAN is supplied to the p/s conversion circuit 102. Therefore, P/S conversion circuit 1
02 is the sound generation command signal NKON from the shift register 94
, mute command signal f=vNKOF from shift register invitation,
By loading the pitch and volume level signals P and LFiV from the shift register 118, which will be described later, one channel at a time in accordance with the channel timing signal OhT, sending them out in accordance with the clock signal φ, and repeating this eight times. Each signal for all eight channels is sequentially sent out as serial data OPO. In this case, since the signals NKON and NK,OF are both %l# for each channel, as will be described later, as a result, the rhythm sound is forcibly attenuated. Note that the register 82 is automatically cleared after the data OPC is sent by the signal TRAN. Furthermore, the shift registers 94 and 98 are connected to the inverter 12.
The data transfer command signal TRAM supplied to AND gates 126 and 128 via 2 and 124 causes all 8 channels to become O1. After this, initialization is performed by clearing the rhythm-related registers. Next, the rhythm set subroutine will be explained with reference to FIG. It is determined whether the contents of the square and rhythm run flag RHYRUN are rhythm runs. If the flag RHYRUN is 0, it is not a rhythm run (during rhythm performance), and if it is not 0, it is a rhythm run. There is no rhythm run before the rhythm starts (N
), so we move on to processing the progressive beat number set. The number of progressive beats is either 0 to 2 if the beat is 3 beats, or 0 to 3 if the beat is 4 beats. The number of beats in triple time is 0.1.
2 corresponds to the in-measure timing (count value of counter T, M, NG) from 0 to 11.12 to 23.24 to 35, respectively, and the number of beats in the case of 4 beats is 0.1.2.3. Intra-measure timing 0-11.12-23.24-35.
36 to 47, respectively. Before the rhythm starts, the beat count is 0 in any case, and 0 is written in the register HKPFi. Next, it is determined whether it is a rhythm run again. Since it is not a rhythm run before the rhythm starts, processing moves to the start address set for the rhythm pattern memory 48. This process is
The contents of the pattern start address memory card are read out based on the rhythm specification data from the register RHYPTN and set in the start address RHYROM. The first address data is read and stored in memory R.
)! Written to YROM. Next, rhythm pattern data reading and address pointer setting processing are performed based on the head address data from the memory RHYROM. That is, in this process, rhythm pattern data corresponding to a specific rhythm is read from the rhythm pattern memory 48, and is stored in the register HKP.
According to the contents of K and counter T, the channel timing data (first byte of event data) to be read first during the next interrupt processing is searched, and the address of the channel timing data is set as the address. Set in pointer RHPNT. Before the rhythm start, register HKPK and counter T and M are NG.
Since the contents of both are 0, the address pointer RHP
1 is written to NT to indicate the address following the first address. Next, the instrument group poumba data corresponding to the particular rhythm read from the rhythm pattern memory 48 is sent to the panel data interface 62, and in response, the interface 62 performs a A rhythm control signal is supplied to the 11th rhythm sound generation circuit mark. After this, it is determined whether the specific rhythm indicated by the rhythm designation data is a triple beat, and if it is a triple beat, the register TMPMA is
A maximum timing value of 35 is set in X, and if it is not a triple beat (it is a quadruple beat), a maximum timing value of 47 is set in the register TMPMAY. The above is the flow of the rhythm set process before the rhythm start, but the flow of the rhythm set process when there is a rhythm change after the rhythm start is as follows. In this case, since the rhythm has started, it is determined that it is a rhythm run (Y), and the pattern change flag PC! H
NGF is set. That is, the flag POHNGF
``01'' is written in hexadecimal notation, and this makes it possible to forcibly attenuate the previous rhythm sound at the next interrupt timing. Next, we move on to processing the progressive beat number set, register HKPI
! The number of progressing beats at the time of rhythm change, for example 2 (corresponding to the third beat), is written in i. At this time, the contents of the in-measure timing counter T, M, and NG are stored in the register HK P J! If the content of i is 2, it is any value from 24 to 3!5,
For example, it is 29. After this, it is determined whether it is a rhythm run again, and since it is a rhythm run, the beat end/return flag Fj HHK
Proceed to ND clear processing. This process is flagged as RHH.
F, ND (HO) is written, and since the address pointer RHPNT is newly set after this, it is necessary for proceeding with the interrupt processing described later. Address set processing is performed.In this case, register RHYP
Since the rhythm specification data corresponding to the newly selected rhythm is stored in TH, the start address data corresponding to the newly selected rhythm is read from the pattern start address pointer, and the start address data corresponding to the newly selected rhythm is read out from the start address memory RHYROM.
written to. Next, rhythm pattern data corresponding to the newly selected rhythm is sequentially read out from the rhythm pattern memory 48 based on the leading address data from the memory RHYROM, and address pointer setting processing is performed. In this process, if the contents of register HKPK are 0 (1
If it is a beat), the data of the counter T MING and the intra-beat timing data TMG are directly compared, but the register H
If the content of KPE is 1 or more (second beat or later), the rhythm pattern data is read out sequentially and the beat change flag RD engineer S is read out.
Every time the PF force reaches l〃 (every time the beat ends), 12 is subtracted from the data of the counter T, M, NG and compared with the intra-beat timing data TMG. Then, the address of the channel timing data when the two match in this comparison is set in the address pointer RHP'NT. For example, as mentioned above, register HKPE! Assuming that 2 and 4 are contained in the counter T and MING, respectively, the beat change flag RDISPF becomes a month at the end of the first beat and the end of the second beat, so the timing value 4 to 12 is Deducted twice. Then, the value 5 obtained as a result is compared with the value of the intra-beat timing data TMG of the third beat, and a match is obtained when reading the channel timing data of the timing value 5 of the third beat. Therefore, the address when such a match is obtained is set in the address pointer RHPNT, and at the next interrupt timing, the rhythm pattern data corresponding to the newly selected rhythm is read from the timing value 5 of the third beat. It will be started. After setting the address pointer as described above, the processing of sending the instrument group number data, determining whether it is a 3-beat or 4-beat, and setting the maximum timing regarding the newly selected rhythm is the same as before the rhythm starts. It is carried out as follows. Next, the interrupt processing subroutine will be explained with reference to FIG. 1O. When an interrupt command signal NT is generated, the contents of each register are transferred to memory and saved. Then, in the same manner as described above, it is determined whether the rhythm run is a rhythm run based on the contents of the rhythm run flag RHYRUN. After setting the rhythm start/stop switch 22 to the start position, the flag RHYR
Since the content of UN is not 0, it is determined that it is a rhythm run (Y). Next, it is determined whether the rhythm has changed based on the contents of the pattern change flag POHNGF. If the flag PCHNGF is 0, it is not a rhythm change, and if it is not 0, it is a rhythm change. Normally, the rhythm is not changed immediately after the rhythm starts, so
In this case, the routine moves to the rhythm pattern processing subroutine shown in FIG. In FIG. 11, first, the beat end/return flag R
It is determined from the contents of HHEND whether it is the end of the beat. There is no beat end immediately after the rhythm starts (flag RHHK)
(ND is not 1), the contents of the address pointer RHPNT are moved to the Y register. Then, using the value obtained by adding the start address memory RHYROM and the Y register as an address, a channel consisting of the J-th byte data from the first event data EVT corresponding to the selected rhythm, that is, the channel number CHN and the intra-beat timing TMG. and timing data to rhythm pattern memory 4
Read from 8 and put it in A register. Next, set the channel timing data of the A register to
After transferring to the register, the lower 4 bits of intra-beat timing data TMG are extracted from the channel timing data of the X register and placed in the A register. That is,
In this state, intra-beat timing data TM is stored in the A register.
G, the X register contains channel number data OHN and intra-beat timing data TMG. Next, it is determined whether the timings match by comparing the contents of the A register, that is, the intra-beat timing data TMG, and the contents of the intra-beat timing counter TMPONT. At this time, assuming that timing matching cannot be obtained,
This means that the timing within the first beat (counter TMPC!
A count value of NT (0) means that there is no event data to be generated. In this case, it is determined whether the value of the intra-beat timing data TMG of the A register is greater than "OD" in hexadecimal, that is, whether it is a beat end/return. Since it is not the beat end/return now, the contents of the Y register are transferred to the address pointer RHPNT and the rhythm pattern processing ends. Next, the process moves to data transfer command output processing shown in FIG. This process is performed in the same way as described above regarding the rhythm stop, and the P/S conversion circuit 102 in FIG.
Send to i next time. Therefore, in this case, no instrument sound is generated for the selected rhythm. After that, the counter TMPONT is incremented by one force, and then it is determined whether the count value of the counter TMPONT is equal to 11, that is, a beat has exceeded. Since the beat is not over at the moment, the in-measure timing counter T, M, NG is incremented by one, and then the previously saved register contents are restored. This completes the first interrupt processing and returns to the normal processing such as keyboard/panel scanning as shown in FIG. The second and subsequent interrupt processing is performed in the same manner as above unless timing coincidence is obtained. By the way, assuming that the first intra-beat timing data TMG indicates a timing value of 5, timing coincidence is obtained in the process of the ffllll diagram during the sixth interrupt process. In this case, 1 is added to the contents of the X register and the read at I/S is advanced by 1. Then, using the start address memory RHYROM and the X register, the second byte data from the first event data EVT, that is, the pitch P
Pitch level data consisting of the pitch T and the volume level LEV is read from the rhythm pattern memory 48 and written to the A register. Next, data output processing is performed. That is, among the pitch-level data of the A register, level data T
JEV is sent to the data bus 6 in FIG. 8 as a 3-bit signal of data bits 0 to 2, and pitch data P is sent to the data bus 76 as a 4-bit signal of data bits 4 to 7. be done. The pitch and level data of these 7 pits in total are then sent to the timing signal RH.
Y D E O2m is loaded into the data register 104 accordingly. In addition, the channel number data OHN of the X register is sent to the -C data bus 76 as a 3-bit soto Q) signal of data bits 4 to 6, and the timing signal RHYDE
C3 is loaded into the channel register 101'i. At this time, the timing signal RHYDKO: (
Since RS flip-flop "108" is turned on, the ND gate 110 becomes conductive to the output Q-%1#.Comparator circuit 11
2 compares the division output of the channel counter 114, which counts the channel timing signal ChT, with the channel number data CHN from the channel register 106, and when the two match, generates a match signal gQ=J4. This match signal EQ resets the flip-flop 108 via an AND gate 110, and is supplied from the AND gate 110 to a selector 116 as a selection signal SB for selecting input B. Therefore, the pitch-level data from the data register 104 is transferred to the selector 1.
8 stage 15 bit shift register 1 through 16
18 and stored. The match signal IQ from AND gate 110 is also provided to shift register 94 via OR gate 92 and stored, as well as inverter 120 and AND gate 1.
It is supplied as a signal 0 to the shift register 98 via 28 and stored therein. Shift registers 94, 98 and 118 operate in synchronization with each other by a channel timing signal ChT, so that data relating to a particular rhythm instrument (for example) stored in each corresponding stage is transferred to the channel. It is stored cyclically in accordance with the timing signal OhT. The signals NKON and NKOF stored in this case are -]# and 0', respectively. After the data output processing as described above, 1 is further added to the contents of the X register and the read address is incremented. Soshi C1
Using the head address memory RHYROM and the X register, the channel timing data of the second event data EVT is read from the rhythm pattern memory 48 and written to the A register. Next, in the same manner as described above, the contents of the A register are transferred to the X register, and the intra-beat timing data TMG is extracted and placed in the A register. Then, as described above, it is determined whether the timing matches by comparing the contents of the A register and the contents of the counter TMPONT, and if the timing matches, the pitch level data is read out in the same manner as before. The movements are repeated. As a result, data regarding all instruments (up to eight instruments) to be sounded at intra-beat timing "5" are stored in shift registers 94, 98 and 118 in FIG. In the shift registers 94, 98 and 118, all bits of channels corresponding to musical instruments that do not produce sound are %ON. After all the event data for intra-beat timing 5 has been read out, timing data TMG indicating an intra-beat timing value greater than 5 is read out and written to the A register, so timing coincidence is no longer obtained and the beat end/beat timing value is greater than 5. Move on to determining whether it is 11 turns. Since it is not the beat end/return now, the contents of the Y register are transferred to the address pointer RT (PNT) and the rhythm pattern processing ends. At this time, the address pointer RHP
The address of the timing data TMG previously written to the A register is written into NT, and the next event data reading is started from this address. Next, the process moves to the data transfer command output shown in FIG. 10, and the shift register 94.98.1 shown in FIG.
The contents of 18 are loaded into the P/S conversion circuit 102 for each musical instrument, and the serial data o is output from this conversion circuit 102.
pa is sequentially transmitted for each instrument for eight instruments, and a corresponding rhythm sound is produced based on the data that is the sound generation command signal NKON chi 1# among the transmitted data. Note that during the sending operation of the serial data opc, the transfer command signal TRAM=11# is input to the inverters 122 and 12, respectively.
Shift registers 94 and 98 are cleared because AND gates 126 and 128 are controlled non-conducting through V4. In addition, the output signal %] of the inverter 120 is supplied to the selector 116 as a signal SA for selecting input A, so the data in the shift register 118 is transferred to the selector 116.
16. After this, in FIG. 10, the counters T M P ON T and T MING are each set to 1 in the same way as described above.
After incrementing the power count and restoring the contents of each register, 6
Finishes the first interrupt processing. At the first beat, when the above-described interrupt processing with or without sound generation is repeated several times, the lower four pits of the first beat end data Bffl are written into the A register. Therefore, the determination result of beat end/return in FIG. 11 is affirmative (Y), and a determination of return is made. Since this is not a return, we move on to processing the beat end/return flag RHHEND and set the flag RHHK.
The contents of the A register (lower 4 bits of beat end data BE) are written to ND. Then, the contents of the Y register are changed. In this case, since it is the beat end, the contents of the Y register are the data (2) following the first beat end data BFJ.
The address is changed to the address of the first channel timing data of the beat. This example converts the contents of the Y register to the address pointer RHP.
Move to NT and finish the rhythmic turn process. Next, the process moves on to the process after outputting the data transfer command shown in FIG. 10, a rhythm sound is produced in the same manner as described above, and this round of interrupt processing ends. In the next interrupt processing, the beat end/return flag RHI (END) is set to the beat end as described above, so the determination result of the beat end in FIG. The routine in Figure 11 immediately ends.Then, the processing after the data transfer command output in Figure 10 is performed, but since both NKON and NKOF are 101, no rhythm sound is generated.Rhythm sounds are generated in this way. When the interrupt processing that is not performed is repeated several times, the count value of the counter TMPONT becomes 11.Then, the determination result of whether the beat is over in FIG. 10 becomes affirmative (Y), and the in-measure timing counter T
Engineering M Engineering NG is incremented by one force, and the count value becomes 12. Next, it is determined whether the measure is over, but since it is not over the measure now, the beat end/return flag RHHKN]
) Proceed to the reset process. t, that is, the flag RHT(E
0 is written to ND. And counter TMPCN
After resetting T and restoring the contents of each register, 1
Finishes the interrupt processing at the end of the beat. In the first interrupt processing of the second beat, the flag RHHT'L is first set.
Since ND has been reset, the determination result of the beat end in Figure 71511 is negative (N), and the Y register contains the next data of the first beat end data BE from the address pointer RHPNT to the Y register. is set. Therefore, event data reading is started from the first channel Φ timing data of the second beat. After the first interrupt process for the second beat is completed, the interrupt process with or without sound production is repeated in the same manner as described above until the final beat in the format shown in FIG. 3. Then, at the final beat, when the interrupt processing is repeated several times, the lower @i4 bit of the return data RTH is written into the A register. Therefore, the determination result of beat end/return in FIG. 11 is positive (Y), and it is determined whether it is a return. Since this is a return, the Y register is reset. That is, 100'' is written in the Y register in hexadecimal notation. Next, processing is performed to set the beat end/return flag RHHKN I), and the contents of the A register (lower 4 bits of return data RTN) are written to the flag RHHEND. Then, the contents of the Y register are changed. In this case, since it is a return, the contents of the Y register are changed to the address C next to the first address (corresponding to the first channel timing data). After this, the contents of the Y register are transferred to the address pointer RHP.
Transfer to NT and finish rhythm pattern processing. Next, the process moves on to the process after outputting the data transfer command shown in FIG. 10, a rhythm sound is produced in the same manner as described above, and this round of interrupt processing ends. In the next interrupt process, the beat end/return flag RHHKND is set to return as described above, so
The determination result as to whether the beat is at the end in FIG. 11 becomes affirmative (Y), and the routine in FIG. 11 ends. And the 10th
Processing after the output of the data transfer command shown in the figure is performed, but no rhythm sound is generated. When the interrupt processing in which no rhythm sound is generated is repeated several times, the count value of the counter MING becomes 35 for 3 beats, and 47 for 4 beats. and,
In FIG. 10, it is determined whether the bar is over. This determination is made by comparing the contents of the callan 41T and the contents of the maximum timing register TMPMAX to see if they match, and it is currently determined that they match (Y). Next, the beat end/return flag RHI (FiND) is reset. Then, the counters T and M are reset.
After resetting P(!NT, the contents of each register are restored to finish the last interrupt processing of the final beat. After this, the address pointer RHPNT is set to the address next to the first address, so the third From the first beat of the format shown in the figure, the same interrupt process as described above is repeated, and the rhythm sound is repeatedly played according to the memorized rhythm pattern. - The above is the rhythm start/stop switch ρ.
The rhythm sound generation operation starts immediately after setting the to the start position, but when the rhythm is changed after the rhythm start, the operation is as follows. That is, in this case, since the pattern change flag POHNGF is set in the process of FIG. 9 as described above, the determination result of rhythm change in FIG. 10 is affirmative (Y), and the buffer clear process is performed. Move. This process is performed in the same manner as in the case of the rhythm stop described above, and is performed by the shift register 94 in FIG.
and 98 are all 8 channels worth 1. Next, the pattern change flag POHNGF is reset, and then the rhythm pattern processing shown in FIG. 11 is started. Rhythm pattern processing in this case is executed regarding the newly selected rhythm. That is, as described above with reference to FIG. 9, the read start child address of the rhythm pattern data corresponding to the newly selected rhythm is set in the address pointer R, HPNT in relation to the progress state of the previous rhythm. Therefore, the first channel timing data after the rhythm change is read from the address indicated by the address pointer RHPNT. Thereafter, the processes shown in FIGS. 11 and 10 are performed in the same manner as described above, and rhythm sounds are produced in accordance with the newly selected rhythm pattern. In this case, the rhythm sound of the channel whose NKON and NKOF are both set to Ki II in the previous buffer clearing process is forcibly attenuated. Next, the detailed operation of the rhythm sound generation circuit 60 will be described with reference to FIG. This circuit 60 includes the rhythm control circuit 130,
It includes an attenuation control circuit 132, an address generation circuit 134, and a volume control/data output circuit 136, and generates timing signals φ, Y1 to 7. as shown in FIG. 13 from a timing signal generator (not shown). , φAB, etc., to operate. However, in FIG. 12, the timing signal φ is omitted. After initialization based on the ON operation of the power switch, the rhythm control circuit J3Q receives the rhythm control signal P for the Japanese musical instrument from the panel data interface 62 (Fig. 1).
A N (A) is supplied. This signal P A N (
A) is converted into a parallel signal by the S/P conversion circuit 138, and the address signal of the lower 5 bits of this parallel signal is decoded by the decoder 140. The signal of the (one output line 1117) line of the decoder 140 is supplied as a write address signal qWAD to the RAM 142 as a level memory for each instrument. is E
Volume level control signal VLO (
(upper 5 bits of the parallel signal) are supplied. Therefore, the RAM 142 stores volume level control signals V for four musical instruments.
The LO is written in sequence, and the volume level for each musical instrument is thereby initialized. Note that instead of initially setting the volume level for each musical instrument in the RAM 142 as described above, a ROM may be provided in which the volume level for each musical instrument is set in advance. Thereafter, when the rhythm set is processed as described above, the rhythm fli control signal PAN(B) is supplied to the rhythm control circuit 130 from the panel data interface 62. This signal P A N (B) is converted into a parallel signal by an S/p conversion circuit 138, and the lower 5 bit address signal of this parallel signal is decoded by a decoder 140. Among the output lines of the decoder 140, the signal on the 29th line is supplied to the latch circuit 144 as a load signal LD, and as the data input of the latch circuit 144, the signal on the 29th line is S/7.
P conversion circuit 138 to instrument group number signal engineering GN
(lower 3 bits of the upper 5 bits of the parallel signal) are supplied. Therefore, the latch circuit 144 latches the musical instrument group number signal GN in response to the load signal LD and supplies it to the ROM 146. The ROM 146 stores instrument name data corresponding to eight instruments for each musical instrument group, and also stores noise system/drum system designation data and center speaker/left speaker designation data for each instrument in each musical instrument group. These data are read and output from the ROM 146 using the instrument group number signal GN from the latch circuit 144 and the 3-bit count output of the counter 148 that counts the timing signal φAB as address signals. There is. For example, if the value of the instrument group number signal engineer GN is 1 and the rhythm type of waltz and ballad in Figure 2 is specified,
From the ROM 146, when the count value of the counter 148 (channel number 0HN) is O, 5 indicates the instrument name TOY.
Parallel 7-bit data consisting of a combination of 1-bit data, 1-bit data indicating that this instrument TOY is a noise type, and 1-bit data indicating that the instrument TCY should be sounded from the left speaker is read out. As the count value of the counter 148 changes from 1, 2, 3, . As the counter 148 repeats the counting operation for eight channels (eight musical instruments), data reading from the ROM 146 is also repeated. From the rhythm interface 58 (ffi8 figure), serial data opc for the first eight instruments including sound generation commands is 1
When supplied to the 1 rhythm control circuit 130, this data OP
C is S/P in the S/P conversion/latch circuit 150
converted and temporarily stored. Here, for the sake of simplicity, it is assumed that the serial data OPC for the first eight instruments includes a sound generation instruction only for the top cymbal TOY (channel number o) of instrument group number I in FIG. 2. - The latch circuit 150 outputs the sound generation command signal NKON-%l# and the mute command signal NK at the timing of channel number O.
OF-%Q# is sent out, and at the timing of channel numbers 1 to 7, %0〃 is sent out as signals NKON and NKOF''.These signals NKON and NKOF'' are sent out.
KOF is the t1 signal NKO supplied to the attenuation control circuit 132.
N is connected to the first input of AND gate 152 with signal NKO.
F is applied via an inverter 154 to a second input of an AND gate 152, respectively. At this time, the signal %11 is supplied from the inverter 156 to the third input terminal of the AND gate 152. Therefore, AND gate 35
2 generates an output signal s1t in response to signals NKON and NKOF at the timing of channel number 0. This output signal Q) is supplied to an 8-stage/1-bit shift register 160 via an OR gate 158, while it is supplied to a NANI) gate 164 via an OR gate 162.
supplied to At this time, inverters 166 and 168
supplies the signal -1# to the NAND gate 164, so the NAND gate 164 generates the output signal sum in response to the output signal 11# of the OR gate 162. This output signal sum l is supplied to an 8-stage/1-bit shift register 172 via an AND gate 170. Therefore, the channel number O of the shift register 172
The signal %ON is written to the stage corresponding to the timing signal φAFI in accordance with the timing signal φAFI. At the same time, it corresponds to channel number 0 of shift register 160.

The signal -1# is written to the stage [7] in response to the timing signal φA8. The shift registers 160 and 172 perform a synchronous shift operation in response to the timing signal φA0, and as a result, the stages corresponding to channel numbers 1 to 7 of the shift register 160 are not reached. Also, %O# is channel number 1 of shift register 172.
Izu LL and Mo 11 are included in the stages corresponding to ~7. When the signal %OI appears at the output of the shift register 172, this signal 0 makes the gate I circuit 74 conductive. Therefore, the stage corresponding to channel number 0 of the 8-stage/7-bit shift register 176 has the output of the shift register 176 (all bits %O").
Addition circuit 1 that adds %】# to the least significant pit (LSB) of
78 output data is written in response to timing signal φAB. The output of the shift register 160 is fed back to the input side via the AND gate 18() and the O'R gate 158, so that the signal NKON=gIv is stored cyclically. Therefore, every time the output of the shift register 2 and 160 reaches 1, the shift register 172 has an OR gate 182.
and 10' is written through the AND gate 170, and each time the output output of the shift register 172 becomes 0, the value of the data at the stage corresponding to channel number 0 of the shift register 176 increases by 1. . When the frequency of data sent from the shift register 176 reaches a predetermined value, the end detection circuit 184 outputs an attenuation end signal D.
PFi=%]# is generated. This signal DPE causes AND gate 180 to become non-conductive through inverter 156, so that the stored data in the circuit including shift register 160 is cleared. Further, since the signal DPB is supplied to the AND gate 170 via the OR gate 182, the output signal of the AND gate) 170 is 1#, and this signal \1
sets the contents of the stage corresponding to channel number O of the shift register 172 to 'l*. Therefore, when data IA1 corresponding to channel number O appears on the output side of the shift register 172, the gate circuit 174 is not conductive, so that the count data of the shift register 176 is cleared. Incidentally, the signal DPFj is supplied to the selectors 186 and 188 of the rhythm control circuit 130 as a signal SB for selecting input B. For this reason, 8 stages/
The 7-pit shift register 90 contains 7-pit instrument name, noise system/drum system, center speaker/left speaker designation data from the ROM 146, and the 8-stage 15-bit shift register 92 stores S/Pq conversion/latch circuit 15.
Pitch level designation data of 0 to 5 bits is supplied respectively. Shift registers 90 and 192 each shift channel number 0 according to the 4-if flag signal φAB.
The supplied data is imported into the corresponding test module and shifted sequentially. Selectors 186 and 188 are shift register 1, respectively.
After supplying data to 90 and ]92, signal DPE=%Ol
The state is set to select input A, and the contents of shift registers 9Q and 192 are changed to selectors 186 and 1, respectively.
88, it is stored and stored cyclically. 5-bit top cymbal TO corresponding to channel number 0 sent out in a time-division manner from shift register 90
Since the instrument name designation signal GS representing Y is supplied to the RAM 142 as the read address signal RAD, the RAM
42, a 5-bit volume level control signal VLO corresponding to channel number 0 of the top cymbal TOY is read out in a time-division manner. Further, the 5-bit instrument name designation signal %GEt from the shift register 190 is sent to the address generation circuit 134 along with the 2-bit pitch designation signal Pt from the shift register 192.
The start/end address data ROM 194 is supplied as an address signal. Therefore, from the ROM 194, the waveform memory 5 in FIG.
At step 6, the start address data SAD and end address data EAD necessary for reading out the waveform of the top cymbal having the pitch indicated by the pitch designation signal PT are read out in a time-divisional manner. The 8-stage/1-bit shift register 196 receives an initial clear signal IC= generated when the power is switched on.
%II is received via the OR gate 198, and 11# is written in all stages according to the timing signal φ^B, and the contents of the shift register 196 are the OR gate 200, the AND gate 202, and The data is stored cyclically via the OR gate 198. In the attenuation control circuit 132, as described above, the signal DP
When E is generated, the AND gate 2(34Q) 3 becomes 111, and the AND gate 204 supplies the read command signal RI=%QI to the AND gate 202 of the address generation circuit 134. Therefore, AND gate 202 becomes non-conductive, and 10# is written in the stage corresponding to channel number 0 of shift register 19f'i in response to timing signal φA+1. When this signal O# appears on the output side of the shift register 196, this signal 10# makes the gate circuit 208 conductive via the OR gate 206. When the gate circuit 208 becomes conductive, the stage corresponding to channel number 0 of the 8-stage/15-bit shift register 210 receives -1 at the lowest pitch (LSB) of the output (all bits % ON) of the shift register 210. The output data of the adder circuit 212 that adds # is the timing signal φA
He died according to B. Since the gate circuit 208 becomes conductive every time the output of the shift register 196 becomes OI, the value of the data in the stage corresponding to channel number 0 of the shift register 2]0 increases by 1 each time the gate circuit 208 becomes conductive. do. The 7-bit start address data SAD from the ROM 194 is sent to the shift register 2 as an upper bit signal.
The 15-bit data from No. 30 are respectively supplied to an adder circuit 214 as lower bit signals and added together. As a result, an 18-bit address signal AD corresponding to channel number 0 is sent out in a time-division manner from the adder circuit 214, and is supplied to the waveform memory 56 in FIG. Therefore, the waveform data of the top cymbal having the pitch specified by the pitch designation signal PT is read out from the memory 56 in a time-division manner in accordance with the address signal AD. The waveform data WDT read at this time has 8 bits for each sample, and is sequentially supplied to the volume control/data output circuit 136. The 5-bit output data from the adder circuit 212 is compared with the 5-bit end address data EAD from the ROM 194 in the comparator circuit 216.
The comparison circuit 216 outputs a match signal W when both comparison inputs match.
Q −' ] ' is generated. This match signal EQ is OR
The gate circuit 208 is made non-conductive via the gates 21R and 2()6, and the AND gate 202 is made conductive via the OR gates 218 and 200. Therefore, channel number 0 of the shift register 210
The contents of the stage corresponding to channel number 0 of the shift register 196 are cleared, and the month is set to 1 in the stage corresponding to channel number 0 of the shift register 196. As a result, reading of waveform data from the waveform memory 56 ends one address before the address indicated by the end data EAD. 8-bit waveform data WDT for each sample is supplied from the waveform memory 56 to the volume control/data output circuit 136.
consists of exponent bits and mantissa bits, and R
Log/linear conversion is performed by OM220. ROM
The 18-bit waveform data for each sample from 220 is P/S converted by a P/S conversion circuit 222,
lt, is supplied to the multiplication circuit 224. 8/P conversion/latch circuit 226 receives volume control signal TJ from panel data interface 62 (FIG. 1).
The 8-bit noise volume level designation signal NLEliV and the 8-bit drum sound level designation signal DLEV are sent to selector 2.
28. The selector 228 selects the signal NLIUV or DLKV according to the noise system/drum system designation signal BAL from the shift register 190, and the selected signal is supplied to the adder circuit 230, which outputs the volume level control signal LC from the RAM 142. is added. That is, when the top cymbal waveform data is read out as described above, the adder circuit 230 selects the selector 22.
Noise volume level designation signals NLEV and RA from 8
The volume two-level control signal VLO for the top cymbal from M142 is added, and this creates a volume that takes into account the noise/drum volume balance by volume U, the total volume by volume 26, and the degree of volume level adjustment during recording. Control becomes possible. The addition output signal from the addition circuit 230 is applied as one addition input to the addition circuit 232, and the signal obtained by logarithmically converting the volume level designation signal LEV from the shift register 192 in the ROM 234 is added as the other addition input of the addition circuit 232. It will be done. For this reason, the adder circuit 232 sends out volume control data that takes into account the strength and weakness of each note. The adder circuit 236 receives the volume control data from the adder circuit 232 and the attenuation control data DU from the shift register 176.
While the count value of the shift register 176 is increasing, volume control data is sent to forcibly lower the -C rhythm volume, but while the shift register 76 is being cleared. is the damping control data DUM
Since this is the all-pit controller, the volume control data from the adder circuit 232 is sent out as is. The volume control data from the adder circuit 236 has the upper 4 bits as exponent bits and the lower 5 bits as mantissa bits, and the signal of the mantissa bits is log/linear converted in the conversion circuit 238 and converted into an 8-bit signal. The signal is supplied to a multiplication circuit 224. The multiplication circuit 224 multiplies the serial waveform data for each sample from the P/S conversion circuit 222 by the volume control data from the conversion circuit 238, and the multiplication output data for each sample is supplied to the level shift circuit 240. Ru. The level shift circuit 240 outputs data from the multiplier circuit 2 according to the exponent part data of the upper 4 bits of the output data of the adder circuit 236.
The U-bit serial waveform data from this circuit 240 is supplied to a distribution circuit 242 for each sample. What has been described above is the waveform data reading and volume control operation for one note at the first sound generation timing, but in the same way, the waveform data reading for multiple notes (up to 8 notes) can be performed. Output/volume control operations are performed. In this case, serial waveform data corresponding to a plurality of rhythm sounds is supplied from the level shift circuit 240 to the distribution circuit 242 in a time-division manner. In addition, at the next sound generation timing, the previously sounded one or more musical instrument sounds are forcibly attenuated by the attenuation control data DUM, and then the same waveform data readout and volume control operations as above are performed. Similar operations are repeated at each timing. The distribution circuit 242 includes a center speaker register 2460, a left speaker register 2716L, and a selector 248.
together with the data output circuit, and then the first
Referring to FIG. 4, the data output operation will be described with reference to I7. FIG. 14 shows a case where central speaker data is continuous (1
) and a case (2) in which data for the center speaker and data for the left speaker alternate. First, to explain case (1), the distribution circuit 24
As data input A of 2, 4 should be output from the central speaker.
Serial waveform data ■ to ■ are sequentially supplied. These data (1) to (2) each correspond to a different musical instrument, and all of them are data of bits related to a specific sample (for example, the first sample). The distribution circuit 242 is connected to the shift register 19 as a control human power B.
The center speaker/left speaker designation signal OHA is received from 0 [7, and the distribution operation is performed accordingly; in this case,
The confidence scale OHA is supplied as 1# for each channel. Therefore, all of the data 1 to 2 are distributed and supplied to the register 246 as output C. Since the register 246o circulates data internally, the same data is supplied twice in succession to the input E of the selector 248 as shown in FIG. 14(1)E. The selector 248 selects the human power E or F in response to the timing signals Y1 to 4 as the control human power G becoming %Jl or Kame 0#, respectively, so the selected output H(I) rhythm sound signal RT8) is , signal Y,
-□ Data ■, ■, ■, ■ of the register 246o are sequentially sent out corresponding to the period (1/2 channel time) of chi1#. Next, the case (2) in which data for the center speaker and data for the left speaker alternate will be described. In this case, data ■ to ■ as input A of the distribution circuit 242 are for the center speaker, and if ■ and ■ are for the left speaker, the control human power B (OHA) is the channel corresponding to the center speaker. 1# for the channel corresponding to the left speaker and 10# for the channel corresponding to the left speaker. Therefore, the data ■ and ■ are outputted to the register 246c as output C.
Then, data ■ and ■ are output to register 246L.
will be distributed and supplied to each. Similarly to the above, the registers 246c and 246L supply the same data to the selector 248 twice as shown in FIG. Select E or F alternately. Therefore, the output H (RTS) of the selector 248 is the signal Y after the central speaker data is sent out.
After one period of , ~, 4 (corresponding to one channel time), data for the left speaker ■ and data for the center speaker ■ are sent out sequentially, and then signal Y, and data for the left speaker after one period of ~24. ■ is sent. It goes without saying that the actual data output operation may be a combination of cases (1) and (2) above. If a rhythm stop or rhythm change operation is performed as described above while a rhythm sound is required based on the serial rhythm/sound signal RTS sent out in a time-divisional manner from the selector 248 as described above, , in FIG. 12, the E/P conversion/latch circuit 150 receives the signal NKON=
%l# and the signal N K OF =%l# are sequentially sent out for eight channels and supplied to the AND gate 250. At this time, AND gate 250 is receiving output signal %1# of inverter 156. Therefore, the AND gate 250 generates an output signal -1, and this signal %11 is passed through the OR gate 162 to the NA
ND gate 164 is supplied while OR gate 252
8 stage/1 bit shift register 254
supplied to A signal 1 is written into each of the eight stages of the shift register 254 in accordance with the timing signal φAB. Also, this signal! 1° of 11
The output signal of the NAND gate 164 is 0#,
This signal type 0 is supplied to the shift register 72 via an AND gate 170. Therefore, signal IO# is written into all eight stages of shift register 172 in accordance with timing signal φA8. Since the signal 0 sent out from the shift register 172 makes the gate circuit 174 conductive, the shift register 76
The output data of the adder circuit 178 is sequentially written to the eight stages. The contents of the shift register 254 are stored cyclically through the AND gate 256 and the OR gate 252, and the contents of the shift register 172 are also stored cyclically through the OR gate 182 and the AND gate 170, so that the shift The data value of each stage of register 176 increases by 1 as described above. When the data value of each stage of the shift register 176 reaches a predetermined value, the end detection circuit 1 outputs an attenuated end signal])
Sequentially transmit p E = % 1 # for 8 channels. The output data of the shift register 176 up to the generation of the signal DPE is sent to the adder circuit 236 as attenuation control data DUM.
, and acts to forcibly attenuate all rhythm sounds being produced. The attenuation end signal DPE is ANDed via the inverter 156.
Since the gate 256 is made non-conductive, the shift register 25
The stored data of the circulation path including 4 is cleared. Further, the signal DPE inputs the contents of each stage of the shift register 172 through an OR gate 182 and an AND gate 70.
At the end, the output signal Q1 from the shift register 172 makes the gate circuit 174 non-conductive. As a result, the count data of the shift register is cleared at each stage. In the case of a rhythm change, serial data opc including a sound generation command is then supplied, so that rhythm sounds are produced in accordance with the newly selected rhythm pattern in the same manner as described above. That is, in this case, after the previous musical instrument sound according to the previous rhythm pattern is forcibly attenuated, the musical instrument sound according to the new rhythm pattern is played. As described above, according to the present invention, since the playback volume level is automatically controlled based on the stored data,
For low-volume rhythm instruments, the S/N ratio can be improved by raising the volume level when recording the waveform. E. The automatic rhythm performance device described above performs waveform data readout and volume control operations in a time-division manner, so it can generate a large number of instrument sounds for each rhythm type using a relatively simple circuit configuration. It has the advantage of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic musical instrument equipped with an automatic rhythm playing device according to an embodiment of the present invention, and FIG. ), Figure 3 is a diagram showing the format of rhythm pattern data, Figures 4 (a) to (c) are waveform diagrams illustrating rhythm waveforms to be stored, and Figure 5 is a diagram showing the format of rhythm pattern data. 6 is a flowchart for explaining the operation of the electronic musical instrument shown in FIG. 1. FIG. 7 is a flowchart for interrupt processing. is a circuit diagram of the rhythm interface, FIG. 9 is a flowchart showing the rhythm set subroutine, FIG. 10 is a flowchart showing details of interrupt processing, FIG. 11 is a flowchart showing the rhythm pattern processing subroutine, FIG. 12 is a circuit diagram of the rhythm sound generation circuit, and FIGS. 13 and 14 are time charts for explaining the operation of the circuit of FIG. 12. 18B...Rhythm operator, 42...Central processing unit, 48...Rhythm pattern memory, 54, 142.
... Level memory for each musical instrument, 56... Rhythm sound waveform memory, 58... Rhythm interface, 60... Rhythm sound generation circuit, 62... Panel data interface, 130... Rhythm profit circuit, 132... ...Attenuation control circuit, ]34...Address waste generation circuit, 136...
Volume control/data output circuit.

Claims (1)

[Claims] 1. A first device that stores waveform data corresponding to a rhythm sound waveform.
a second memory storing timing data indicating the sounding timing of the rhythm sound waveform;
a first reading means for reading out the timing data from the memory; and an address signal to the first memory for reading out the waveform data at each sound generation timing indicated by the timing data read out from the second memory. an address generator for supplying; a third memory storing volume control data regarding the rhythm waveform; a second reading means for reading the volume control data from the third memory; An automatic rhythm performance device comprising: a volume control circuit that controls the volume of rhythm tones based on waveform data from the first memory in accordance with read volume control data. 2. A first memory storing waveform data corresponding to a plurality of rhythm sound waveforms, a second memory storing timing data indicating sound generation timings of the plurality of rhythm sound waveforms, and a second memory storing waveform data corresponding to the plurality of rhythm waveforms; a third memory storing volume control data; an @l address generator supplying an address signal to the third memory for time-divisionally reading out the volume control data; reading means for reading timing data; reading the waveform data from the second memory and time-divisionally reading the waveform data in synchronization with the read timing by the first address generator for each sound generation timing indicated by the timing data; a second address generator providing an address signal to the first memory for reading; and a waveform from the first memory responsive to volume control data from the third memory for each of the rhythm waveforms. An automatic rhythm performance device equipped with a volume control circuit that controls the volume of rhythm sounds based on data. 3. A first memory that stores waveform data corresponding to a large number of rhythm sound waveforms; a second memory that stores timing data that indicates the sounding timing of a plurality of rhythm sound waveforms for each rhythm type; a third memory that stores volume control data regarding the plurality of rhythm waveforms; a first address generator that supplies an address signal to the third memory to read out the volume control data in a time-sharing manner; reading means for reading out the timing data from the second memory; and reading means for reading out the timing data from the second memory, and reading out the waveform in synchronization with the readout timing by the first address generator for each sound generation timing indicated by the timing data read out from the second memory. a second address generator for supplying an address signal to the first memory to read data in a time-divisional manner; a volume control circuit for controlling the volume of the rhythm sound based on the waveform data from the first memory, a rhythm selection means, and successive addresses of the second and third memories according to the rhythm type selected by the rhythm selection means. 1. An automatic rhythm performance device, comprising: means for changing a rhythm, and reading waveform data suitable for a selected rhythm type from the first memory in a time-divisional manner.