JPS5936432B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

In general, in bipolar transistors suitable for high frequencies or high-speed switching devices, the gain bandwidth product fT
is required to increase.

Therefore, in order to increase fT, it is necessary to reduce the element dimensions as much as possible and at the same time particularly shorten the base transit time of minority carriers. Currently, most silicon transistors are planar type, with emitters and bases formed by impurity diffusion. In this case, as the size of the emitter becomes smaller, the junction becomes a curved surface, and the effective base travel time depends not only on the base width but also on the depth of the collector-base junction. Therefore,
To improve fT, reduce the base width and at the same time
It is also required to reduce the base junction depth at the same time, and the problem becomes how to realize a shallow diffusion junction. By the way, the conventional bipolar type npn transistor
It has the structure shown in the figure.

That is, numeral 1 in FIG. 1 is a p- type silicon substrate, on which an n+ type buried layer 2 is provided, and further on the same substrate 1, an n type epitaxial layer 3. This epitaxial layer 3 is provided with a p+ isolation region 4 for element isolation. The island-shaped epitaxial layer 3 separated by the isolation region 4 has a p-type base region 5, an n+-type emitter region 6 within the region 5, and another region of the epitaxial layer 3. is the n+ buried layer 2
A collector connection diffusion layer 7 reaching up to the bottom is formed in each case. Further, a thermal oxide film 8 is provided on the n-type epitaxial layer 3, and the emitter region 6,
Aluminum electrodes 10, 11, and 12 connected to the base region 5 and the collector connection diffusion layer T are provided. However, in a transistor having such a structure, if the depth of the base region 5 is made shallow, the base resistance increases accordingly. In particular, if the base region 5 becomes extremely shallow, the base resistance will depend on the distance between the end of the base contact hole 92 and the emitter region 6. The positional relationship between the diffusion window of the emitter region 6 and the base contact hole 92 is determined by photo-etching technology, and with the current optical alignment technology, this distance l is
．． It is impossible to reduce the thickness to 5 μm or less, and there is a limit to the reduction in base resistance. On the other hand, I2L (IntegratedInjectiOnLOgi) which is a bipolar logic element
Taking d) as an example, a conventional I2L has a structure shown in FIG.

That is, 1 in FIG. 2 is a p- type silicon substrate, and this substrate 1 has an n+ buried layer 2, and further on the same substrate 1 is an n-type epitaxial layer separated by a p+ isolation region 4. Layer 3 is provided. This epitaxial layer 3
A p-type injector 13, a p-type base region 14, and a plurality of n+-type collector regions 15 are provided within the base region 14. A thermal oxide film 8 is provided on the n-type epitaxial layer 3, and the respective collector regions 15, base regions 14, Aluminum electrodes 161, 162, 17, 18, and 19 connected to the injector 13 and the extension portion 2' of the n+ buried layer 2 are provided. Such I2L is a bipolar logic element having a composite structure of a so-called reverse-operation type vertical Npn transistor in which the emitter and collector of a normal transistor are used in reverse, and a horizontal Pnp transistor whose collector is the base of this transistor. However, in the above-mentioned I2L, since the vertical Npn transistor as an inverter is inverted, the emitter-base junction area is much larger than the collector-base junction area. High-speed operation is not implemented sufficiently. That is, since carrier injection into the base is performed over the entire emitter region, which has a wide area surrounding just below the collector region, the effective base width becomes large, and therefore the current amplification factor becomes small and the FT becomes low. This had the disadvantage of interfering with I2L performance, especially switching speed.

Therefore, in order to compensate for these shortcomings, IEDMtechni
caldigestpp2Ol~204, (1979)
゛SubNanOsecOndSelf-Aligne
In dI2L/MTLCircuits'', a highly concentrated n+ type doped polycrystalline silicon layer is used for the I2L collector region, making it possible to form the base contact hole and the collector region by a self-alignment method due to the difference in the thickness of the silicon oxide film. An I2L is shown in which the base region exposed on the surface is covered with metal, which lowers the base resistance and enables device miniaturization, making it possible to create a structure in which the emitter-base and collector-base junction area ratio approaches 1. Its performance is the minimum propagation delay time Tpdmin. It shows the highest performance among conventional 12L, which is approximately 0.8 nsec.

However, on the other hand, this ゛Sub-NanOsecOnd
Self-AlignedI2L/MTLCircui
ts" has many problems. The method for manufacturing this device will be explained below with reference to FIGS. 3a-f, 4, and 5. First, an n A type epitaxial growth layer 23 is formed, and a high concentration n+ type semiconductor layer 222 is formed from the surface thereof to form an emitter region (
(Illustrated in Figure 3a).

Next, as shown in FIG. 3b, a silicon nitride film 24 of approximately 100%
A desired silicon nitride film is partially opened and the underlying n-type epitaxial layer 23 is selectively etched.

A thermal oxidation process is then performed to form a silicon oxide film 25 of about 1.0 to 1.5 .mu.m in the etched area as shown in FIG. 3c. Since this silicon oxide film 25 is provided so as to surround the periphery of the I2L gate, it is also called an oxide film collar or an oxide film separation layer, and it separates the gates of I2L and prevents minority carriers injected from the emitter to the base. It plays a role in increasing effectiveness. And silicon nitride film 24
After removing all of the silicon oxide film 26, a 5000A silicon oxide film 26 was formed again, and the desired silicon oxide film portion was opened (the third
c). Next, the base area 2T and the injector area 28
After forming, a 300% arsenic-doped polycrystalline silicon layer is applied to the entire surface.
0λ deposited, and then a CVD silicon oxide film (
CVD-SiO2) is deposited at 3000A.

This CVD-SlO2 is then patterned using photoetching technology, and further CVD-SiO2 pattern 3 is formed.
HF:HNO3:CH3COOH=1 with 0 as a mask
The arsenic-doped polycrystalline silicon layer 29 was etched with a mixed solution of 3:8 (as shown in FIG. 3d). At this time, a part of the arsenic-doped polycrystalline silicon layer 29 that was selectively left formed the collector region of I2L. It exists on the base region 2T and is used as a collector electrode lead wiring. Next, while forming the collector region 31 by diffusion from the arsenic-doped polycrystalline silicon film 29, thermal oxidation treatment was performed at a low temperature (700° C. to 900° C.) to form silicon oxide films 321 and 322.

At this time, a silicon oxide film 322 with a thickness of several hundred λ is grown on the base and injector regions, and a silicon oxide film 321 with a thickness of about 1000 to 2000 Å is formed on the surface of the arsenic-doped polycrystalline silicon layer 29. This is because the oxide film growth rate of the high concentration n+ type semiconductor layer is low temperature (700°C to 900°C).
), the oxide film growth rate is several to ten times faster than that of a low concentration p-type semiconductor layer. Subsequently, in order to reduce contact resistance with the metal electrode film, high-concentration p+ type ion implantation is performed, and the injector region 28 and external base 2T' are again diffused (as shown in Fig. 3e). Next, the injector region 28 and the external base region 2T'11. The silicon oxide film 322 with a thickness of several hundred λ is etched using a self-alignment technique, all contact holes are opened using a photo-etching technique, a metal electrode film is deposited, the electrodes are separated, and the base extraction electrode 33, I2L was manufactured by forming an injector extraction electrode 34 and an emitter grounding electrode 35 (third
Figure f (illustrated).

Incidentally, a plan view of FIG. 3f is shown in FIG. 4, and a sectional view taken along line V-V in FIG. 4 is shown in FIG. In the I2L manufactured by the above-mentioned process, the base, injector, and emitter of the element can be taken out with metal electrode films, and the collector electrode can be taken out with arsenic-doped polycrystalline silicon.
It has various features as mentioned above.

However, such manufacturing methods have various problems listed below. In the step d in FIG. 3 described above, C
When etching the arsenic-doped polycrystalline silicon film (thickness 3000λ) using the VD-SiO2 film pattern 30 as a mask, side etching is performed by the thickness of the polycrystalline silicon film, and the CVD-SiO2 film pattern 30 has an overhang shape. .

When the arsenic-doped polycrystalline silicon film 29 is oxidized in this state, a silicon oxide film 321 grows in an abnormal shape on the peripheral side of the arsenic-doped polycrystalline silicon film 29, as shown in FIG. -SiO2 film pattern 3
Push up 0. As a result, there is a drawback that the base lead-out electrode crossing the arsenic-doped polycrystalline silicon film 29 is broken. Moreover, since this arsenic-doped polycrystalline silicon film 29 is used as a first-layer wiring for connecting elements, the second-layer wiring that crosses over it is induced to break in the oxide film portions other than the element region. In addition, in the step e of FIG. 3 described above, as a means for configuring the base contact hole and the collector region 31 by a self-alignment method,
Since the difference in the growth rate of silicon oxide films due to low-temperature oxidation is utilized, shorts due to metal electrodes often occur between the base and collector.

The cause of this is that the silicon oxide film 321 grown thereon by low-temperature oxidation of the arsenic-doped polycrystalline silicon layer 29 is several times larger than the silicon oxide film 322 formed on the base region 21 as the temperature is lower. Formed thickly.
However, on the other hand, the density of the film is inferior and the insulation properties are several times worse, especially after the silicon oxide film formed by oxidizing the arsenic-doped polycrystalline silicon layer 29 at 700°C is treated with an HF-based etchant. It is very bad, and compared to a silicon oxide film formed by oxidizing a single crystal silicon layer at high temperature (1000°C or higher) of 80 to 90V with a thickness of 1000λ, a breakdown voltage of 10 to 20V with a thickness of 2000λ.
In some cases, the dielectric strength may be low or even zero. Furthermore, when observing the state after thermal oxidation, it is found that the silicon oxide film 321 grown on both sides of the arsenic-doped polycrystalline silicon layer 29 existing on the base region 27 formed in the single-crystal silicon layer is A small amount of the silicon oxide film grows at the contact portion with the region 2T), forming a concave shape. Therefore, when the silicon oxide film 322 on the side surface of the arsenic-doped polycrystalline silicon layer 29 is removed using an HF-based etchant, the silicon oxide film 322 on the arsenic-doped polycrystalline silicon layer 29 is removed as described above.
, has poor density, is weak to etchant, and base region 2? Since the contact part with the 6th part is thinner than other parts,
As shown in FIG. b, the lower side of the arsenic-doped polycrystalline silicon layer 29 in the collector region 31 is etched, and an n+ type layer is formed using the polycrystalline silicon layer 29 as a diffusion source.
The crystal region 31 is exposed from the side surface of the polycrystalline silicon layer 29. As a result, when the base extraction electrode 33 is formed,
The electrode 33 contacts the exposed portion of the collector region 31, resulting in a base-collector short circuit. The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device with high performance and high integration.

That is, the present invention has a second conductivity type in a part of the first conductivity type semiconductor layer.
a step of selectively forming a first semiconductor region of a conductive type; a step of forming an oxidation-resistant insulating film having an opening at one or more locations in the first semiconductor region on the semiconductor layer; After depositing the layer, patterning is performed to form a polycrystalline silicon pattern containing a first conductivity type impurity at least in the opening of the oxidation-resistant insulating film, and thermal oxidation treatment is performed to form at least the polycrystalline silicon pattern. a step of growing a silicon oxide film around the first semiconductor region;
a step of forming a second semiconductor region of a conductivity type; a step of removing the oxidation-resistant insulating film to form an opening for taking out the electrode of the first semiconductor region; and a step of covering the electrode wiring material layer and removing the opening from the opening. forming an electrode wiring connected to the first semiconductor region via the polycrystalline silicon pattern and insulated by a silicon oxide film provided around the polycrystalline silicon pattern. be.

The means for forming the first semiconductor region of the second conductivity type in the present invention includes a method of selectively thermally diffusing an impurity of the second conductivity type into a semiconductor layer of the first conductivity type, a method of ion-implanting the same impurity,
Examples include a method of heat treatment.

The oxidation-resistant insulating film of the present invention serves to prevent an oxidizing agent from entering the first semiconductor region under the insulating film during thermal oxidation, thereby preventing a thermal oxide film from growing in that region. .

In addition, since this oxidation-resistant insulating film has good selective etching properties with respect to the thermally oxidized film, when removing the insulating film after thermal oxidation to form an electrode lead-out opening in the first semiconductor region, there are many This method has the advantage that the insulating film can be removed without reducing the thickness of the silicon oxide film around the crystalline silicon pattern. Examples of such an oxidation-resistant insulating film include a silicon nitride film and an alumina film. As a means for forming a polycrystalline silicon pattern containing an impurity of the first conductivity type according to the present invention, for example, an undoped polycrystalline silicon layer is deposited by a CVD method, and this polycrystalline silicon layer is doped with an impurity of the first conductivity type. Then, patterning is performed by photolithography to form a polycrystalline silicon pattern containing impurities, or a polycrystalline silicon layer containing impurities of the first conductivity type is deposited and then patterned by photolithography to form a polycrystalline silicon pattern. Examples include a method of forming a pattern.

The scratched polycrystalline silicon pattern is used as an extraction electrode for the second semiconductor region or as an electrode wiring such as a diapper wiring. In order to form the second semiconductor region of the first conductivity type using the polycrystalline silicon pattern containing the impurity of the first conductivity type as a diffusion source in the present invention, a process separate from the thermal oxidation process is performed when the second semiconductor region of the first conductivity type is formed simultaneously with the thermal oxidation process. There are cases where it is done.

Examples of the electrode wiring material used in the present invention include Al or Al-Si. Examples include Al alloys such as Al-CU and Ae-Si-CU, high melting point metals such as MO, WNPt, and Ta, and metal silicides such as molybdenum silicide and tungsten silicide.

Next, regarding an example in which the present invention is applied to the production of I2L, Section T.
This will be explained with reference to Figures a to h.

Example [1] First, what? As shown in FIG.
2 (semiconductor layer of the first conductivity type) is epitaxially grown, a high concentration of phosphorus is diffused from a part of the surface of the epitaxial layer 102 to form an n+ type diffusion layer 103, thereby forming an emitter region. was configured.

Next, a silicon nitride film 10 with a thickness of 1000A is applied to the entire surface.
4 and opening a desired portion of the nitride film 104,
Using the nitride film 104 as a mask, the n-type silicon epitaxial layer 102 was selectively etched to a depth of about 0.5 to 0.7 .mu.m (as shown in FIG. 3B). Subsequently, using the same silicon nitride film 104 as an oxidation-resistant mask, thermal oxidation treatment was performed in a high temperature wet oxygen atmosphere to form a silicon oxide film 105 with a thickness of about 1.0 to 1.5 μm on the etched portion of the epitaxial layer 102. (Illustrated in Figure T c). Since this silicon oxide film 105 is provided so as to surround the periphery of the I2L gate, it is also called an oxide film collar or an oxide film isolation layer.
It serves to isolate the gates of I2L and enhance the effect of minority carriers injected from the emitter to the base. Furthermore, after removing all the silicon nitride film 104, thermal oxidation treatment is performed again to obtain the same result. Thickness 4 as shown in figure c
A thermal oxide film 106 of 000A was formed. 011 then
After the base of the thermal oxide film 106 and the injector region 108 are removed by photolithography and holes are formed, boron is thermally diffused to form the p-type base region IOT and the injector region 108.
(first semiconductor region of second conductivity type) was formed.

Next, a thickness of 1000 ml was applied to the entire surface as an oxidation-resistant insulating film.
After depositing a silicon nitride film 109 of λ by the CVD method, a part of the silicon nitride film 109 on the p-type base region IOT soil is selectively removed by photolithography to form two openings 1.
101, 1102, were formed (as shown in FIG. 1d). Marshal
Next, the entire surface is doped with arsenic, which is an n-type impurity, to a thickness of 2
After depositing a polycrystalline silicon layer of 000-3000λ,
This polycrystalline silicon layer was photo-etched to form polycrystalline silicon patterns 1111 and 1112 that partially existed within the openings 1101 and 1102 and extended in a direction perpendicular to the length direction of the base region 107 (T. Figure e).

Note that if there is no alignment error in this photoetching, side etching of the polycrystalline silicon will remove the peripheral sides of the polycrystalline silicon patterns 1111 and 1112 and the openings 110,
, 1102, a gap corresponding to the thickness of the polycrystalline silicon was formed between the inner circumferential wall surfaces of the substrates. ]V] Then, 950-1
Thermal oxidation treatment was performed at 000°C.

At this time, as shown in FIG. 7f, the oxidizing agent is prevented from entering the silicon layer under the silicon nitride film 109, and the periphery of the polycrystalline silicon patterns 111, 1112 exposed from the nitride film 109 is prevented. and openings 1101, 110
Dense silicon oxide films 112, 1122 with a thickness of 1000 to 3000 Å and excellent insulating properties were selectively formed on the silicon layer between 2 and the patterns 1111 and 1112. At the same time, arsenic-doped polycrystalline silicon patterns 111,,1
Arsenic was diffused from 112 into the p-type base region IOT, and shallow n+-type collector regions 1131 and 1132 (second semiconductor regions of the first conductivity type) were formed directly under the patterns 111 and 1112.

Subsequently, etching was performed using hot phosphoric acid, which is an etchant for silicon nitride, or a Freon-based dry etchant. At this time, since the silicon nitride film 109 has sufficient selective etching properties with respect to the silicon oxide films 1121 and 1122 surrounding the polycrystalline silicon patterns 1111 and 1112, the silicon oxide film 109 is etched as shown in FIG.
The silicon nitride film 109 was selectively removed without causing any reduction in the thickness of the base and injector openings 1141 and 1142. Subsequently, high concentration boron ions are implanted using the openings 1141 and 1142 as diffusion windows, and heat treatment is performed to make the injector region 108 a high concentration p + type, and the p type base region IOT exposed from the opening 1142 is implanted. A p+ type external base region 115 was formed (as shown in FIG. 7g).
Note that at this time, the external base region 15 separates the p-type base region IOTI and lOT2 into two p-type base regions IOTI and lOT2. [VLI
Next, an Al film with a thickness of 1 μm is deposited on the entire surface, and the electrodes are separated by photolithographic etching, and p +
Polycrystalline silicon patterns 1111, 111 connected to the mold external base region 115 and serving as collector extraction electrodes
2, the surrounding silicon oxide films 1121, 1122
Base lead-out Al electrode 116 insulated with opening 11
An injector lead-out Al electrode IIT connected to the injector 108 through 41 and an emitter lead-out Al electrode 119 connected to the n+ type diffusion layer 103 through a contact hole 118 of the silicon oxide film 106 are formed.
was manufactured (as shown in Figure 7h). According to the method of the embodiment described above, the area of the p-type base regions 1071, 10T2 can be made small, so that I2L with a high current amplification factor can be obtained.

Moreover, since the silicon oxide films 1121 and 1123 around the polycrystalline silicon patterns 1111 and 1112 after thermal oxidation treatment and removal of the silicon nitride film 109 do not have an overhanging structure on their circumferential sides, the base extraction A that crosses over the silicon oxide films 1121 and 1123 does not have an overhang structure.
It is possible to prevent disconnection of the l electrode 116, resulting in a highly reliable I? I was able to get L. In addition, the base region 10TV exposed from the openings 1101 and 1102 of the silicon nitride film 109
Not only can the Cn na type collector regions 113, 1132 be formed, but also the openings 1141, 114 as base contact holes can be formed by removing the silicon nitride film 109.
2, and arsenic-doped polycrystalline silicon patterns 1111 and 1112 as collector lead-out electrodes surrounded by silicon oxide films 1121 and 1122 can be automatically formed.
A highly integrated I2L can be manufactured.Furthermore, during thermal oxidation, since the p-type base region IOT and the injector region 108 other than around the polycrystalline silicon patterns 1111 and 1112 are covered with the silicon nitride film 109, the p-type base region 1071, 10T2, the growth of a thermal oxide film in the injector region 108 can be prevented, and polycrystalline silicon patterns 1111, 1112 can be formed without considering the growth of a thermal oxide film in that area.
can be thermally oxidized under suitable conditions, and sufficiently thick and dense silicon oxide films 1121 and 1122 can be grown. Moreover, the electrode extraction openings 1141, 11 of the base and injector
When the silicon nitride film 109 is etched away to form the polycrystalline silicon pattern 11
Since the etching has sufficient selective etching properties for the silicon oxide films 1121 and 1122 of Nos. 11 and 1112, the etching can be performed without reducing the thickness of the silicon oxide films 1121 and 1122. As a result, the n+ type collector regions 1131, 1132 formed under the polycrystalline silicon patterns 1111, 1112 form the electrode extraction openings 114.
1,1142 can be prevented from being exposed, and the base can be taken out A.
When the l electrode 116 is formed, it is possible to prevent the base-collector from shorting due to the electrode 116, and the dielectric strength voltage of the base-collector can be sufficiently improved. Furthermore, the openings 1101 and 110 in the silicon nitride film 109 on the base region
2, when forming an arsenic-doped polycrystalline silicon pattern as a collector lead-out electrode by photoetching, the polycrystalline silicon pattern is formed in the openings 1101 and 110.
Even if a positional shift occurs with respect to 2, the short circuit between the base and the collector described above can be prevented.

This will be explained below with reference to FIGS. 8a-c. first,
The opening portion 110 is formed according to the steps shown in FIG.
A silicon nitride film 109 having 1,1102 is formed.

Subsequently, a film with a thickness of 2,000 to 3
After depositing an arsenic-doped polycrystalline silicon layer of 000λ,
Patterning was performed by photolithography. At this time, due to the alignment error, the polycrystalline silicon patterns 1111', 1112' are shifted to the right by several μm as shown in FIG. A gap of several μm was created between the patterns 1112', and the right sides of the patterns 1111' and 1112' overlapped on the silicon nitride film 109 by several μm. Subsequently, thermal oxidation treatment was performed at 1000°C. At this time,
As shown in FIG. 8b, a polycrystalline silicon pattern 111,
', 1112' and the exposed p-type base region IO
Dense silicon oxide films 1121', 1122' on the T surface
Power was formed. At the same time, arsenic is diffused from the arsenic-doped polycrystalline silicon patterns 1111', 1112' into the p-type base region IOT, and the n+-type collector regions 1131', 1
132' is formed.

After that, boron is added to the silicon oxide films 1121' and 112.
After ion implantation using 2' as a mask and thermal annealing to form a p+ type external base region 115, the silicon nitride film 109 was removed using hot phosphoric acid or Freon dry etching tint. At this time, as shown in FIG. 8c, a silicon nitride film portion 109' where the polycrystalline silicon patterns 1111', 1112' and the surrounding silicon oxide films 1121', 1122' are overlapped! The hole 11 for taking out the electrode in the base after removing the silicon nitride film 109 remains.
42', the collector regions 113,', 1132' and the polycrystalline silicon 1111', 11121& are not exposed.
Therefore, according to the present invention, it is possible to prevent a short circuit between the base and the collector, which has conventionally been a problem, without taking any alignment margin when forming a polycrystalline silicon pattern. In addition,
In forming a polycrystalline silicon pattern in the present invention, the method is not limited to the above embodiment, but as shown in FIG. 9, a CVD-SiO2 film and a silicon nitride film are deposited on an arsenic-doped polycrystalline silicon layer, The silicon nitride film is patterned in the same shape as the polycrystalline silicon pattern to be formed to form a silicon nitride film pattern 120, and etched using this as a mask to form a CVD-SiO2 pattern 121. The layer may be patterned to form a polycrystalline silicon pattern 111''.

According to such a method, oxidation in the film thickness direction of the polycrystalline silicon pattern 111'' is prevented by the silicon nitride film pattern 120 during thermal oxidation, and the thickness of the polycrystalline silicon pattern 111'' serving as the collector electrode is reduced, that is, the resistance is increased. , a sufficiently thick and dense silicon oxide film 112'' can be grown around the polycrystalline silicon pattern 111''. For this reason, the collector electrode (
It is possible to lower the resistance of the polycrystalline silicon pattern (polycrystalline silicon pattern), achieve high-speed operation, and prevent the collector region 113'' and polycrystalline silicon layer 111'' from being exposed in the base electrode extraction opening after the silicon nitride film 109 is removed. Highly reliable I2L can be manufactured. Further, p and n in each region shown in the above-mentioned embodiments may all be reversed.

Moreover, in the example, the silicon nitride film was deposited directly on the single crystal silicon, but it is better to form a thin silicon oxide film and then deposit the silicon nitride film to prevent crystal defects from occurring in the single crystal silicon layer. is preferred. Furthermore, the present invention is not limited to the production of I2L as in the above embodiments,
The present invention can be similarly applied to the manufacture of Npn bipolar transistors, field effect transistors (including static induction transistors; SIT), static induction transistor logic (SITL), and the like.

As described in detail above, according to the present invention, the current amplification factor is high;
Semiconductor devices such as I2L have excellent performance such as high switching speed, can improve reliability by preventing wiring breaks and short circuits between base and collector, and can be highly integrated. It is possible to provide a manufacturing method.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional Npn type bipolar transistor, Fig. 2 is a cross-sectional view of a conventional I2L, Fig. 3 a-f is a cross-sectional view showing the manufacturing process of a conventional improved I2L, and Fig. 4 is a plan view of FIG. 3 f, FIG. 5 is a sectional view taken along the line V-V of FIG. 4, FIG. 6 a is a sectional view showing the state of the thermal oxidation process of FIG. 3 e, and FIG. 6 b is a cross-sectional view showing the state after etching in the step of FIG. 6a, FIG.
9 is a cross-sectional view showing a process during the manufacture of I2L when the polycrystalline silicon pattern is misaligned with respect to the opening of the silicon nitride film due to a mask alignment error in the present invention, and FIG. It is a sectional view showing a part of the manufacturing process of I2L. 101...n+ silicon layer, 102...
- N-type silicon epitaxial layer (semiconductor layer of first conductivity type), 107, 101,, 10?2...p-type base region (first semiconductor region of second conductivity type), 108.
...p+ type indie region (first semiconductor region of second conductivity type), 109... silicon nitride film (oxidation-resistant insulating film), 1101, 1102... opening Part, 111,, 1112, 1111', 1112', 11
1″...Arsenic-doped polycrystalline silicon pattern (
collector electrode), 1121, 1122, 112,', 1
122', 112''...Silicon oxide film, 11
31,1132,1131',1132'113...
...N+ type collector region (first conductivity type second semiconductor region), 1141, 1142... Electrode extraction opening, 115... P+ type external base region, 1
16,117,119...Al electrode.

Claims (1)

[Claims] 1. A step of selectively forming a first semiconductor region of a second conductivity type in a part of a semiconductor layer of a first conductivity type, and an opening at one or more locations facing the first semiconductor region. a step of forming an oxidation-resistant insulating film on the semiconductor layer, and a step of depositing a polycrystalline silicon layer and then patterning it to form a polycrystalline silicon pattern at least in the opening of the oxidation-resistant insulating film. a step of performing thermal oxidation treatment to grow a silicon oxide film around at least the polycrystalline silicon pattern; a step of forming a second semiconductor region of a first conductivity type in the first semiconductor region using the pattern as a diffusion source; and a step of removing the oxidation-resistant insulating film to form an opening for taking out an electrode in the first semiconductor region. , forming an electrode wiring covering an electrode wiring material layer, connected to the first semiconductor region through the opening, and insulated with a silicon oxide film provided around the polycrystalline silicon pattern; A method for manufacturing a semiconductor device, comprising the steps of: 2. When patterning the polycrystalline silicon layer, selective etching is performed using the two-layer pattern of silicon oxide film and silicon nitride film as a mask to form a polycrystalline silicon pattern in the opening of the oxidation-resistant insulating film, and then the silicon Claims characterized in that a thermal oxidation treatment is performed with a two-layer pattern of an oxide film and a silicon nitride film left on the polycrystalline silicon pattern to grow a silicon oxide film at least on the peripheral side of the polycrystalline silicon pattern. A method for manufacturing a semiconductor device according to scope 1. 3. Claim 1, wherein the semiconductor layer and the second semiconductor region are n-type, and the first semiconductor region is p-type.
A method for manufacturing a semiconductor device according to item 1 or 2. 4. Claim 1 or 2, characterized in that it includes a manufacturing process of a bipolar reverse operation transistor in which the semiconductor layer is used as an emitter region, the first semiconductor region is used as a base region, and the second semiconductor region is used as a collector region. A method for manufacturing the semiconductor device described.