JPS6262064B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

In general, a bipolar transistor suitable for high frequency use or high speed switching devices is designed to have a large gain bandwidth product f _T . Therefore, in order to increase f _T , it is necessary to reduce the element dimensions as much as possible and at the same time particularly shorten the base running time of the minority carrier. Currently, most silicon transistors are of planar type, and the emitter and base are formed by impurity diffusion. In this case, as the size of the emitter becomes smaller, the junction becomes a curved surface, and the effective base travel time depends not only on the base width but also on the depth of the collector-base junction. Therefore,
In order to improve f _T , it is required to reduce the base width and the collector-base junction depth at the same time, and the problem ultimately becomes how to realize a shallow diffusion junction.

By the way, a conventional bipolar type npn transistor has a structure shown in FIG. That is, the first
1 in the figure is a p ^- type silicon substrate, this substrate 1 has an n ⁺ type buried layer 2, and further on the same substrate 1 is an n
A type epitaxial layer 3 is provided. This epitaxial layer 3 is provided with a p ⁺ isolation region 4 for element isolation. In the island-shaped epitaxial layer 3 separated by the isolation region 4, there is a p-type base region 5, an n ⁺ type emitter region 6 is provided in the region 5, and another region of the epitaxial layer 3 is provided. A collector connection diffusion layer 7 reaching up to the n ⁺ buried layer 2 is formed at this location. Further, a thermal oxide film 8 is provided on the n-type epitaxial layer 3, and the thermal oxide film 8
On the top, an aluminum electrode 10 is connected to the emitter region ₆ , the base region 5, and the collector connection diffusion layer 7 through contact holes 91, ₉₂ , ₉₃ .
11 and 12 are provided. However, in a transistor with such a structure, the base region 5
If the depth is made shallower, the base resistance increases accordingly. In particular, the base region 5
If it becomes extremely shallow, the base resistance will depend on the distance between the end of the base contact hole ₉₂ and the emitter region 6. The positional relationship between the diffusion window of the emitter region 6 and the base contact hole ₉₂ is determined by photo-etching technology, and it is impossible to reduce this distance l to 2 μm or less using current optical alignment technology.

On the other hand, I ² L which is a bipolar logic element
(Integrated Injection Logic) as an example, a conventional I ² L has the structure shown in FIG. That is, 1 in FIG. 2 is a p ^- type silicon substrate,
An n ⁺ buried layer 2 is provided on this substrate 1 , and an n type epitaxial layer 3 separated by a p ⁺ type isolation region 4 is further provided on the substrate 1 . This epitaxial layer 3 has a p-type injector 1.
3. A p-type base region 14 is provided, and a plurality of n ⁺ -type collector regions 15 are provided within the base region 14. and n-type epitaxial layer 3
A thermal oxide film 8 is provided on the thermal oxide film 8, and the collector regions 15, the base region 14, the injector 13, and the n ⁺ buried layer 2 are formed on the thermal oxide film 8 through contact holes 9. Aluminum electrodes 16 ₁ , 16 ₂ , 17, 1 connected to the extension part 2'
8 and 19 are provided. Such an I ² L is a bipolar logic element with a composite structure of a so-called reverse-acting vertical npn transistor, which uses the emitter and collector of a normal transistor in reverse, and a horizontal pnp transistor, whose collector is the base of this transistor. It is. However, as mentioned above
For I ² L, vertical npn as an inverter
Since the transistor is inverted, the emitter-base junction area is much larger than the collector-base junction area, so the high-speed operation inherent to bipolar elements cannot be fully realized.

That is, since carrier injection into the base is performed from the entire emitter region, which has a wide area surrounding just below the collector region, the effective base width becomes large, and therefore the current amplification factor becomes small and f _T becomes low. This had the disadvantage of interfering with ^I2L performance, especially switching speed.

Therefore, to compensate for these shortcomings, IEDM
technical digest pp 201-204, (1979) “Sub-
Nanosecond Self-Aligned I ² L/MTL
By using a highly concentrated n ⁺ type doped polycrystalline silicon layer in the I ² L collector region, it is possible to form the base contact hole and the collector region using a self-alignment method due to the difference in the thickness of the silicon oxide film. The base region exposed on the surface is covered with metal, which lowers the base resistance and enables miniaturization of the device, making it possible to create a structure in which the emitter-base and collector-base junction area ratio approaches ¹ . The performance is superior to that of conventional I ² L with a minimum propagation delay time tpd min of approximately 0.8 nsec.
shows the best performance. But on the other hand,
This “Sub―Nanosecond Self―Aligned I ² L/
There are many problems with "MTL Circuits".The method for manufacturing this device will be explained below with reference to FIGS. 3a-f, 4 and 5.

First, an n type epitaxial growth layer 23 is formed on an n ⁺ type semiconductor substrate ₂₂₁ , and a high concentration n ⁺ type semiconductor layer ₂₂₂ is formed from the surface thereof to form an emitter region (as shown in FIG. 3a).

Next, as shown in FIG. 3b, the silicon nitride film 24
A desired silicon nitride film is partially opened and the underlying n-type epitaxial layer 23 is selectively etched. Then, as shown in FIG. 3c, a silicon oxide film 25 of about 1.0 to 1.5 μm is formed. Since this silicon oxide film 25 is provided so as to surround the periphery of the I ² L gate, it is also called an oxide film collar or an oxide film separation layer, and it separates the I ² L gates and prevents the injected material from being injected from the emitter to the base. It plays a role in increasing the effectiveness of minority carriers. Then, after removing all the silicon nitride film 24,
A silicon oxide film 26 with a thickness of 5000 Å was formed, and desired openings were opened in the silicon oxide film (as shown in Figure 3c).

Next, after forming the base region 27 and injector region 28, a layer of arsenic-doped polycrystalline silicon is deposited on the entire surface with a thickness of 3000 nm.
A CVD silicon oxide film (CVD-SiO ₂ ) 30 with a thickness of 3000 Å is further deposited thereon. This CVD-SiO ₂ 30 was then patterned using photo-etching technology, and the arsenic-doped polycrystalline silicon layer was further etched using a mixed solution of HF:HNO ₃ :CH ₃ COOH=1:3:8 using the CVD-SiO 2 30 as a mask _. (as shown in Figure 3d). At this time, a part of the arsenic-doped polycrystalline silicon layer 29 selectively left is I ² L
It exists on the base region 27 forming the collector region, and the other part exists on the insulating film, and is used as a collector electrode lead wiring.

Next, while forming the collector region 31 by diffusion from the arsenic-doped polycrystalline silicon film 29,
Silicon oxide films 32 ₁ and 32 ₂ were formed at a temperature of 900° C. to 900° C. There are several numbers on the base and injector area.
A silicon oxide film ₃₂₂ with a thickness of 100 Å is formed, and about 1000 to 2000 Å is formed on the surface of the arsenic-doped polycrystalline silicon layer 29.
A silicon oxide film ₃₂₁ having a thickness of 1.5 Å is formed. This means that the oxide film growth rate of the high concentration n ⁺ type semiconductor layer is
This is because by oxidizing at low temperatures (700°C to 900°C), the oxide film growth rate is several to ten times faster than that of a low-concentration p ^- type semiconductor layer. Continuing, in order to reduce the metal electrode film and contact resistance,
High-concentration p ⁺ type ion implantation is performed to form the injector region 28 and the external base 27' by diffusion again (as shown in FIG. 3e).

Next, the silicon oxide film ₃₂₂ with a thickness of several hundred Å on the injector region 28 and the external base region 27' is etched using a self-alignment method, all contact holes are opened using a photo-etching method, and a metal electrode film is covered. After the attachment, the electrodes are separated to form a base lead-out electrode 33, an injector lead-out electrode 34, and an emitter grounding electrode 35.
I ² L was produced (as shown in Figure 3 f). In addition, Fig. 3 f
FIG. 4 shows a plan view of the same, and FIG. 5 shows a cross-sectional view taken along the line --- in FIG.

In I ² L manufactured by the manufacturing process described above,
Since the electrodes of the device include the base, injector, and emitter using metal electrode films, and the collector electrode using arsenic-doped polycrystalline silicon, the device has various features as described above. However, these manufacturing methods have various problems listed below.

In the step d in Fig. 3 described above, CVD-SiO ₂
When etching the arsenic-doped polycrystalline silicon layer (3000 Å thick) using the film 30 as a mask, side etching is performed by the thickness of the polycrystalline silicon film.
The CVD-SiO ₂ film 30 has an overhang shape. When the arsenic-doped polycrystalline silicon film 29 is oxidized in such a state, a silicon oxide film ₃₂₁ grows in an abnormal shape on the circumferential side of the arsenic-doped polycrystalline silicon film 29, as shown in FIG. 6a, and is present on it.
Push up the CVD-SiO ₂ film 30. As a result, there is a drawback that the base lead-out electrode crossing the arsenic-doped polycrystalline silicon film 29 is broken. Moreover, since this arsenic-doped polycrystalline silicon film 29 is used as a single-layer wiring for connecting elements,
This induces a break in the two-layer wiring that crosses over this.

In addition, in the step e in FIG. 3 described above, the base contact hole and the collector region 31 are formed using the self-alignment method by utilizing the difference in the growth rate of the silicon oxide film due to low-temperature oxidation. Shorts due to metal electrodes often occur between the collectors. The cause of this is that the silicon oxide film 32 ₁ grown thereon by low-temperature oxidation of the arsenic-doped polycrystalline silicon layer 29 is more sensitive to the silicon oxide film 32 ₂ formed on the base region 27 as the temperature is lower. Formed several times thicker. However, on the other hand, the density of the film is inferior, and the insulation properties are several times worse.In particular, the insulation properties after the silicon oxide film formed by oxidizing the arsenic-doped polycrystalline silicon layer 29 at 700°C are treated with an HF-based etchant. It is very bad, and compared to a silicon oxide film formed by oxidizing a single crystal silicon layer at high temperature (1000℃ or higher) of 80 to 90 V with a thickness of 1000 Å, a dielectric breakdown voltage of 10 to 20 V with a thickness of 2000 Å is very poor. Alternatively, the dielectric strength voltage may be zero. Furthermore, when observing the state after thermal oxidation, it is found that the silicon oxide films ₃₂₁ grown on both sides of the arsenic-doped polycrystalline silicon layer 29 existing on the base region 27, which is a p-type single-crystal silicon layer, are p-type single-crystal silicon. layer (base area 2
7), a small amount of the silicon oxide film grows in the contact area with the silicon oxide film, forming a concave shape. Therefore, when the silicon oxide film ₃₂₂ on the side surface of the n ⁺ polycrystalline silicon is removed with an HF-based etchant, the silicon oxide film ₃₂₁ on the arsenic-doped polycrystalline silicon layer 29 has poor density and is susceptible to etchants, as described above. Since the contact portion with the base region 27 is thinner than other portions, as shown in FIG. The formed n ⁺ type collector region 31 is exposed, and as a result, when the base extraction electrode 33 is formed, the electrode 33 and the collector region 31 are short-circuited.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device with high performance and high integration.

That is, the method of the present invention includes a step of selectively forming a first semiconductor region of a second conductivity type in a part of a semiconductor layer of a first conductivity type, and a step of forming a first semiconductor region of a second conductivity type on a portion of a semiconductor layer of a first conductivity type; selectively forming an oxidation-resistant insulating film, forming a semiconductor film on the entire surface, and forming a single crystal silicon layer of a second conductivity type on the insulating film in a portion directly in contact with the first semiconductor region; A step of forming a polycrystalline silicon layer of a second conductivity type in the contacting portion, and masking a part of the single crystal silicon layer from a desired portion of the polycrystalline silicon layer, and selectively etching the polycrystalline silicon layer. A step of forming a protrusion made of single crystal silicon of a second conductivity type on one semiconductor region and forming a desired polycrystalline silicon pattern integrally connected to the protrusion, and performing thermal oxidation treatment to A step of growing a thermal oxide film as an insulating film on the entire surface of the protrusion made of single crystal silicon of a second conductivity type, and selectively removing an oxidation-resistant insulating film provided on the first semiconductor region. a step of exposing a portion of the first semiconductor region adjacent to the protrusion; and a step of selectively doping the first semiconductor region with an impurity of the first conductivity type using the protrusion covered with the thermal oxide film as a mask to prevent the protrusion from being exposed. The method is characterized by comprising a step of forming a second semiconductor region of the first conductivity type that is self-aligned.

In the method of the present invention, the method for forming the first semiconductor region of the second conductivity type includes a method of selectively thermally diffusing impurities of the second conductivity type into the semiconductor layer of the first conductivity type;
Examples include a method of ion-implanting the impurity and subjecting it to heat treatment.

When forming the semiconductor film, the oxidation-resistant insulating film used in the method of the present invention has an etching rate that is higher than that of the single-crystal silicon layer grown in the second conductivity type first semiconductor region other than the planned portion where the protrusion is to be formed. forming a polycrystalline silicon layer having different physical properties such as, and preventing the oxidizing agent from entering the first semiconductor region under the insulating film during thermal oxidation to prevent a thermal oxide film from growing in that region. play a role. Furthermore, when providing a formation window for the second semiconductor region of the first conductivity type in the first semiconductor region after thermal oxidation, it has selective etching properties for the thermal oxide film, and the thermal oxide film around the protrusion is etched. It has the advantage of being able to remove the oxidation-resistant insulating film without causing film thinning. Examples of such an oxidation-resistant insulating film include a silicon nitride film and an alumina film. However, if a silicon nitride film is used as an oxidation-resistant insulating film and is provided directly on the first semiconductor region, substances such as nitrides that adversely affect device characteristics are generated in the first semiconductor region during the thermal oxidation process. Therefore, the thermal oxide film grown on the first semiconductor region in the thermal oxidation process should be sufficiently thinner (50~
It is desirable to selectively form a silicon nitride film through a SiO ₂ film (100 Å).

As a method for forming a semiconductor film in the present invention, for example, after depositing a polycrystalline silicon layer by a liquid phase growth method, a solid phase growth method, or a vapor phase growth method such as a CVD method or a PVD method, Examples include a method of selectively epitaxially growing a single crystal silicon layer by irradiating a high-energy beam. When forming such a semiconductor film,
The epitaxial growth method is adopted because a single crystal silicon layer of the second conductivity type is formed on the first semiconductor region.
This is to form a second conductivity type polycrystalline silicon layer having selective etching properties with respect to the single crystal silicon on the insulating film of the first semiconductor region. In addition,
To form a single crystal silicon layer or a polycrystalline silicon layer of the second conductivity type, for example, a method of doping impurities during vapor phase epitaxial growth, or a method of doping an impurity during vapor phase epitaxial growth, or a method of growing an undoped polycrystalline silicon layer and single crystal silicon, and then forming a second conductivity type single crystal silicon layer and a polycrystalline silicon layer A method of diffusing or ion-implanting a conductive type impurity may be adopted.

Next, an example in which the present invention is applied to a bipolar type npn transistor will be described along with a manufacturing method.

Example 1 [] First, as shown in FIG. 7a, an n ⁺ buried layer 102 is formed on a p ^- type semiconductor substrate 101, and an n type epitaxial layer 103 is formed on this substrate 101.
After growing the (first conductivity type semiconductor layer), a p ⁺ -type isolation region 104 reaching the substrate 101 was formed by selectively diffusing boron at a high concentration. Next, the n-type epitaxial layer 1
03, a high concentration n ⁺ type impurity was selectively diffused to form an n ⁺ type collector extraction diffusion layer 105 that reached the n ⁺ buried layer 102. After that, a silicon oxide film 106 with a thickness of 4000 Å is deposited on the entire surface, and the silicon oxide film 106 in the area where the base is to be formed is
selectively removed by photolithography to form diffusion window 1.
After opening holes 07, boron ions were implanted into the n-type epitaxial layer 103, and heat treatment was performed to form a p-type region 108 (as shown in FIG. 7B).

[] Next, after depositing a silicon nitride film with a thickness of 1000 Å as an oxidation-resistant insulating film on the entire surface, the silicon nitride film in the areas where the protrusions of the silicon oxide film 106 and the p-type region 108 are to be formed is selected by photolithography. Then, silicon nitride film patterns 109, 109 were formed (as shown in FIG. 7c).
Subsequently, a semiconductor film was formed on the entire surface by vapor phase epitaxial growth. At this time, as shown in FIG. 7d, a single-crystal silicon layer 110 with a thickness of 5000 Å is formed on the portion directly in contact with the p-type region 108, and the same thickness is formed on the silicon oxide film 106 and the silicon nitride film patterns 109, 109. A third polycrystalline silicon layer 111 was formed. Thereafter, a U-shaped resist pattern 112 was formed in a desired portion of the polycrystalline silicon layer 111 by photolithography (as shown in FIGS. 7(d) and 8). Continued HF:
HNO ₃ :CH ₃ COOH=1:3:8 or HF:
Etching was performed using an etchant with a mixing ratio of HNO ₃ :CH ₃ COOH:H ₂ O=1:20:20:40.
At this time, since the polycrystalline silicon layer 111 has selective etching properties with respect to the single-crystalline silicon layer 110, only the polycrystalline silicon layer 111 other than that covered with the resist pattern 112 is removed.
After removing the resist pattern 112, protrusions 113 of single crystal silicon that are self-aligned with the silicon nitride film patterns 109 and 109 are formed as shown in FIGS. A polycrystalline silicon pattern 114 was formed in integral contact with the polycrystalline silicon pattern 114.

[] Next, boron was thermally diffused over the entire surface. At this time, as shown in FIG. 7f, highly concentrated boron is diffused into the protrusion 113 made of single crystal silicon to form a p ⁺ type base region 115, and a polycrystalline silicon pattern integrally connected to the p + type base region 115. Boron is also diffused into the base electrode 114 to reduce its resistance and become the base electrode 116. Continuing, 950
Thermal oxidation treatment was performed at ~1100℃. At this time, as shown in FIG. 7f, the protrusion 1 made of single crystal silicon
13, and a base electrode 116 made of boron-doped polycrystalline silicon with a thickness of 3000 Å and a thickness of 4000 Å.
Thermal oxide films 117 and 118 of Å are grown, respectively.
In particular, since the thermal oxide film 117 around the protrusion 113 is an oxide film of single crystal silicon, it has extremely high density. Note that p-type region 1
08 is re-diffused by heat treatment to become a p-type base region 108' (first semiconductor region of second conductivity type), and a silicon nitride film pattern 109,
The pattern 109, 109 prevents the growth of a thermal oxide film on the p-type base region 108' portion covered with the pattern 109 due to the effect of preventing the oxidizing agent from entering.

[] Next, silicon nitride film pattern 10
After removing 9,109 with hot phosphoric acid or a Freon-based dry etchant to form an emitter diffusion window, arsenic or phosphorus ions were implanted and heat treatment was performed. At this time, as shown in FIG. 7g, a plurality of n ⁺ type emitter regions 119 are formed in the p type base region 108'.
_{1,119 2} (second semiconductor region of first conductivity type)
were formed in self-alignment with respect to the protrusions 113, 113, 113. Subsequently, contact holes 120 and 120' were formed in the silicon oxide film 106 on the collector extraction diffusion layer 105 and the thermal oxide film 118 on the base electrode 116 made of boron-doped polycrystalline silicon, respectively, and then a 1 μm thick aluminum film was formed on the entire surface. A bipolar npn transistor was manufactured by depositing a film and separating the electrodes by photolithography to form emitter lead-out Al electrodes 121 ₁ , 121 ₂ , collector lead-out Al electrode 122 , and base lead-out Al electrode 123 (No. 7). (Illustrated in Figures g, 10, and 11). In addition,
Fig. 10 is a plan view of Fig. 7 g, Fig. 11 is a plan view of Fig. 1
FIG. 2 is a sectional view taken along the line XI-XI in FIG.

Bipolar type of the present invention obtained in Example 1 described above
The npn transistor is shown in Figure 7g, Figure 10 and Figure 1.
As shown in Figure 1, a protrusion 1 made of single crystal silicon
Thermal oxide film 117 with an emitter contact hole of 3000 Å for the p ⁺ type base region 115 of 13...
Because it is self-aligned through the emitter region, it is not limited to miniaturization due to alignment error as in the conventional bipolar transistor shown in Fig. 119
By locating the base region 115 of low-resistance p ⁺ type single-crystal silicon close to ₁ , 119, ₂ , the base resistance can be reduced and the gain and switching speed can be significantly improved. Furthermore, since the protruding portions 113 made of single crystal silicon having the p ⁺ type base regions 115 are integrally connected to the base electrodes 116 made of polycrystalline silicon doped with high concentration boron, the p ⁺ type base regions 115 have a high concentration. 115... without increasing the resistance of the base electrode 1.
16 and a contact hole 120', it can be connected to the lead-out Al electrode 123. Furthermore, since the protrusion 113 having the p ⁺ type base region 115 is covered with a highly dense insulating film, which is the thermal oxide film 117 of single crystal silicon constituting the protrusion 113, The dielectric strength between the p ⁺ -type base regions 115 and the emitter extraction electrodes 121 ₁ and 121 ₂ can be significantly improved. Furthermore, the protruding portion 113...
The side part of the thermal oxide film 117 (insulating film) is the p-type base region 1 formed in the n-type epitaxial layer 103.
Since it is located so as to cover the exposed area of the junction between 08' and the n ⁺ emitter region 119..., the emitter extraction Al electrode 121 ₁ , 12 between the emitter and the base
1 ₂ short circuit can be prevented.

Furthermore, according to the method described above, since polycrystalline silicon is epitaxially grown with the silicon nitride film patterns 109, 109 formed on the p-type base region 108' of the n-type epitaxial layer 103, the p-type base region 108' A single-crystal silicon layer 110 is placed in the portion that is in direct contact with the silicon nitride film patterns 109,
6, a polycrystalline silicon layer 1 having sufficient selective etching properties with respect to the single crystal silicon layer 110 is provided.
11 can be formed. As a result, by etching with a selective etchant for polycrystalline silicon, single-crystal silicon protrusions 113 can be formed that are self-aligned with the silicon nitride film patterns 109, 109 that will become emitter contact holes. Furthermore, during this etching, as shown in FIG. 8, by covering a desired portion of the polycrystalline silicon layer 111 and a part of the single-crystal silicon layer 110 with a resist pattern 112, the protruding portion 113 of the single-crystal silicon is etched. A polycrystalline silicon pattern 114 serving as a base electrode connected with low resistance can be formed. In addition, a silicon nitride film pattern 10 having excellent oxidation resistance is formed on the p-type base region 108' portion adjacent to the protruding portion 113 made of single crystal silicon.
Thermal oxidation treatment is performed while covered with 9,109 (7th
(FIG. f), the silicon nitride film pattern 10
It is possible to prevent the growth of a thermal oxide film on the p-type base region 108' portion under 9,109, and to form a silicon nitride film pattern on the entire surface of the protruding portion 113 made of single crystal silicon without considering the growth of the thermal oxide film on that portion. thick enough to have selective etching properties (e.g. 3000
A thermal oxide film 117 of .ANG.) can be grown. the result,
In order to provide a hole that serves both as an emitter diffusion window and an emitter contact, a silicon nitride film pattern 10
9,109, the thermal oxide film 1 around the protrusions 113 made of single crystal silicon is removed by etching.
This can be done without causing the film loss of 17. However, by diffusing an n-type impurity such as arsenic into the p-type base region 108' through the diffusion window, n ⁺ -type emitter regions 119, 119 are formed in self-alignment with respect to the protrusions 113. The exposed areas of these base-emitter junctions can be covered with the side surfaces of the thermal oxide film 117.
Therefore, the emitter extraction electrodes 121 ₁ , 12
1 ₂ , it is possible to prevent short circuits of the base emitters due to the electrodes 121 ₁ and 121 ₂ and to sufficiently improve the dielectric strength voltage of the base emitters.

Example 2 [] First, as shown in FIG. 12a, an n ⁺ buried layer 102 is formed on a p ^- type semiconductor substrate 101, and an n type epitaxial layer 103 is formed on this substrate 101.
After growing the (first conductivity type semiconductor layer), a p ⁺ -type isolation region 104 reaching the substrate 101 was formed by selectively diffusing boron at a high concentration. Next, the n-type epitaxial layer 1
03 by selectively diffusing high concentrations of phosphorus and arsenic to
After forming the n ⁺ type collector extraction diffusion layer 105 that reaches the n ⁺ buried layer 102, thermal oxidation treatment is performed to grow a silicon oxide film 106 with a thickness of 4000 Å, and the silicon oxide film 106 in the area where the base is to be formed is grown.
6 was selectively removed by photolithography to form an opening 107 (as shown in FIG. 12b).

[] Next, after depositing a silicon nitride film with a thickness of 1000 Å as an oxidation-resistant insulating film on the entire surface, the portion where the protrusion of the n-type epitaxial layer 103 is to be formed is exposed on the silicon oxide film 106 and through the opening 107. The silicon nitride film is selectively removed by photolithography to form a silicon nitride film pattern 10.
9,109 was formed. Next, after depositing polycrystalline silicon with a thickness of 5000 Å on the entire surface by vapor phase growth,
Nd-YAG laser light with an energy density of 2 J/cm ² was irradiated. At this time, the polycrystalline silicon layer grows epitaxially, and as shown in FIG.
6 and silicon nitride film patterns 109, 109
A polycrystalline silicon layer 111 was formed thereon.

[] Next, the monocrystalline silicon layer 11 is removed from a desired portion of the polycrystalline silicon layer 111 by photolithography.
After forming a U-shaped resist pattern (not shown) spanning part of 0 in the same manner as in FIG. 8 of Example 1, HF:HNO ₃ :CH ₃ COOH:H ₂ =
A silicon nitride film pattern 10 is etched using an etchant with a mixing ratio of 1:20:20:40.
Protrusions 113 of single crystal silicon that are self-aligned with respect to the protrusions 9 and 109 were formed, and a polycrystalline silicon pattern (not shown) integrally connected to the protrusions 113 was formed. Subsequently, the entire surface is doped with boron to form a p ⁺ type base region 115 doped with boron at a high concentration in the protrusion 113, and a polycrystalline silicon pattern (not shown) is also doped with boron to form a low-resistance base electrode. did. then 950
A thermal oxide film 117 (the thermal oxide film of the base electrode is not shown) with a thickness of 3000 Å and 4000 Å was grown around the protrusion 113 and the base electrode by thermal oxidation treatment at ~1100°C (Fig. 12). (e diagram).

[] Next, silicon nitride film pattern 10
After removing 9,109 with hot phosphoric acid or a Freon-based dry etchant to form a diffusion window that serves both as a base and an emitter, low concentration boron is sufficiently thermally diffused through the diffusion window to form a silicon single crystal. The p ⁺ type base region 1 of the protrusion 113 consisting of
p-type base region 108' ₁ in contact with 15...
_108'2 was formed. Subsequently, an arsenic-doped polycrystalline silicon layer 124 is formed through the diffusion window.
are formed and heat treated to form each p-type base region 10.
n ⁺ type emitter region 1 in 8' ₁ , 108' ₂
19 ₁ and 119 ₂ were formed in self-alignment with respect to the protrusions 113 . Thereafter, contact holes 1 are formed in the silicon oxide film on the collector extraction diffusion layer 105 and the thermal oxide film on the base electrode, respectively.
After opening 20 (contact holes in the thermal oxide film are not shown), an Al film with a thickness of 1 μm is deposited on the entire surface, and the electrodes are separated by photolithography to take out the emitters of the Al electrodes 121 ₁ , 121
_2. A collector lead-out Al electrode 122 and a base lead-out Al electrode (not shown) were formed to manufacture a multi-emitter bipolar type npn transistor (shown in FIG. 12f).

Since the bipolar type npn transistor of the present invention described above has a smaller base area than that of the first embodiment, f _T can be improved. Furthermore, when used in reverse operation, the upward current amplification factor can be significantly improved.

Note that the present invention is not limited to bipolar type npn transistors having multi-emitters as in the above embodiments, but also applies to I ² L, field effect transistors (including static induction transistors; SIT), and static induction transistors (SITL). It is also applicable to the following.

As detailed above, according to the present invention, semiconductor devices such as bipolar transistors, which have excellent performance such as high current amplification and high switching speed, and high reliability and high integration can be manufactured simply and with high yield. It is possible to provide a method for manufacturing the same.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional bipolar npn transistor, FIG. 2 is a sectional view of a conventional I ² L, and FIGS. 3 a to 3 f are sectional views showing the manufacturing process of a conventional improved I ² L. 4 is a plan view of FIG. 3f, FIG. 5 is a sectional view taken along the line - in FIG. 4, FIG. 6a is a sectional view showing the state of the thermal oxidation process in FIG. 3e, and FIG. 7b is a cross-sectional view showing the state after etching in the above process, FIGS. 9 is a plan view of FIG. 7 e, FIG. 10 is a plan view of FIG. 7 g, FIG. 11 is a sectional view taken along line XI-XI of FIG. 10, and FIGS. f is a cross-sectional view showing the manufacturing process of a multi-emitter bipolar type npn transistor in Example 2 of the present invention. 101...p ^- type semiconductor substrate, 102...n ⁺ buried layer, 103...n type epitaxial layer (semiconductor layer of first conductivity type), 104...p ⁺ isolation region, 108', 108' ₁ , 108 ' ₂ ...p-type base region (first semiconductor region of second conductivity type), 10
9,109...Silicon nitride film pattern, 113...
Protruding portion made of single crystal silicon, 115...p ⁺ type base region, 116... base electrode made of boron-doped polycrystalline silicon, 117... thermal oxide film (insulating film), 119 ₁ , 119 ₂ ... n ⁺ type emitter region,
121 ₁ , 121 ₂ ...Emitter extraction Al electrode,
122... Al electrode taken out from the collector, 123... Al electrode taken out from the base.

Claims (1)

[Claims] 1. A step of selectively forming a first semiconductor region of a second conductivity type in a part of a semiconductor layer of a first conductivity type; selectively forming at least an oxidation-resistant insulating film, forming a semiconductor film on the entire surface, and forming a single crystal silicon layer of a second conductivity type on the insulating film in a portion directly in contact with the first semiconductor region; forming a polycrystalline silicon layer of a second conductivity type in a portion in contact with the polycrystalline silicon layer; and after masking a part of the single crystal silicon layer from a desired portion of the polycrystalline silicon layer, selectively etching the polycrystalline silicon layer; forming a protrusion made of single crystal silicon of a second conductivity type on the first semiconductor region, forming a desired polycrystalline silicon pattern integrally connected to the protrusion, and performing thermal oxidation treatment. A step of growing a thermal oxide film as an insulating film on the entire surface of the protrusion made of single crystal silicon of the second conductivity type, and selectively removing an oxidation-resistant insulating film provided on the first semiconductor region. exposing a portion of the first semiconductor region adjacent to the protrusion; and selectively doping the first semiconductor region with an impurity of a first conductivity type using the protrusion covered with a thermal oxide film as a mask to form the protrusion. The first self-consistent
1. A method of manufacturing a semiconductor device, comprising the step of forming a second semiconductor region of a conductive type. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor film is formed by vapor phase epitaxial growth. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor film is formed by depositing a polycrystalline silicon layer over the entire surface and then irradiating it with an energy beam.