JPS594031A - Manufacturing device of semiconductor - Google Patents
Manufacturing device of semiconductorInfo
- Publication number
- JPS594031A JPS594031A JP57112960A JP11296082A JPS594031A JP S594031 A JPS594031 A JP S594031A JP 57112960 A JP57112960 A JP 57112960A JP 11296082 A JP11296082 A JP 11296082A JP S594031 A JPS594031 A JP S594031A
- Authority
- JP
- Japan
- Prior art keywords
- furnace
- decompression
- semiconductor
- oxide film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体集積回路等の製造工程の一部である焼
な甘し処理を行なうもので、半導体基板内に行なった配
線を安定化する手段を改善した半導体製造装置に関する
。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to annealing treatment that is part of the manufacturing process of semiconductor integrated circuits, etc., and is a means for stabilizing wiring formed within a semiconductor substrate. The present invention relates to a semiconductor manufacturing device that has been improved.
半導体装置は、普通半導体基板上に形成した絶縁物の酸
化膜をマスクにして、P型あるいはN型の不純物を添加
するプレナシ技術が基本になってつくられる。この半導
体装置がダイオードまたはトランジスタ等の能動素子の
ように単7り: TJ気回路累子を構成している場合、
配線は基板内の各半導体素子の電極からリード線を引き
出すだけでよく、またこのような構成の装置の用途も多
い。しかし他方、扱う電力が比較的小さく、能動素子の
他に抵抗、コンデンサ等の受動素子を含め、主らこれら
の被合的な組み合せによる機能の増大、小型化、故障率
の低減等を促進するために、半導体のQ−、積回路(I
OlL S I 、 V T、 S I等)化が計られ
ている。このよう慶集積回路を構成するには半導体基P
V内に多層構造の軍、気回路素子を形成し、それぞれを
有機的に結合する配線が必要になる。そして、集積の高
度化に伴い、アルミニウム等の配線金属も細くしなくて
はならない。し2かし、この場合の配線に十分な密着性
が得られないと、製造した半導体集積回路の電気特性に
ばらつきを生じてしまう。したがって、これらに対し期
待する動作を望むことはでき々くなる。ゆえに配線金属
をしっかりと基板に密ねするために焼々まし処理を行な
うものである。Semiconductor devices are generally manufactured based on a plenary technique in which P-type or N-type impurities are added using an insulating oxide film formed on a semiconductor substrate as a mask. If this semiconductor device constitutes a TJ circuit, such as an active element such as a diode or a transistor,
For wiring, it is sufficient to simply draw out lead wires from the electrodes of each semiconductor element within the substrate, and there are many uses for a device having such a configuration. However, on the other hand, the power handled is relatively small, and in addition to active elements, passive elements such as resistors and capacitors are included, and the combination of these elements is mainly used to increase functionality, miniaturize, and reduce failure rates. Therefore, the semiconductor Q-, product circuit (I
OLSI, VT, SI, etc.) are being planned. To construct such a Kei integrated circuit, a semiconductor substrate P is required.
It is necessary to form a multilayer structure of circuit elements in the V, and to provide wiring to organically connect them. As integration becomes more sophisticated, wiring metals such as aluminum must also be made thinner. However, in this case, if sufficient adhesion is not achieved in the wiring, variations will occur in the electrical characteristics of the manufactured semiconductor integrated circuits. Therefore, it becomes impossible to expect the expected behavior from these. Therefore, a baking process is performed to firmly adhere the wiring metal to the board.
以下この焼な甘し処理までの過程をシリコン半導体基板
を用いた例により説明する。The process up to this annealing treatment will be explained below using an example using a silicon semiconductor substrate.
まず、半導体基板の表面を酸化して酸化膜(S+C)、
)を形成する。ついで、この酸化膜(8+O,)をマス
クに利用して選択的にP型あるいはN型の不純物全基板
内に拡散させ、多層構造の能ル、11素子および受動素
子を形成する。First, the surface of the semiconductor substrate is oxidized to form an oxide film (S+C).
) to form. Next, using this oxide film (8+O,) as a mask, P-type or N-type impurities are selectively diffused into the entire substrate to form a multilayer structure of active elements, 11 elements, and passive elements.
上記酸化ll5(S i O,:)や、不純物の拡散源
として形成するリン・ケイ酸ガラス(L’8G)膜゛ま
たはホウ素・ケイ酸ガラス(BSG)膜等のOV I)
肱は絶縁物々ので各素子の電気特性の保護膜の役目を
させて次の配線に利用することができる。配線は、これ
ら酸化膜またはOVD膜に配線金属を蒸着またはスパッ
タリングにより被着させて各素子を接続する。上記配線
金属にはアルミニウム(AJ)、アルミニウム・シリコ
ン混合物(A l −S i ) 、アルミニウム・シ
リコン・銅混合物(A l−8i −Ou )等を用い
、上記のようにして半導体集積回路を形成する。The above-mentioned oxide ll5 (S i O,:) or OV I) such as a phosphorus silicate glass (L'8G) film or a boron silicate glass (BSG) film formed as a diffusion source of impurities.
Since the collar is an insulating material, it can serve as a protective film for the electrical characteristics of each element and can be used for the next wiring. The wiring connects each element by depositing wiring metal on these oxide films or OVD films by vapor deposition or sputtering. A semiconductor integrated circuit is formed as described above using aluminum (AJ), an aluminum-silicon mixture (A l-S i ), an aluminum-silicon-copper mixture (A l-8i-Ou ), etc. as the wiring metal. do.
しかし、これだけでは回路の信頼性が十分でないので配
線金属と、酸化膜寸たはCV I) %の打合面を蜜漬
させ安定するように、焼々ましをして合金層を形成させ
るようにする。However, this alone is not sufficient to ensure the reliability of the circuit, so it is recommended to immerse the wiring metal and the contact surface of the oxide film (CV Make it.
従来、この焼な咬し処理はn圧型処理炉内を窒素(N、
)または水素(FIt)の雰囲気で満し、400〜50
0℃、程度の温敦、すなわち配線金属の融点より低い温
度で数分〜数十分焼な捷しをしていた。Conventionally, this annealing process uses nitrogen (N,
) or hydrogen (FIt) atmosphere, 400-50
Annealing was carried out at a temperature of about 0° C., that is, at a temperature lower than the melting point of the wiring metal for several minutes to several tens of minutes.
しかし、上記のように常用で焼11しを行なうと、配線
金属の内部、まだは下地の酸化膜もしくはOVD膜に付
着した水分(H2O)を完全に離脱させることが難しい
。すなわち、配線金属にアルミニウム(AIりを用い、
水分(1−120)が離脱しないまま半淘体f!+、積
回路が製造された場合、これを笑際に通電して動作させ
ると次のようh電気化学反応が促進され、アルミニウム
(AJ)の粒界に水酸化腐蝕(電食)を生じて断線に至
る。However, when baking is carried out regularly as described above, it is difficult to completely remove the moisture (H2O) that has adhered to the inside of the wiring metal and to the underlying oxide film or OVD film. In other words, using aluminum (AI) as the wiring metal,
A semi-depleted body without water (1-120) being released! +、When a product circuit is manufactured, when it is operated by energizing it, the following electrochemical reaction is promoted, causing hydroxide corrosion (electrolytic corrosion) at the grain boundaries of aluminum (AJ). This will lead to a disconnection.
2H’+2 e−−+H2、Aj””+3 (OH)−
+AJ (OH)3オた、伎−護1便とするリン・ケイ
酸ガラス(PSG)lI!It中のリン濃度が高い場合
には泡1解4′「用によってアルミニウム(Ar)中の
水分(H2O) を吸収し、解けだした五酸化リン(
P2O5)から1)ン酸(2H1lPO4) の形成
力−あり、反応を促進するという欠点があった。2H'+2 e--+H2, Aj""+3 (OH)-
+AJ (OH) 3 Ota, KI - Mamoru 1 flight phosphorus silicate glass (PSG) lI! When the concentration of phosphorus in It is high, the phosphorus pentoxide (phosphorus
P2O5) to 1) phosphoric acid (2H11PO4), which has the disadvantage of accelerating the reaction.
この発明は」二記のような間融点を解決するためになさ
れたもので、配線金属と、酸化膜捷たはOV D B’
fiとを密着させる焼な捷し処理「pに、この密着性以
外の電気特性劣化要因も削減する半導体製造装置を提供
することを目的とする。This invention was made in order to solve the problem of melting point between the metal wiring and the oxide film or OV D B'.
It is an object of the present invention to provide a semiconductor manufacturing apparatus that reduces electrical property deterioration factors other than this adhesion during an annealing process that brings fi and p into close contact.
すなわちこの発明に係る半導体製造装置は焼なまし処理
を減圧状紗にした減圧型処理炉内で行方い、製造された
半導体装置の動作時に粒界の水酸化腐蝕を生起させる水
分が配線金属、または酸化膜もしくはQ V D膜に付
着している場合、これを離脱するようにしだものである
。That is, in the semiconductor manufacturing apparatus according to the present invention, the annealing process is carried out in a reduced-pressure type processing furnace in which a reduced-pressure type gauze is used, and when the manufactured semiconductor device is operated, moisture that causes hydroxide corrosion at the grain boundaries is removed from the wiring metal, Or, if it is attached to an oxide film or a QVD film, it is made to separate from it.
以下図面を参照してこの発明の一実施例を説明する。第
1図はその構成を示したもので、焼なましを行なう減圧
型処理炉11はジヨイント12を介して減圧手段例えば
真空ポンプ13に連通している。この処理炉11には減
圧モニタ14を設け、真空ポンプ13による減圧状態が
一定にガるように調整させる。この減圧型修1処理炉1
1の内部には、多数の半導体基板15a、15b・・・
を並べた治具16を設定し、この処理炉11の外側には
炉11内を加熱する加熱手段例えばレジスタンスヒータ
17を設置する。処理炉11内の上部および下部にはそ
れぞれノズル列18g、18hを設け、このノズル列1
8s、18bには移送管19を通り適宜マニホルド20
で分割された雰囲気となる気体をこのそれぞれから噴出
させるようにする。すなわち、この移送管19には、気
体の種類に対応した数の開閉弁21とfM量計22を設
け、窒素(Nり、水素(l(、)等の雰囲気ガスを供給
する。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows its construction, in which a reduced-pressure processing furnace 11 for annealing is communicated via a joint 12 with a reduced-pressure means, such as a vacuum pump 13. This processing furnace 11 is provided with a pressure reduction monitor 14 to adjust the pressure reduction state by the vacuum pump 13 to be constant. This reduced pressure treatment furnace 1
1 includes a large number of semiconductor substrates 15a, 15b...
A jig 16 is set up in which the processing furnace 11 is lined up, and a heating means, such as a resistance heater 17, for heating the inside of the processing furnace 11 is installed outside the processing furnace 11. Nozzle rows 18g and 18h are provided in the upper and lower parts of the processing furnace 11, respectively.
8s and 18b pass through a transfer pipe 19 and are properly connected to a manifold 20.
The gas forming the divided atmosphere is ejected from each of these parts. That is, this transfer pipe 19 is provided with a number of on-off valves 21 corresponding to the type of gas and an fM quantity meter 22 to supply an atmospheric gas such as nitrogen (N) or hydrogen (1).
このよう々装置によって焼なオし処理をする場合、廿ず
半導体基板15a、15b・・・を治具16の上に並べ
て処理炉11内に設定する。そして、真空ポンプを作動
させて処理炉11内を01〜ITorri度に減圧する
。この圧力状態を維持したませレジスタンスヒータによ
シ処理炉1ノを400〜500℃、に加熱し、この炉1
1内に水素(H,)2Jまたは窒素(Nt )24の気
体を送り込んで半導体基板15a。When annealing is performed using such an apparatus, the semiconductor substrates 15a, 15b, . . . are arranged on a jig 16 and set in the processing furnace 11. Then, the vacuum pump is operated to reduce the pressure inside the processing furnace 11 to 01 to ITorri degrees. While maintaining this pressure state, heat the processing furnace 1 to 400 to 500°C using a resistance heater.
A gas of hydrogen (H, ) 2J or nitrogen (Nt) 24 is introduced into the semiconductor substrate 15a.
15h・・・を焼atしする。Burn for 15 hours...
すなわち、上記のような減圧状態にすれば、圧力的に炉
・11内の水分(H,0)が蒸発しやすくなり、配線の
接合部分を合金属によシ密着するだけでなく、水酸化腐
蝕(電食)も防止することができる。In other words, if the pressure is reduced as described above, the moisture (H, 0) in the furnace 11 will easily evaporate due to the pressure, and not only will the joints of the wiring be tightly bonded to the alloy metal, but also the hydroxide Corrosion (electrolytic corrosion) can also be prevented.
このようにして行なう焼な甘し処理はIO。The roasted sweet process performed in this way is IO.
LSI等どのような半導体基板にも適用することができ
、配線の接合部材料がアルミニウム(AIり、アルミニ
ウム・シリコン混合物(AI!−8i) 、アルミニ
ウム・シリコン銅混合物(kl−8i −Ou )等と
、酸化膜(8i0t)寸たはOVD膜(PSG)等であ
れば有効である。It can be applied to any semiconductor substrate such as LSI, and the wiring junction material is aluminum (AI), aluminum-silicon mixture (AI!-8i), aluminum-silicon copper mixture (kl-8i-Ou), etc. An oxide film (8i0t) or an OVD film (PSG) is effective.
そして、実際にバづポーラ型IOで比較したところ、確
かにアルミニウム(AIりの電食不良が従来よシ減少す
ることが認められた。When we actually compared the polar type IO, it was found that the electrolytic corrosion defects caused by aluminum (AI) were certainly reduced compared to the conventional one.
また、減圧処理炉11に供給する雰囲気ガスは、例えば
第2図に示すように酸素(0,)、?5、モノシラン(
S i’H4) 26.およびリン化水素(PH,)
、27の各気体を噴出できるように移送管19、開閉
弁21および流量計22を追加して設置するようにして
もよい。この場合、焼なまし後減圧状態を維持した脣ま
上記気体を噴出させるようにする。これはアルミニウム
等の配線金属に表面保護膜を形成するものである。した
がって、より完全が水分の分離ができ電食不良の防止に
々る。Further, the atmospheric gas supplied to the decompression processing furnace 11 is, for example, oxygen (0,), ?, as shown in FIG. 5. Monosilane (
S i'H4) 26. and hydrogen phosphide (PH,)
, 27, a transfer pipe 19, an on-off valve 21, and a flow meter 22 may be additionally installed. In this case, the above gas is ejected while maintaining the reduced pressure state after annealing. This is to form a surface protective film on wiring metal such as aluminum. Therefore, moisture can be separated more completely, which helps prevent electrolytic corrosion defects.
以上のようにこの発明の半導体製造装置によれば、焼々
まし処理中に配線金属と酸化膜寸たはOV D +1か
との接合面に合金層を形成してこれらを密着させるとと
もに、粒界の水酸化腐蝕(電1食)も防止することがで
きる。このため配線パターンの細い半導体集積回路では
、従来に比べてとくに顧著な有効性を発揮して安定した
′Fl(気持性が得られ、製品の信頼性を向上すること
ができる。As described above, according to the semiconductor manufacturing apparatus of the present invention, an alloy layer is formed on the bonding surface between the wiring metal and the oxide film size or OV It can also prevent hydroxide corrosion (electrical corrosion). For this reason, in semiconductor integrated circuits with thin wiring patterns, it is particularly effective compared to conventional methods, and stable 'Fl (comfortability) can be obtained, and product reliability can be improved.
第1図はこの発明の一更施例を説明する半導体製造装置
の構成図、第2図はこの発明の他の実施例の構成図であ
る。
11・・・減圧型処理炉、12・・・ジヨイント、13
・・・減圧手段(真空ポンプ)、14・・・減圧モニタ
、15・・・半導体基板、16・・・治具(ボート)、
17・・・加熱手段(レジスタン4−タ)、18・・・
ノズル列、19・・・移送管、20・・・マニホルド、
21・・・開閉弁、22・・・流量計、23・−・水素
(H,)、24・・・窒素(N、)、25・・・酸素(
0,)、26・・・モノシリカン(S IH4)、27
・・・リン化水素(PH3)。FIG. 1 is a block diagram of a semiconductor manufacturing apparatus illustrating a further embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment of the present invention. 11...Reduced pressure type processing furnace, 12...Joint, 13
... pressure reduction means (vacuum pump), 14 ... pressure reduction monitor, 15 ... semiconductor substrate, 16 ... jig (boat),
17... Heating means (resistance 4-ta), 18...
Nozzle row, 19... Transfer pipe, 20... Manifold,
21... Opening/closing valve, 22... Flow meter, 23... Hydrogen (H,), 24... Nitrogen (N,), 25... Oxygen (
0, ), 26... Monosilicane (SIH4), 27
...Hydrogen phosphide (PH3).
Claims (1)
減圧する減圧手段と、上記処理炉を加熱する加熱手段と
、上記処理炉内に複数種の雰囲気ガスを注入する手段と
を具備したことを特徴とする半導体製造装置。A reduced pressure processing furnace for accommodating a semiconductor substrate, a pressure reduction means for reducing the pressure inside the processing furnace, a heating means for heating the processing furnace, and a means for injecting a plurality of types of atmospheric gas into the processing furnace. A semiconductor manufacturing device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57112960A JPS594031A (en) | 1982-06-30 | 1982-06-30 | Manufacturing device of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57112960A JPS594031A (en) | 1982-06-30 | 1982-06-30 | Manufacturing device of semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS594031A true JPS594031A (en) | 1984-01-10 |
Family
ID=14599841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57112960A Pending JPS594031A (en) | 1982-06-30 | 1982-06-30 | Manufacturing device of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS594031A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6236530U (en) * | 1985-08-21 | 1987-03-04 |
-
1982
- 1982-06-30 JP JP57112960A patent/JPS594031A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6236530U (en) * | 1985-08-21 | 1987-03-04 |
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