JPS59502090A - Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ - Google Patents

Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ

Info

Publication number: JPS59502090A
Authority: JP; Japan
Prior art keywords: input; output; port; arbiter; character
Prior art date: 1982-11-23
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

JP59500090A

Other languages

English (en)

Japanese (ja)

Other versions

JPH0253983B2 (2

Inventor

クラ−ク・ベツキ−・ジエ−ン

Original Assignee

バロ−ス・コ−ポレ−ション

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1982-11-23

Filing date

1983-11-18

Publication date

1984-12-13

1983-11-18 Application filed by バロ−ス・コ−ポレ−ション filed Critical バロ−ス・コ−ポレ−ション

1983-11-18 Priority claimed from PCT/US1983/001803 external-priority patent/WO1984002239A1/en

1984-12-13 Publication of JPS59502090A publication Critical patent/JPS59502090A/ja

1990-11-20 Publication of JPH0253983B2 publication Critical patent/JPH0253983B2/ja

Status Granted legal-status Critical Current

Links

230000004044 response Effects 0.000 claims description 11
239000011159 matrix material Substances 0.000 claims description 9
239000000872 buffer Substances 0.000 description 46
230000007704 transition Effects 0.000 description 7
238000010586 diagram Methods 0.000 description 6
230000008859 change Effects 0.000 description 2
230000004048 modification Effects 0.000 description 2
238000012986 modification Methods 0.000 description 2
241000238413 Octopus Species 0.000 description 1
230000005540 biological transmission Effects 0.000 description 1
230000000903 blocking effect Effects 0.000 description 1
238000001514 detection method Methods 0.000 description 1
235000012054 meals Nutrition 0.000 description 1
230000005012 migration Effects 0.000 description 1
238000013508 migration Methods 0.000 description 1
KRTSDMXIXPKRQR-AATRIKPKSA-N monocrotophos Chemical compound CNC(=O)\C=C(/C)OP(=O)(OC)OC KRTSDMXIXPKRQR-AATRIKPKSA-N 0.000 description 1
235000002020 sage Nutrition 0.000 description 1
210000002784 stomach Anatomy 0.000 description 1
238000010415 tidying Methods 0.000 description 1
235000021419 vinegar Nutrition 0.000 description 1
239000000052 vinegar Substances 0.000 description 1

Landscapes

Data Exchanges In Wide-Area Networks (AREA)
Small-Scale Networks (AREA)

JP59500090A 1982-11-23 1983-11-18 Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ Granted JPS59502090A (ja)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US443967		1982-11-23
PCT/US1983/001803 WO1984002239A1 (en)	1982-11-23	1983-11-18	Speed independent arbiter switch employing m-out-of-n codes

Publications (2)

Publication Number	Publication Date
JPS59502090A true JPS59502090A (ja)	1984-12-13
JPH0253983B2 JPH0253983B2 (2)	1990-11-20

Family

ID=22175583

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP59500090A Granted JPS59502090A (ja)	1982-11-23	1983-11-18	Ｎ個のうちのｍ個のコ−ドを用いる速度自在ア−ビタスイッチ

Country Status (1)

Country	Link
JP (1)	JPS59502090A (2)

1983
- 1983-11-18 JP JP59500090A patent/JPS59502090A/ja active Granted

Also Published As

Publication number	Publication date
JPH0253983B2 (2)	1990-11-20

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