JPS5953632B2 - Data processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system, and more particularly, to updating a memory reference history bit in a computer system that uses a buffer memory system.

In general, computer systems have a reference history bit for each desired block unit (hereinafter, this unit is referred to as a page) of main memory in order to manage memory usage status.

When an arbitrary area within a page is accessed, the corresponding reference cover history bit is set, and then this bit is reset by issuing a reference cover history bit reset instruction (hereinafter referred to as the RRB instruction). . RRB commands are issued at predetermined time intervals, and if the reference override bit of the page specified by the RRB command is set, the data of the corresponding page in the memory management table is incremented by 1, and then the reference override bit is set. Executes processing to reset history bits. Therefore, the program can grasp the usage status of the main memory ρ from the contents of the memory management table. This can be done, for example, by expelling the contents of a page in main memory,
When loading new programs or data from external memory such as a disk or drum into main memory, it is used to determine the page to be evicted. On the other hand, in order to improve processing speed, in large-scale computer systems, the central processing unit (CPU) is equipped with a high-speed buffer memory.
A copy of the main memory is stored in this, and when a memory reference request is issued, the target instruction or data is read out from the buffer memory at high speed.

The problem here is, when the target instruction or data is read from the buffer memory, how to reflect the reference to the buffer memory in the reference history bit of the corresponding page in the main memory. Conventionally, as a method for reflecting the reference to this buffer memory in the reference history bit, the buffer memory has a reference history bit, or the history history bit is only held in the main memory, and the target instruction or data is read from the buffer memory. There is also a known method of setting the relevant reference history bit in main memory even in such cases. However, the former method uses RR during block eviction and multiprocessor configuration.
The latter method has the disadvantage that control is complicated when executing the B instruction, and the latter method requires setting the corresponding reference history bits in the main memory one by one even when the target data etc. are obtained from the buffer memory. It has the disadvantage that the advantage of providing it is lost. The present invention was made to eliminate these drawbacks, and the reference history bit is provided only in the main memory, and is set in response to a reference to the main memory.
When the RB instruction is executed, the buffer memory (and address translation table, etc. if the virtual memory method is used) is searched, and if the corresponding page is registered, it is invalidated and at least the first time after the RRB instruction is executed for the corresponding page. The reference cover history bit is set so that the access is made to the main memory, and then when the target instruction or data is read from the buffer memory, the operation of setting the corresponding reference cover history bit in the main memory one by one is eliminated, This provides a data processing method that speeds up processing.

Hereinafter, the present invention will be explained in detail with reference to the drawings. The figure is a block diagram of an embodiment of the present invention. When an RRB instruction is executed, the corresponding entry in the buffer memory specified by the instruction is searched and invalidated, and in particular, the RRB instruction is repeatedly executed. search buffer memory if
Processing such as invalidation of the corresponding program is interrupted and a series of RRs are executed.
This is an example in which the buffer memory is searched and the corresponding blocks are invalidated all at once when the last RRB instruction of the B instructions is executed to further speed up the processing.

In the figure, 1 is an address input terminal, 2 is an address register that holds an upper address (page address), and 3 is an address register that holds an upper address (page address).
4 is a buffer address array that registers the main memory address (page address) of data stored in buffer memory 5; 5 is buffer memory; 6 is buffer memory; Address register 2 and buffer address array 4
7 is a selector that selects the read data of the buffer memory 5 based on the match signal from the match detecting circuit 6, and 8 is an output terminal for the read data.

9 and 10 are registers that hold the range of the invalidation area; in this case, register 9 holds the lower limit address of the range, and register 1
0 shall hold the upper limit address.

11 is a comparison circuit that compares the address of address register 2 with the address of register 10 to see if it is larger; 12 is a comparison circuit that compares the address of register 9 with the address of address register 2 to see if it is smaller; 13 is an output terminal for outputting addresses to the main memory and other CPUs; 14 is a counter used to sequentially designate the row positions (entry positions) of the buffer address array 4 and the buffer memory 5 when searching the buffer memory; 15, 1;
6 is a selector, and 17 is a latch circuit that indicates the validity of registers 9 and 10.

Normally, latch circuit 17 and counter 14 are in a reset state.

Assume that in this state, a memory reference address arrives from input terminal 1, and an upper address is set in address register 2, and a lower address is set in address register 3. The contents of the address register 3 specify a row position in the buffer address array 4 and buffer memory 5, and the address and data registered in the corresponding row are read out. Comparison circuit 6 compares the address read from buffer address array 4 with the address in address register 2, and if they match, sends a match signal to selector 7. This results in
The selector 7 selects the data read from the buffer memory 5 and sends it to the output terminal 8. If the address in the address register 2 and the address in the buffer address array 4 do not match, the address in the address register 2 is given to the main memory through the output terminal 13, and the target data is obtained from the main memory. Next, the operation when an RRB command is issued will be explained. R when the latch circuit 17 indicating the validity of registers 9 and 10 is set.
When the RB instruction is executed, the reference history bit reset address in the RRB instruction set in the address register 2 via the input terminal 1 is stored in registers 9 and 10, and is also sent to the main memory and other CPUs via the output terminal 13. The corresponding reference history bit is set.
At the same time, the latch circuit 17 is set and the counter 14 starts incrementing. Since the contents of this counter 14 are given to the buffer address array 4 via the selector 15 and the address register 3, the address registered in the buffer address array 4 corresponds to the incrementing operation of the counter 14. They are read out sequentially starting from the row position. The address read from buffer address array 4 is inputted to each comparison circuit 11, 12 through selector 16, and compared with the address stored in register 9, 10, respectively. If the comparison results of the comparison circuits 11 and 12 are both negative, that is, if the read address of the buffer address array 4 matches the contents of the registers 9 and 10 or is included in the range thereof, the buffer address array 4 and invalidate the corresponding entry in the buffer memory 5. In addition,
In this case, the same contents are stored in registers 9 and 10, so we only need to pay attention to whether the contents match the contents of these registers 9 and 10, and whether or not they are included in the range of registers 9 and 10. The problem is that, as will be described later, the next RRB is
This is when an order is issued. When the latch circuit 17 is set, execution of the next instruction starts, and if the address associated with that instruction (upper address) is set in address register 2, that address is equal to the contents of registers 9 and 10. Comparing circuits 11 and 12 monitor whether the data are equal or within the range indicated by the contents of registers 9 and 10, and if they are equal or within the range, even if the data of interest is in the buffer memory 5, The address of the address register 2 is given to the main memory through the output terminal 13 to allow direct access to the main memory.

On the other hand, if the next RRB instruction is issued before the counter 14 overflows, that is, before all entries in the buffer address array 4 have been searched,
If the counter 14 is reset at that point, either the reference history bit reset address specified by the RRB instruction set in address register 2 is smaller than the address already stored in register 9, or Comparing circuits 11 and 12 compare whether the address stored in register 10 is larger than the address stored in register 10. If the address of address register 2 is smaller than the contents of register 9, the contents of register 9 are transferred to address register 2.
Similarly, if the address of address register 2 is larger than the contents of register 10, the contents of register 10 are replaced with the address of address register 2.

Thereafter, the counter 14 starts incrementing, and the addresses of the buffer address array 4 are sequentially read out, and the contents of the registers 9 and 10 are compared with the contents of the registers 9 and 10 by the comparison circuits 11 and 12. R again
When the RB command is issued, the counter 14 is reset, and after updating the range indicated by the registers 9 and 10, the counter 14 starts incrementing, and the buffer address array 4 and the buffer address array 4 are updated. The search and invalidation of the memory 5 is restarted from the beginning.In this way, when the last RRB instruction of the series of RRB instructions is executed and the counter 14 overflows, the registers 9 and 10 and the counter 14 are cleared. In this example, when an RRB instruction is executed, only the corresponding entry in the buffer memory 5 indicated by the range of registers 9 and 10 is invalidated, but when the last RRB instruction of a series of RRB instructions is issued, the counter Even if the buffer address array 4 and the buffer memory 5 are detected by overflowing, and all entries in the buffer address array 4 and the buffer memory 5 are invalidated at this point, the intended purpose can be achieved.

In this case, it is not necessary to update the address range using the registers 9 and 10, and it is only necessary to reset and restart the counter 14 each time an RRB command is issued. Tamashi, for example RR
It is necessary to provide a latch that is set when B instructions are issued consecutively, and to perform an AND condition between the output of this latch and the overflow output of the counter 14. As explained above, according to the present invention, in order to search and invalidate the corresponding entry in the buffer memory when an RRB instruction is executed, at least the first access to the corresponding program is performed from the main memory, By setting the relevant reference history bit in the memory, even if the desired instruction or data is subsequently obtained from the buffer memory, there is no need to go back and set the relevant reference history bit in the main memory, reducing processing time. .

Also, during the buffer memory search/invalidation process, RRB is re-entered.
When an instruction is decoded, the processing associated with the previous RRB instruction is interrupted, and the processing of searching and invalidating the corresponding block is postponed, allowing high-speed processing even when RRB instructions are issued frequently. There are advantages.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the data processing method according to the present invention. 1... Address input terminal, 2, 3...
Address register, 4... Buffer address array, 5... Buffer memory, 6, 11, 12
... Comparison circuit, 7, 15, 16 ... Selector, 8 ... Data output terminal, 9, 10 ...
... Register, 13 ... Address output terminal, 14 ... Counter, 17 ... Latch circuit.

Claims (1)

[Scope of Claims] 1. A central processing unit having a main memory and a buffer memory for storing copies of instructions, data, etc. on the main memory, In a computer system having a mechanism for providing a memory reference history bit that is set by accessing memory and resetting the bit by a reference history bit reset instruction (hereinafter referred to as RRB), when executing the RRB instruction, The corresponding memory reference history bit is searched and invalidated in the buffer memory specified by the instruction, and the first access to the block after the execution of the RRB instruction is made to the main memory. A data processing method characterized by setting . 2 When the next RRB instruction is decoded during the search/invalidation process, the search/invalidation process associated with the previous RRB instruction is interrupted, and the buffer memory is read all at once when the last RRB instruction of the series of RRB instructions is executed. The data processing method according to claim 1, characterized in that search and invalidation processing is performed.