JPS5953636B2 - semiconductor memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binary information storage circuit, and particularly to a semiconductor memory cell suitable for integration into an integrated circuit.

In a large-capacity, high-speed operation memory IC, when reading the contents of a memory cell, the read current IR that can be passed while the operation is stable.
It is necessary that the current be as large as, for example, about 1 mA.

Furthermore, considering the case of integration such as 4096 words x 1 bit/IC, the read current IR mentioned above is the current consumption of only the selected 1 bit, and the unselected 4095 bits are used only for retaining the contents. Since the holding current H is consumed, a total of IR+4095 x H is consumed. In reality, the holding current IH term becomes dominant, and particularly in large capacity storage, it is effective to reduce this IH in order to reduce current consumption. Conventionally, this type of memory cell is called ESSCC.
-ESSC Engineering RC79Digest0fTechnfc
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adCharacteristio'' and describes the advantages and disadvantages of various memory cells.

The collector load of the transistor pair constituting the memory cell is in the first case a resistor, in the second case a resistor connected in parallel with a diode with a series resistance, and in the third case a resistor connected in parallel with a diode with a series resistance. It is a series connection of Schottky diodes with resistance. The structure is shown in FIGS. 1 to 3.

In FIG. 2, the PN junction diode is replaced with a Schottky diode to reduce the voltage drop in the memory cell when reading the memory cell, and in FIG. 3, the series resistance of the Schottky diode unnecessary for basic operation is removed. The first point to note in this type of circuit is the potential difference ΔVC between the collectors of the cross-coupled transistors.
The voltage difference ΔVC between the collectors is shown. In FIG. 1, the resistors R11 and R12 are 10Ω, and the collector-collector potential difference ΔVC is the difference in voltage drop between R11 and R12.

When I (total current consumption of memory cells) increases from zero, ΔVC
increases, and when it further increases, ΔVC decreases due to the saturation phenomenon of the transistor. In FIG. 4, the transistor current amplification factor hFE=50 is shown by a curve C41. Voltage ΔV
C is a constant voltage on static failure prevention and dynamic failure prevention;
For example, if it is set to about 25V, ID/IH--50hFE (transistors Tll, T12) can be seen in Figure 4. It doesn't fit.

In the conventional example shown in Figure 2, resistors R2l and R22 are 200kΩ, R
The curve of ΔC when S2l, 22 is a 250Ω transistor and the HFB of T22 is 50 is curve 42 in FIG.
Indicated by

In the low current region, ΔC is secured by the difference in voltage drop between R2l and R22, and in the high current region, the Schottky diode D2
ΔVC is ensured by the difference in voltage drop across the series resistors RS2l and RS22. Therefore, since the ratio of IR/IH can be set fairly freely by the values of resistors R2lJR22 and resistors RS2l and RS22, it is expected that the current consumption in the holding state will be reduced and the speed of successive writing will be increased. Furthermore, the possibility of realizing it as a monolithic semiconductor integrated circuit is good. However, as seen in Figure 4, Δ
There is a region where VC drops extremely, and as the resistance value is set to increase the IR/IH ratio, the valley becomes deeper, and there is a current region where operation is unstable. Figure 3 shows Schottky diodes connected in series with a large coefficient N, which indicates the goodness of the junction, and the voltage drop VSBD of one Schottky diode is N-KTISBDSBD=? 1n? It is indicated by.

QISq /KT: Thermal stress of the diode IS: Reverse saturation current of the diode ISBD: Forward current flowing through the Schottky diode From these, if the current amplification factors of transistors T2l and T22 are HFB, ΔVC is 2N-RT Δc= ? 1nhFEq, and ΔVC is independent of ISBD.

In Figure 4, the value is 43 when N=1,5 and hFE=50.
is shown by the curve. In this example as well, the current consumption in the holding state is low, and high-speed operation can be expected during read/write operations.
Stable operation can be expected with a constant VC, but in order to realize it with a monolithic semiconductor, an additional insulation area is required than in the conventional example shown in Figures 1 and 2 due to the series connection of Schottky diodes. .

This becomes a big problem when a large capacity memory is installed in a limited area. In addition, this memory cell is particularly suitable for word line WL8l and digit lines DL2l and DL during reading.
The voltage drop between 22 is large, and the diode) D3l, D
0.6V1 at 32 and 0.6V at D3Ol and D3O2
When the transistors T3l and T32 are ON, a total voltage of about 2V is required between the base and emitter of 0.8, which is disadvantageous when lowering power or combining conventional logic for peripheral logic circuits.

A first object of the present invention is to provide a memory cell in which the ratio of the read current to the holding current is set to a large value and the read and write operations are high-speed while requiring low power. Another object of the present invention is to provide a memory cell which has a large collector-to-collector potential difference for retaining cell contents and is operationally stable.

Another object of the present invention is to provide a memory cell with a small inter-element insulation region, that is, a small area.

Another object of the present invention is to provide a memory cell in which the voltage drop from the word line of the memory cell to the constant current source and digit line is small, and therefore can be operated at low voltage. Therefore, according to the present invention, when the total current 1 in FIG. 1 is large and the transistors Tll and Tl2 are about to enter saturation, the collector-emitter voltage of the transistors is close to zero, and therefore the collector load Rll or Rl2O voltage The descent is PN
This is sufficient to bring the junction to 0N.

It is conceivable to use a transistor with a current amplification factor here. That is, 2. Two mutually equal, multi-emitter bipolar transistors are provided, the collectors of which are connected to a common word line through an impedance element, the bases and collectors of each of them being cross-coupled, the first emitter of each of them being connected to a common word line through an impedance element, and the first emitter of each of and further have their respective second emitters connected to a common constant current source, including transistors complementary to the transistor, whose emitters are commonly connected to the word line, and whose bases are connected to the word line. By connecting the collectors of the transistors and the collectors to the digit lines, the collector current of the transistors that retain memory contents can be amplified, and high-speed operation can be expected because the transistors are prevented from entering saturation. . Next, the present invention will be explained in detail with reference to FIGS. 5 to 9.

FIG. 5 shows the first embodiment, FIG. 6 shows the second embodiment, FIG. 7 shows the collector voltage ΔVC with respect to the memory cell current 1 in the first and second embodiments, and FIG. An embodiment of the monolithic semiconductor integrated circuit according to the first embodiment, FIG. 9 is a cross-sectional view taken along the plane I-1' of FIG. 8. Fifth
In the figure, load resistors R5l and R52 are connected to word line WL5.
The other ends are connected to the collectors of NPN transistors T5l and T52, respectively. The bases and collectors of the NPN transistors T5l and T2 are cross-coupled with each other, and their first emitters are connected to a common contact CL5l, through which a holding current 1H flows out. Furthermore, the second emitter of T5l is connected to digit line DL5l, and the second emitter of T52 is connected to digit line DL52. The emitter of the PNP transistor T5Ol is connected to the word line WL5l, the base to the collector of the transistor T5l, and the collector to the digit line DL5l. PNP transistor T5O2 is T5Ol
The emitter is connected to WL5l, the base is connected to the collector of T52, and the collector is connected to DL52. In explaining the operation here, the transistor T5
Consider the case where l is 0N and T52 is 0FF, most of the holding current 1H flows through the resistor R5l, and the read current 1R flows into the digit line DL5l.

The values of the resistors R5l and R52 are set to be slightly larger, for example, 100 kΩ, compared to the first conventional example. Consider a case in which the potentials of digit lines DL5l and DL52 are higher than that of contact CL5l. The value of IH is that the voltage drop across resistor R5l is PN.
The current value is set to 4 μA, which is sufficient to keep the P transistor T5Ol at 0FF and to retain the contents of the memory cell. If the current amplification factor HFE of T5l is 50, the voltage drop of R5l is about 0.4V, the voltage drop of R52 is 8mV, the collector voltage ΔVC is about 0.4, and the base-emitter voltage of transistor T5l, which is 0N, is 0. It is about .8. When the potential of the digit lines DL5l and DL52 is lowered to be lower than the contact CL5l, the current flowing through the first emitter of T5l flows to the digit line D5l through the second emitter.

Furthermore, when the potential of DL5l and DL52 is lowered, the base-emitter voltage of T5l hardly increases beyond about 0.8, so a change in potential appears across the resistor R52,
IRl changes by 0.1μA and ICl changes by 5μA.
A changes, resulting in 9μA. At this time, the voltage drop across R5l is 100kΩ x 9μA = 0.9V, but it is clamped at approximately 0.8 due to the base-emitter diode characteristics of transistor T5Ol, and the current flowing through R5l is JA.
limited to. Therefore, the remaining current of ICl becomes the base current 1B2 of the transistor T5Ol, and its collector current C2 is the current amplification factor HFE of the PNP transistor.
The current is multiplied (for example, by 10 times) and 10 μA flows out to DL5l. If you further lower the digit lines DL5l and DL52,
An increase in IBl causes an increase in C1, and the increase in PNP
The base current 1B2 of the transistor T5Ol increases, and IC2 may also increase rapidly.

At this time, the ratio of the increase in IC2 to the increase in IBl is (HFE of T5Ol)×(HFE of T5O2).
When the collector current IC2 of transistor T5Ol is 1mA, B2=100μA, IRl=0.8/100kΩ=
8 μA, Cl = 108 μA, IBl + 2.16 μA, and collector voltage ΔVC = BE (T5Ol) - 1B1X
R52=0.8V-2.16μA×100kΩ=0.5
It becomes 84V.

Therefore, even for a current of 1 mA, ΔC has a value that can sufficiently withstand static and dynamic disturbances. At this time, the voltage between the collector and the emitter of the transistor T5l is actually close to zero and has entered saturation, so the above current value and voltage value deviate slightly, but there is no significant difference. Figure 7 Curve 75
indicates the calculated ΔVC, which indicates that the current value at which the memory cell can operate is that the IR/IH value can be set to 1 mA/4 μA while using the same NPN transistor as in the conventional example.

In the second embodiment of FIG. 6, an impedance load in series with a resistor and a Schottky diode is used as the load for the cross-coupled transistors.

Schottky diodes D6l and D62 in this example are 0N
It is included to offset the base potential of the NPN transistor by, for example, about 0.3. For this reason, PNP
When the transistor T6Ol is 0N, the voltage between the collector and emitter of the NPN transistor T6l is (Schottky diode D62: 0.3) + (base-emitter voltage of T6l: 0.8) - (base-emitter voltage of T6Ol: 0). .8V) = 0.3, it is possible to increase the saturation by maintaining the voltage drop of D62, and it is expected that the write operation speed of the memory cell will be increased. A curve 76 in FIG. 7 shows the collector voltage ΔVC with respect to the memory cell current of this embodiment. Although ΔC decreases slightly, the value of IR/IH is reduced to 1 mA.
This shows that it can be set to /4μA. In both embodiments, the potential difference between the word line and the digit line during reading is (voltage drop of R52: 0.22) + (T5l) in the first embodiment.
0N voltage between base and emitter: 0.8V) = LO2V
In addition, in the second embodiment, the forward voltage of the Schottky diode is 0.3V, and the total is 1.32V.
The voltage drop is smaller than that of the conventional example shown in FIG.

FIG. 8 shows an example in which the first embodiment is implemented as a silicon monolithic semiconductor integrated circuit. Memory cells are B1 and C
The base-emitters of NPN transistors T8l and T82 are cross-coupled by the first-layer metal region connecting C1 and B2, and the first-layer metal region connecting C1 and B2, and the first emitter Ell of T8l is cross-coupled by the first-layer metal region connecting C1 and B2. , through the through ball to the second layer metal region forming the digit line DL8l. In exactly the same way, the first emitter E2l of T82 is connected to the digit line DL8l. The second emitter El2 of T8l and the first emitter E22 of T82 are connected by a first layer metal region to a common contact CL8l, and the resistors R8l, R82 each have one end connected to the first emitter together with the emitters of lateral PNP transistors T8Ol and T8O2. It is connected to a word line WL8l consisting of a layered metal region, and the other end is connected to each T8l.
It is connected to the base of T82 and the base of T82. The N epitaxial layer forms the collector regions of the NPN transistors T8l, T82 and also forms the lateral PNP transistor T8.
A base of Ol, T8O2 is formed, and it is designed to be connected without using a metal wiring layer. T8Ol collector CP
1 is connected from the first layer metal region to the second layer metal region forming the digit line DL8l through a through hole.
In exactly the same way, collector CP2 of T8O2 is also connected to DL82. As explained above, the present invention provides a PNP transistor amplification bypass circuit between the memory cell and the read digit line, thereby reducing the area occupied by the memory cell and achieving stable operation for retaining the cell contents. Above,
This has the advantage that the holding current can be extremely small and at the same time the read current for speeding up can be set extremely large.

[Brief explanation of drawings]

Figures 1 to 3 are memory cell circuit diagrams according to conventional examples;
FIG. 5 is a circuit diagram of the first embodiment of the present invention, FIG. 6 is a circuit diagram of the second embodiment of the present invention, FIG. 7 is a diagram showing the potential difference between specific points with respect to the memory cell current of the first and second embodiments of the present invention, and FIG. 8 is an example of the first embodiment of the present invention implemented as a monolithic semiconductor integrated circuit. FIG. 9 is a cross-sectional view showing the I-" plane in FIG.
...Complementary transistor, Rll, Rl2, R
2l...Resistance, D2l, D22, D3l...
...Shotkey diode.

Claims (1)

[Claims] 1 has two transistors whose collectors are connected to a common word line through an impedance element, whose bases and collectors are cross-coupled, and whose respective first
a memory cell having an emitter connected to each digit line and a second emitter connected to a common constant current source, the memory cell including a transistor complementary to the transistor, and having its emitter connected to the word line in common. , their bases are connected to the collectors of the transistors, and their collectors are connected to the digit lines.