JPS595690A - Semiconductor laser - Google Patents

Semiconductor laser

Info

Publication number
JPS595690A
JPS595690A JP11419082A JP11419082A JPS595690A JP S595690 A JPS595690 A JP S595690A JP 11419082 A JP11419082 A JP 11419082A JP 11419082 A JP11419082 A JP 11419082A JP S595690 A JPS595690 A JP S595690A
Authority
JP
Japan
Prior art keywords
layer
type inp
mesa stripe
active layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11419082A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Kitamura
北村 光弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11419082A priority Critical patent/JPS595690A/en
Publication of JPS595690A publication Critical patent/JPS595690A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching
    • H01S5/2277Buried mesa structure ; Striped active layer mesa created by etching double channel planar buried heterostructure [DCPBH] laser

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To facilitate high output power operation and to improve a characteristic yield, in semiconductor laser having a heterogeneous structure, by forming a current block layer structure at a part where the layer is closer to a substrate than an active layer, in addition to a current block layer, which is formed on both sides or in the vicinity of the active layer. CONSTITUTION:A mesa stripe 102 is formed on an N type InP substrate 101. On the substrate 101, a P type InP layer 103, an N type InP clad layer 104, a nondoped In0.72Ga0.28As0.61P0.39 active layer 105 corresponding to an oscillating wavelength of 1.3mum, and P type InP clad layer 106 are sequentially laminated by a liquid phase epitaxial method. In this case, the P type InP layer 103 is not grown on the upper surface of the mesa stripe 2. Mesa etching is performed on said semiconductor wafer. Two etching grooves 107 and 108 and a mesa stripe 109, which separates the grooves, are formed at this time. Embedded growing is performed in the semiconductor wafer, wherein the mesa stripe 109 is formed. Then, a P type InP current block layer 110 and an N type InP current block layer 111 are laminated all-over except only on the surface of the mesa stripe 109. Thereafter, a P type InP embedded layer 112 and an electrode layer 113 are laminated, and finally an electrode is formed.

Description

【発明の詳細な説明】 本発明は活性層の周囲を活性層よりもエネルギーギャッ
プが大きく、かつ屈折率の小さな半導体材料で埋め込ん
だ埋め込みへテロ構造半導体レーザ、特に高光出力動作
特性の改善された埋め込みへテロ構造半導体レーザに関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buried heterostructure semiconductor laser in which the active layer is surrounded by a semiconductor material having a larger energy gap and a lower refractive index than the active layer. This invention relates to buried heterostructure semiconductor lasers.

埋め込みへテロ構造半導体レーザ(BH−LD)は低い
発振しきい値電流、安定化された発振横モード、高温動
作可能などの優れた特性を有しているため、光フアイバ
通信用光源として注目を集めている。本願の発明者らは
特願昭56−166666に示した様に2本のほぼ平行
な溝にはさまれて形成された発光再結合する活性層を含
むメサストライプの周囲で確実に電流ブロック層を形成
することのできるBH−LDを発明した。このBH−L
Dは、温度特性に優れ、種々の基板処理過程でのダメー
ジを受けることが少なく製造歩留りの向上したものであ
る。ところでこの例のBH−LDに限らず、一般にBH
−LDにおいては、もれ電流は完全に無くすことのでき
ない課題である。前述のBH−LDも他のタイプのBH
−LDも一般に、半導体のp−n−p−n電流ブロック
構造をもちいて、もれ電流を可能な限り低減しようとし
ている。しかしながら、片面光出力59mW以上の大光
出力動作をさせようとすると、埋め込み活性層のわきを
流れるもれ電流も大きくなる。するとこのもれ電流が前
述のp−rl−p−n  電流ブロック構造におけるゲ
ート電流となり、電流ブロック構造がブレークダウンを
起こすようになる。それに伴なって光出力も急激に飽和
してしまい、いくら注入電流をふやしても、活性層に有
効に注入されずに高い光出力を得ることができなくなる
。この様な高出力動作特性を改善するために活性層上部
以外を絶縁膜でおおったり、あるいは活性層上部のみを
不純物拡散して、いわゆるブレーナ・ストライプ構造と
する試みがなされているが、電極形成が難かしく信頼性
lこ乏しかったり、また内部の電流ブロック構造が有効
に機能しなくなると、電流が基板側に大きく拡がってし
まうようになる。すなわち、これまでのBH−LDでは
、活性層付近の電流ブロック構造に対し、成長層表面側
に電流狭さく機構を有していたので、いったん活性層周
辺のp−n−p−n  電流ブロック構造が有効に働か
なくなると、急激に光出力の飽和を起こしてしまう。こ
のようなことを防ぐには、活性層よりも基板側に別の電
流ブロック機構を形成しておけばよいわけである。
Buried heterostructure semiconductor lasers (BH-LDs) have excellent characteristics such as low oscillation threshold current, stabilized oscillation transverse mode, and high-temperature operation, so they are attracting attention as light sources for optical fiber communications. are collecting. As shown in Japanese Patent Application No. 56-166666, the inventors of the present application have ensured that a current blocking layer is formed around a mesa stripe containing an active layer that recombines light and is formed between two substantially parallel grooves. We have invented a BH-LD that can form . This BH-L
D has excellent temperature characteristics, is less susceptible to damage during various substrate processing processes, and has an improved manufacturing yield. By the way, not only BH-LD in this example, but BH-LD in general
- In LD, leakage current is a problem that cannot be completely eliminated. The above-mentioned BH-LD is also a BH of other types.
-LD also generally uses a semiconductor p-n-p-n current block structure to reduce leakage current as much as possible. However, when attempting to operate with a high optical output of 59 mW or more on one side, the leakage current flowing beside the buried active layer also increases. This leakage current then becomes the gate current in the p-rl-pn current block structure described above, causing breakdown of the current block structure. Correspondingly, the light output also saturates rapidly, and no matter how much the injection current is increased, the light is not effectively injected into the active layer, making it impossible to obtain a high light output. In order to improve such high-output operating characteristics, attempts have been made to cover the area other than the upper part of the active layer with an insulating film, or to diffuse impurities only in the upper part of the active layer, creating a so-called Brenna stripe structure. If it is difficult and has poor reliability, or if the internal current block structure no longer functions effectively, the current will spread greatly toward the substrate side. In other words, in conventional BH-LDs, in contrast to the current blocking structure near the active layer, the current narrowing mechanism was provided on the surface side of the growth layer, so once the pn-pn current blocking structure around the active layer If it no longer works effectively, the optical output will suddenly become saturated. To prevent this, it is sufficient to form another current blocking mechanism closer to the substrate than the active layer.

本発明の目的は、製造歩留りが高く、高光出力動作特性
の改善されたBH−LDを提供することにある。
An object of the present invention is to provide a BH-LD with high manufacturing yield and improved high optical output operating characteristics.

本発明による半導体レーザの構成は半導体基板上に少な
くとも活性層を含む半導体多層膜を積層させた多層膜構
造半導体ウェファに、前記活性層よりも深く形成された
2本の平行な溝によってはさまれたメサストライプを形
成した後埋め込み成長してなる埋め込みへテロ構造半導
体レーザにおいて、前記多層膜構造半導体ウェファが、
少なくとも前記メサストライプ周辺を除いて、異なる導
電型の半導体層が交互に積層された電流ブロック構造を
有することを特徴としている。
The semiconductor laser according to the present invention has a structure in which a semiconductor wafer has a multilayer film structure in which a semiconductor multilayer film including at least an active layer is laminated on a semiconductor substrate, and is sandwiched between two parallel grooves formed deeper than the active layer. In the buried heterostructure semiconductor laser formed by forming a mesa stripe and then growing the buried heterostructure semiconductor laser, the multilayer structure semiconductor wafer comprises:
It is characterized by having a current block structure in which semiconductor layers of different conductivity types are alternately stacked except at least around the mesa stripe.

以下、実施例を示す図面を用いて本発明を説明する。EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated using drawing which shows an Example.

第1図は本発明の第1の実施例であるBH−LDの製造
工程を示す概略図を示す。このようなりH−LDを得る
にはまず図中(1)に示したように(100)n−In
P基板101に< 011 > 方向に平行にメサスト
ライプ102を形成する。このメサストライプ102は
幅10μm1深ざ肛μm 程度とすればよい。
FIG. 1 shows a schematic diagram showing the manufacturing process of a BH-LD which is a first embodiment of the present invention. To obtain such H-LD, first, as shown in (1) in the figure, (100) n-In
Mesa stripes 102 are formed on a P substrate 101 in parallel to the <011> direction. The mesa stripe 102 may have a width of about 10 μm and a depth of about 1 μm.

これは通常のフォトリングラフィの手法と化学上、チン
グ法により容易に形成できる。このメサストライプ10
2が形成されたn−InP基板101 上に液相エピタ
キシャル法(LPE法)lc上ヨリp−1nP層103
、n−InPクラッド層104、発振波長1.3μmに
相当するノンドープIno72 Gao、zs A50
.6IP0.39  活性層105、p−InPクラッ
ド層106を順次積層させる。この際p−InP層10
3 はメサストライプ102の上面には成長しないよう
にする。このようなことは液相成長の特徴のひとつであ
り、メサストライプの側面の成長が速いためにメサ上面
付近ではP原子が少なくなり、溶液の過飽和度が小さく
なるために生じる。実際にはこのよう番こして素子を作
製したが、他ζこも例えばp−1nP層103を成長し
た後、過飽和度のきわめて小さな溶液を用い゛Cメサス
トライプ102の上面を軽くメルトバックするよっにす
ればメサ上面にもp−InP層103が積層した場合で
も所望の半導体ウェファが得られる。またそれぞれの半
導体層の厚さはn −InPクラッド層104は3 a
m 、 In O,72Gao2s ASo、61P0
39活性層105は0.15μm、 p−InPクラッ
ド層106は1μm程度である。次にこのようにして得
た半導体ウェファに第1図(2)に示した様にメサエッ
チングを行なう。この際2本の幅10μm1深さ3μm
程度のエツチング溝107,108およびそれらによっ
てはさまれるメサストライプ109を形成する。メサス
トライプ109は(011>方向に平行で、メサストラ
イプ109ははじめのメサ102の上部に位置するよう
lこする。このよ゛うにしてメサストライプ109を形
成した半導体ウェファに埋め込み成長を行ない所望のB
1−1−LDを得る。埋め込み成長lコおいてはp −
I nP 電流ブロック層110. n −InP電流
電流ブラフ111をいずれもメサストライプ109の上
面のみを除いて積層する。さらにp−InP埋め込み層
112、発光波長13μn1  に相当するp−Ino
7z Gao28AS0.61 Po、39電極層11
3を全面にわたって積層し、最後に電極形成を行なう。
This can be easily formed by ordinary photophosphorography techniques and chemical ching methods. This mesa stripe 10
On the n-InP substrate 101 on which 2 is formed, a p-1 nP layer 103 is formed by liquid phase epitaxial method (LPE method).
, n-InP cladding layer 104, non-doped Ino72 Gao, zs A50 corresponding to an oscillation wavelength of 1.3 μm
.. 6IP0.39 The active layer 105 and the p-InP cladding layer 106 are sequentially laminated. At this time, the p-InP layer 10
3 should not grow on the upper surface of the mesa stripe 102. This is one of the characteristics of liquid phase growth, and occurs because the side surfaces of the mesa stripe grow quickly, so there are fewer P atoms near the top surface of the mesa, and the degree of supersaturation of the solution becomes smaller. In practice, a device was fabricated in this manner, but for other devices, for example, after growing the p-1nP layer 103, the upper surface of the C mesa stripe 102 was lightly melted back using a solution with an extremely low degree of supersaturation. In this way, a desired semiconductor wafer can be obtained even if the p-InP layer 103 is also stacked on the upper surface of the mesa. The thickness of each semiconductor layer is 3 a for the n-InP cladding layer 104.
m, In O, 72Gao2s ASo, 61P0
The thickness of the 39 active layer 105 is 0.15 μm, and the thickness of the p-InP cladding layer 106 is about 1 μm. Next, the semiconductor wafer thus obtained is subjected to mesa etching as shown in FIG. 1(2). At this time, two pieces of width 10μm and depth 3μm
Etched grooves 107, 108 and a mesa stripe 109 sandwiched between them are formed. The mesa stripe 109 is parallel to the (011> direction, and the mesa stripe 109 is rubbed so that it is located above the first mesa 102.The semiconductor wafer on which the mesa stripe 109 has been formed in this way is buried and grown as desired. B of
1-1-LD is obtained. In the case of embedded growth, p −
InP current blocking layer 110. All n-InP current-current bluffs 111 are stacked except for the top surface of the mesa stripe 109. Furthermore, a p-InP buried layer 112, a p-InP layer corresponding to an emission wavelength of 13 μn1
7z Gao28AS0.61 Po, 39 electrode layer 11
3 is laminated over the entire surface, and finally electrodes are formed.

このようにして得たBH−LDにおいて室温でのCW発
振しきい値電流20 mA 、微分量子効率60チ、片
面からの光出力5QmW以上までI−L特性の直線性の
よい素子が再現性よく得られた。この第1の実施例にお
いては埋め込み成長段階で形成されるp−InP電流電
流ブタ22層110−InP電流電流ブラフ2層111
にあらかじめp−InP層103によって構成される電
流ブロック層構造を素子内部に形成した。これによって
BH−LDのもれ電流は大幅に減少し、大出力動作がき
わめて再現性よく得られるようになった。すなわち活性
層付近の電流ブロック層構造に対し、活性層よりも基板
側に電流ブロック層構造を形成したために大電流注入時
のもれ電流を大幅に減らすことができ、BH−LDの大
出力動作が可能となった。
The BH-LD obtained in this way has a CW oscillation threshold current of 20 mA at room temperature, a differential quantum efficiency of 60 cm, and an optical output from one side of 5 Q mW or more, resulting in a device with good linearity of the I-L characteristic with good reproducibility. Obtained. In this first embodiment, p-InP current current bluff 22 layers 110-InP current current bluff 2 layers 111 are formed in the buried growth stage.
A current blocking layer structure constituted by the p-InP layer 103 was previously formed inside the device. As a result, the leakage current of the BH-LD has been significantly reduced, and high output operation can now be achieved with extremely high reproducibility. In other words, with respect to the current blocking layer structure near the active layer, since the current blocking layer structure is formed closer to the substrate than the active layer, the leakage current when large current is injected can be significantly reduced, resulting in high output operation of BH-LD. became possible.

第2図は本発明の第2の実施例を示す。この場合、第1
の実施例と異なるのはp−InP層103をエピタキシ
ャル成長前に不純物拡散によって形成した点である。す
なわちn−1nP基板101上に選択的に不純物拡散を
行ないp−InP層103を形成した後に半導体多層膜
を積層させる。メサストライプ109は第1の実施例の
場合と同様にp−InP層103が形成された以外の部
分に形成する。第1の実施例においてはn−、InP基
板101上に形成した幅の広いメサストライプ102以
外に選択的にp−InP層103をエピタキシャル成長
させたわけだが、この第2の実施例においては選択拡散
法を用いたので、製造の容易さはさらに向上した。この
第2の実施例においても、活性層に対して、その両わき
のほかに、さらに基板内部に電流ブロック層構造を形成
したことによりBH−LDの大出力動作が容易に得られ
るようになった。この場合にも第1の実施例で示したの
と同程度の特性のBH−LDが歩留りよく得られた。
FIG. 2 shows a second embodiment of the invention. In this case, the first
This embodiment differs from the embodiment in that the p-InP layer 103 is formed by impurity diffusion before epitaxial growth. That is, after selectively diffusing impurities on the n-1nP substrate 101 to form the p-InP layer 103, a semiconductor multilayer film is laminated. Mesa stripes 109 are formed in areas other than where the p-InP layer 103 is formed, as in the first embodiment. In the first embodiment, the p-InP layer 103 was epitaxially grown selectively on areas other than the wide mesa stripe 102 formed on the n-InP substrate 101, but in the second embodiment, a selective diffusion method was used. The ease of manufacture was further improved. In this second embodiment as well, a current blocking layer structure is formed inside the substrate in addition to both sides of the active layer, making it easy to obtain high output operation of the BH-LD. Ta. In this case as well, a BH-LD with characteristics comparable to those shown in the first example was obtained with good yield.

なお、本発明の2つの実施例においては、いずれもIn
Pを基板とし、それに格子整合のとれたIn5−z G
as Asy Pl−1層を活性層とした波長1μm帯
の素子を示したが用いる半導体材料はもちろんこれに限
るものでなく、可視光領域の半導体材料、あるいは波長
2μm前後の波長領域の半導体材料であっても、もちろ
ん差しつかえない。半導体の導電型についてもn型基板
を用いたが、p型基板を用いて他の半導体層の導電型を
すべて逆転させてもよいし、さらに電流ブロック層はp
−n  接合による電流ブロック作用を基本構成したが
、i層あるいはアモルファス半導体層を電流ブロック層
として構成してもかまわない。実施例においては単純な
りH−LD構造を示したが、単一モード化LDとして回
折格子を用いたDFB−BH−LD、DBR−BH−L
Dlさらにモニタ用FD、 ドライバ用FET。
In addition, in the two embodiments of the present invention, both In
P as a substrate and In5-z G with lattice matching to it.
As Asy Although a device with a wavelength band of 1 μm is shown in which the active layer is an active layer, the semiconductor material used is of course not limited to this, and semiconductor materials in the visible light region or semiconductor materials in the wavelength region of around 2 μm can be used. Even if there is, of course it can't be ruled out. Regarding the conductivity type of the semiconductor, an n-type substrate was used, but a p-type substrate may be used to reverse the conductivity types of all other semiconductor layers, and the current blocking layer may be a p-type substrate.
Although the basic structure is based on a current blocking effect using a -n junction, an i-layer or an amorphous semiconductor layer may be used as a current blocking layer. In the example, a simple H-LD structure was shown, but DFB-BH-LD and DBR-BH-L using a diffraction grating as a single mode LD
DL, FD for monitor, and FET for driver.

トランジスタ等を複号化したBH−LDでも本発明は適
用できる。
The present invention can also be applied to a BH-LD in which transistors and the like are decoded.

本発明の特徴はBH−LDにおいて、活性層の両わき、
あるいはその周辺に形成された電流ブロック層の他に、
活性層よりもさらに基板に近い側に電流ブロック層構造
を形成したことである。これによって2重の電流ブロッ
ク層構造が形成されることになったわけで、特に大電流
注入時に活性層の両わきを流れるもれ電流が大幅に減少
した。したがってBH−LDの高出力動作が従来型と比
べてずっと容易になり、特性歩留りも向上した。
The feature of the present invention is that in the BH-LD, both sides of the active layer,
Or in addition to the current blocking layer formed around it,
The current blocking layer structure is formed on the side closer to the substrate than the active layer. This resulted in the formation of a double current blocking layer structure, which significantly reduced the leakage current flowing through both sides of the active layer, especially when a large current was injected. Therefore, high output operation of the BH-LD has become much easier than in the conventional type, and the characteristic yield has also improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例であるB1−1−LDの
製造工程を示すための概略図、第2図は第2の実施例で
あるBH−LDの断面図である。図中、101はn−I
nP基板、102はメサストライプ、103はp−In
P層、104はn−InPクラッド層、105はIno
、yz Gao、zs ASQ、61 Po、39 活
性層、106はp−InPクラッド層、107,108
はエツチング溝、109は活性層を含むメサストライプ
、110はp−1nPil;流プロ、り層、111はn
−1nP電流ブロック層、112はp−InP埋め込み
層、113はp−In0.72Gao2s ASo、6
1 Po、39 電極層をそれぞれあられす。
FIG. 1 is a schematic diagram showing the manufacturing process of B1-1-LD, which is the first embodiment of the present invention, and FIG. 2 is a sectional view of BH-LD, which is the second embodiment. In the figure, 101 is n-I
nP substrate, 102 is mesa stripe, 103 is p-In
P layer, 104 is n-InP cladding layer, 105 is Ino
, yz Gao, zs ASQ, 61 Po, 39 active layer, 106 is p-InP cladding layer, 107, 108
109 is an etched groove, 109 is a mesa stripe containing an active layer, 110 is a p-1nPil;
-1nP current blocking layer, 112 is p-InP buried layer, 113 is p-In0.72Gao2s ASo, 6
1 Po, 39 electrode layers respectively.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に少なくとも活性層を含む半導体多層膜を
積層させた多層膜構造半導体ウェファに、前記活性層よ
りも深く形成された2本の平行な溝によってはさまれた
メサストライプを形成した後埋め込み成長してなる埋め
込みへテロ構造半導体具なる導電型の半導体層が交互に
積層された電流ブロック構造を有することを特徴とする
埋め込みへテロ構造半導体レーザ。
A mesa stripe sandwiched between two parallel grooves formed deeper than the active layer is formed on a multilayer semiconductor wafer in which a semiconductor multilayer film including at least an active layer is laminated on a semiconductor substrate, and then buried. A buried heterostructure semiconductor laser having a current block structure in which conductive type semiconductor layers, which are grown buried heterostructure semiconductor layers, are alternately stacked.
JP11419082A 1982-07-01 1982-07-01 Semiconductor laser Pending JPS595690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11419082A JPS595690A (en) 1982-07-01 1982-07-01 Semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11419082A JPS595690A (en) 1982-07-01 1982-07-01 Semiconductor laser

Publications (1)

Publication Number Publication Date
JPS595690A true JPS595690A (en) 1984-01-12

Family

ID=14631448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11419082A Pending JPS595690A (en) 1982-07-01 1982-07-01 Semiconductor laser

Country Status (1)

Country Link
JP (1) JPS595690A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020241236A1 (en) * 2019-05-31 2020-12-03 住友電装株式会社 Wiring member

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020241236A1 (en) * 2019-05-31 2020-12-03 住友電装株式会社 Wiring member

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