JPS5957314A - Battery backup circuit of memory - Google Patents

Abstract

PURPOSE:To eliminate the need for a memory exclusive use for data storage by only connecting a battery via a connector so as to attain backup in an information processor. CONSTITUTION:When a system power supply is turned off, a Zener diode ZD is turned off, transistors TR2, TR1 are turned off, and the +5V side of the system power supply and the Vcc side of a C-MOS memory 1 are opened. When the battery B is connected, a voltage of the battery B is applied to the terminal Vcc of the memory 1, and a voltage required for backup is kept. A selecting terminal CS1 of the memory 1 is pulled up to a backup voltage at the same time, and the memory content is kept. When a battery detecting signal is at a GND level, a CPU circuit for the system performs required processing by regarding it as the backup state at the battery.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to data retention, and makes it possible to connect a battery for backup to a memory.
In the case of i, S, the memory is packed up with a battery so that the data contents can be retained even when the system's power is turned off, and the status is notified to the signal system. This invention relates to battery backup circuits for memory.

[Conventional technology and problems]

In information processing equipment, there are 8+1 benefits of retaining data set by the operator or data set by the host even when the power is turned off. Such data includes, for example, printer format settings. To store relatively small amounts of data such as those for printers, it is generally recommended to set up a C-MOS dedicated to data storage, separate from the area normally used by the system, and back it up with a battery such as a Niracad battery. Widely used. However, in a device that uses only IK or 2 (1) memory in total, the data capacity that you want to store is usually around 200 to 300 bytes at most, and a special Providing memory is disadvantageous in terms of implementation cost.Also, there are cases where the user does not need to retain data, and even in such cases, equipment with a backup circuit is required. However, since data retention was not essential, equipment without a puncture circuit was used, but later it became necessary to retain data. In such cases, the problem arises that it is not possible to retain data using the same device.

[Purpose of the invention]

The present invention solves the above-mentioned problems, and by connecting a battery, data can be retained in the quantity rate.
It is an object of the present invention to provide a memory battery backup circuit that does not require a memory dedicated to data retention.

[Fourth feature of the invention] For this reason, the battery backup circuit of the memory of the present invention maintains the data stored in the memory using the battery power even if one supply of the system electric bullet is cut off. A memory battery backup circuit that has become possible has a first switching means connected in the Mj column between the system power supply and the memory, and a voltage detection element, and detects the entire voltage of the system power supply. It is equipped with an 8g2 switching means that turns on when system power is supplied, and a connector, and the input side and the output side of the connector are configured to be detachable, and the input side has a first terminal and a second terminal.
A battery is connected to the terminal, a third terminal is connected to the second terminal, and on the output side, the first terminal is connected to the first switching means and the power supply terminal of the memory via the first resistor. A second terminal is connected to a common power supply connection line between the system power supply and the memory power supply terminal, and a third terminal is connected to the first switching means and the system power supply through a second resistor. The second switching means is connected to the connection line of and is configured to be sent to the system side as a potential gold battery detection signal at the connection point between the third terminal on the output side and the second resistor. On the condition that the system power is supplied, the first switching means is turned on and the chip select terminal of the memory is set to low level, and on the condition that the system power is not supplied, the first switching means is turned on. The special feature is that the switching means is turned off and the chip select terminal of the memory is brought to the level of connection between the first switching means and the power supply terminal of the memory.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to Figure Bni.

Figure 1 is a diagram showing one embodiment of the present invention, Figure 2 is a diagram showing the flow of processing by the system CPU when the system power is turned on. FIG. 4 is a diagram showing an outline of a first system to which the present invention is applied, and FIG. 4 is a diagram showing a specific example of a system to which the present invention is applied. In the figure, l is C-MO
S memory, 2t, 1 connector.

3 is the host, 4 is the interface section, 5t, ↓ Mecha.
Control section, 6 r, t pudding mechanism section is shown.

The present invention does not use a C-MOS memory dedicated to data retention, and enables switching between data retention and non-retention depending on whether or not a battery is connected. Figure 1 shows a circuit using all 2-byte C-MOS memory 1 (type with 2 chip selects) according to the present invention.
This is shown as an example. In Fig. 1, the system power supply has its +5V side connected to the VCC of the C-MOS memory l through the emitter-collector of the transistor TR1.
connected to the terminal, and the GND (ground) side is C-MOS
Connected to the VSS terminal of memory 1. Also, there is a Zener diode Z between the system power supply -1-5V and GND.
l) (3 to 4 V) and a series circuit of resistor 1 (2 and R3 is connected, and the 1a column connection point of resistor It 2 and R3 is connected to the base of transistor l' R2. transistor i' LL 2 ) :l vktali, c-h
It is connected to the chip select terminal C5I of the as memory 1, and also connected to the transistor 1'R through the resistor iX14.
1 and connected to the base of resistor 115? ! - to the collector of the transistor TI'LI and to the trunk. The input side of the terminal ■ of the connector 2 is connected to the positive terminal of the batch 171'3, and the output side is connected to the resistor R6.
connected to the VCC terminal of C-MOS memory 1 via
The input sides of terminals ■ and ■ are connected to the negative terminal of batch IJ B, and the output side of terminal (lol) is connected to the system power supply G N I
) side, and the output side of the terminal (2) is connected to the +5V side of the system power supply via a resistor 1tl, and is also connected to the CPU path of the system. AO of C-MOS memory 1
or AIO indicates an address terminal, and DO or D
? indicates a data terminal. These terminals are the system's CP
J is connected to the address bus and data bus of the 0 circuit. Further, C82 of the IOS system 1 is a chip select terminal and an R/W 1/2 write terminal, and these terminals are also connected to the CP0 circuit of the system. C-
The MOS memory has a +5V power applied between VCC and VS2, and can be read/written by the CPU when chip select terminals C81 and C82 are at low level, and when chip select terminals C'-81 and C82 are at high level. At this time, it is not possible to read/write from CI"U, and the data is held in the status mode.Next, I will explain the status of tI! + operation (i7).When the system power supply is connected, The base IIi current is supplied to the transistor 'l'' 112, turning on the transistor 'rIt2.As a result, the base' current is also supplied to the transistor TR1, and the transistor i'l(1 is also turned on, and C- MOS memo 1〕1
Power is supplied from the 111C system power supply. At this time, one of the C-MOS memory selectors C81 turns on the transistor i''It2 (therefore it becomes low level).The system power supply 75≦turns off.

At that time, Zener die,, 4-- )' Z l
) power ball mef (ζ to r, transistor'a (2 also T)
R1 is also off (/(, so the system f system 1iij@ノ+
5 V (III C-MOS Memo') 1 terminal V
ccillll (Tsukutsuku7so7°(III) Tol
t: becomes ;4--7'7 state. Here nokunona January 3 /Js m 4<:1-SaJt te 0 ro case +, 1
．． (January 3rd) Army, I: I Mika Ball Resistance R6, C-MOS Memo IJ 1 Noyii Ako VCC
ItC4JkM4 is maintained at the voltage required for pull-up.At the same time, one chip of C-MOS memory 1 is
The select terminal C8I is pulled up to the backup voltage and the memory contents are retained. When the chip select terminal is at the high level, the C-MOS memory 1 cannot be read or written and is in standby mode, but when the chip select terminal is at the low level, it can be read or written. The connection point between terminal Q) of connector 2 and resistor 1 (1 is
When the battery 13 is disconnected and the battery 13 is not connected, the voltage is 1.5μ of the system power supply, but the voltage of the connector 2
When B is connected, it is always at G N I) level. So, &:j in the CPUH path of the system.

The field at this point is detected as the battery detection Id number, and when the battery detection signal is at the (3ND level), it is assumed that the battery is backed up and necessary processing can be performed.

I will explain the flow of processing carried out by the CPU of the system when the system's CPU is turned on, referring to Part I.

■ Look at the battery detection signal and check whether the battery is turned on.

In the case of Yes, the entire process of ■ is performed, and in the case of No, the process of ■ is performed.

(Performs a checksum of the young format data section. Next, performs the processing in (>).

(Check whether the contents of the format data section are OK or not as a result of the checksum.

If YES, process e''-■ is performed, and if NO, process KE is performed.

(Reformats the data saved in the format data section.

■ Clear Wt in the format data section.

An overview of the configuration of the printer device to which the present invention is applied is provided in Part 3.
As shown in the figure, it is divided into an interface section 4, a mechanical control section 5, and a printer mechanism section 6. host 3
The data that is sent is decoded by the interface section 4, and necessary control signals are sent to the mechanical control section 5. The mechanical control section 5 controls the printer@structure section 6 in order to cause the printer to operate in accordance with the control signals. In the printer device configured as described above, the battery bank amplifier according to the present invention is required in the interface section 4, in order to save printer type and setting data. Printer name (car) λ-Mat and 1 to 1, for example, setting the tab position to specify the position in advance to move to the gear ridge according to the form of the paper, and printing to match the width of the paper. , the space that limits the left and right printing positions.
These include margin settings, page length settings, type of print media, and settings for messages sent to the host. All of these formats are more reconfigurable for command data from the host. To save the host the process of initializing these formats each time the power is turned on, the format data should be saved while the power is turned off. It is necessary to

FIG. 4 shows a more specific configuration example of a printer device to which the present invention is applied. In FIG. 4, 7 is an operator panel, 8 is a power supply, 9) is a microprocessor, 10 is a display, and 11 is a RAM.

12 is the print wheel control processor? , 13 is a gear carriage control processor, 14 is a paper feed control processor, 15 is a print wheel servo circuit, 16 is a carriage servo circuit, 17 to 23t driver, 2
4 is print wheel motor, 25ri7' lint wheel transducer" 1.26 & Yuhamma, 2
7 is a shift motor.

28 is a ribbon lift magnet, 29 is a carriage motor, 30 is a carriage transducer, 31
32 indicates a ribbon feed motor, 32 paper feed motors, and 33 to 35 sensors. Power supply 8 is interface part 4
It supplies power to the mechanical control section. The interface section 4 includes a microprocessor 9 for controlling the interface, a display 10 for displaying power-on and error messages on the front panel of the printer, and a RAM.
II is provided. Since format data is stored in RAM II, a battery backup circuit according to the present invention (FIG. 1) is provided for rtAMll, and the microprocessor 9 performs processing as shown in FIG. Print wheel tbl↓ control processor 12 of mechanical control section 5 controls print wheel motor 24 through print wheel servo circuit 15 and driver 17 to control print wheel angle 12, type 'fr, Select, drive the hammer 26 all the way through the drive 8, and print.
The motor 26 is operated at 71,14 ihl+ depending on which side of the print wheel is selected, and the ribbon lift magnet 28 is operated according to the color of the ribbon. It is excited when printing is done by changing the position. The gear ridge control processor 13t controls the carriage motor 29 through the entire gear ridge servo circuit 16 and driver 21. Print]...The wheel servo circuit 15 is the print wheel-1-
The printer 25 drives the print wheel motor 24 through the driver 17 so that the print wheel angle is the specified angle from the print wheel control processor 12 based on the print wheel angle signal. be. Similarly, the gear carriage servo circuit 16 drives the carriage motor 29 based on the carriage space 8 movement signal from the carriage transducer 30 so that the movement of the carriage matches the command from the carriage control microprocessor 13. It is something to do. The paper feed control blower 14 includes a driver 22
The ribbon feeding motor 31 is controlled through the driver 23, and the paper feeding motor 32 is controlled through the entire driver 23.
The sensors 33 to 35 detect each car state signal of the printer mechanism 6, such as end of ribbon, paper out, cover open, etc., and perform error monitoring.

〔Effect of the invention〕

As explained above, according to the present invention,
Backup can be performed simply by connecting the Vanoderi via a connector, and a memory system that does not require memory for data storage can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing the flow of processing by the system CPU when the system power is turned on, and FIG. 3 is a diagram showing an overview of the system to which the present invention is applied.
FIG. 4 is a diagram showing a specific example of a system to which the present invention is applied. 1... C-MOS memory, 2... Connector, 3...
- Host, 4... Interface section, 5... Mechanical control section, 6... Printer mechanism section, 7...
Operator panel, 8...Power supply, 9...Microprocessor, 10...Display unit, 11...RAM, 1
2... Print wheel control prosensor, 13...
- Carriage control processor, 14... Paper feed control processor, 15... Print wheel servo circuit, 16... Carriage servo circuit, 17 to 2
3... Driver, 24... Print wheel motor, 25... Print-wheel transformer, 26... Hammer, 27... Shift motor, 2
8... Ribbon lift magnet, 29... Carriage motor, 30... Carriage transuser, 31... Ribbon feed motor, 32... Paper feed motor, 33... 1235... Sensor . Patent Applicant: Fujitsu Limited Representative Patent Attorney Kyotani Shibu 1 JP Pu 2 Zuzai 31 Power

Claims (1)

[Claims] 19 A memory battery backup circuit capable of retaining data stored in a memory in a battery power supply even when the system power supply is cut off,
The first
a second switching means having a voltage detection element to detect the voltage of the system power supply and turn on when the system power supply is L (L), and a connector, the connector having an input side and an output side. A battery is connected to the ?A1 terminal and the second terminal on the input side, the third terminal is connected to the second terminal, and the first terminal is connected to the output side. fits over the first resistor
connected to the connection line between the switching means of "i jA" and the power supply terminal of the memory, the 20th terminal is connected to the common power supply connection line between the system power supply and the power supply terminal of the memory,
A third terminal is connected to the connection line between the first switching means and the system power supply via a second resistor, and the potential at the connection point between the third terminal on the output side and the second resistor is connected to the battery. To be sent to the system side as a detection signal +
: M l+, and the switching means of upper HQ t2 is set to upper HQ on the condition that system power is supplied.
The switching means with id<1 is turned on and the chip select terminal of the memory is set to low level, and on the condition that the system power is not supplied, the first switching means is turned off and the chip select terminal of the memory is set to low level. 1. A battery backup circuit for a memory, characterized in that the connection line between the first switching means and the power supply terminal of the memory is level-matched.