JPS5957366A

JPS5957366A - Pattern inspecting method

Info

Publication number: JPS5957366A
Application number: JP57167504A
Authority: JP
Inventors: Giichi Kakigi; 柿木　義一; Kikuo Mita; 三田　喜久夫; Moritoshi Ando; 護俊安藤; Akifumi Muto; 明文武藤; Kazuo Yagi; 一夫八木
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1982-09-28
Filing date: 1982-09-28
Publication date: 1984-04-02

Abstract

PURPOSE:To increase accuracy of pattern inspection by providing two or more sensors that scan a pattern in two directions perpendicular to each other in parallel and judging whether continuous number of logical 0 output of each sensor is within specified limit or not. CONSTITUTION:A pattern is scanned by sensors parallel to two directions perpendiucular to each other. The number of logical 0 output A-D is supplied to subtracters 10, 12 to calculate ¦A-B¦, ¦C-D¦, and these are inputted to comparators 20, 21. When any defect is in the pattern, comparators 20, 21 satisfy the expression 1 and output logic 1 to AND gate. A-D are inputted to an upper limit comparator U and a lower limit comparator L. When there is defect that does not satisfy the expression 2, U and L output logic 0 to NAND gate 40, and the gate 40 outputs logic 1. Outputs of gates 30, 40 are inputted to AND gate 50, and when there is defect in the pattern, logic 1 is outputted from the gate 50.

Description

【発明の詳細な説明】（１）　　発明の技術分野本発明はパターン検に方式、時に光学的に検知したパタ
ーンを記憶装置に蓄え、該パターンが正常か異常か全検
査する方式に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a pattern detection method, and sometimes to a method in which optically detected patterns are stored in a storage device and the patterns are fully inspected to see if they are normal or abnormal.

（２）　　従来技術と問題点現在、パターン検査方法が各種開発されているが、検査
対象であるパターンが増々多様化して来ている。(2) Prior Art and Problems Currently, various pattern inspection methods are being developed, but the patterns to be inspected are becoming increasingly diverse.

このような多様化したパターンに対して、従来の単純な
パターンに採用されてぃ／こ倹食方法を採用したのでは
正置′なパターンをも欠陥のあるパターンとみなして誤
動作をするという問題点があった。For such diversified patterns, if we adopt the traditional method of feeding simple patterns, we will have the problem that even correct patterns will be treated as defective patterns and malfunctions will occur. There was a point.

即ち従来の検査方法はいわば十字形方法であって、第１
図（１）に示すようにＸ方向とｙ方向に連続する論理「
ｏ」の数を計測し、「ｏ」の数が特定の範囲α＜Ｘ＜β
　γ＜ｙ＜δにあれば該パターンは正常であると判定し
ていた。しかしこの十字形検査方法によると、第１図（
２）に示すように、Ｌ形のパターンＰを検査する場合に
、全体としてｒよ正常であるにもかかわらず縁部の微小
な四部りにおいても、方向ｌにおける論理１０」の数は
止冨範囲を越えていると判断しこのパターンＰは欠陥で
あるとみなしてし゛まう。That is, the conventional inspection method is a so-called cross-shaped method, and the first
As shown in Figure (1), the logic “
The number of "o" is measured, and the number of "o" is within a certain range α<X<β
If γ<y<δ, the pattern was determined to be normal. However, according to this cross-shaped inspection method, Figure 1 (
As shown in 2), when inspecting an L-shaped pattern P, even though it is normal as a whole, the number of logical 10's in the direction l reaches a limit even in the four minute edges. It is determined that the range is exceeded, and this pattern P is considered to be a defect.

（３）発明の目的本発明の目的は、パターン検査を井形に行うことにより
、多様化したパターンを正確に検査し正常なパターンを
欠陥とする誤動作を防止することにある。(3) Purpose of the Invention The purpose of the present invention is to accurately test diversified patterns by performing pattern inspection in a rectangular pattern, and to prevent malfunctions in which normal patterns become defects.

（４）発明のｌ１成本発明によれば記憶装置ｋに蓄えられたパターンを互い
に垂直な２つの方向に走査するセンサにより検査するパ
ターン検査方法において、上記２方向に平行に走査する
センサを各方向にそれぞれ少なくとも２つ設けて各セン
サによって論理「０」が連続している故を計測し、同方
向のセンサの論理「０」の数の差が所定の値以下の場合
に２方向の各センナの論理「０」の数が所定の上限値以
下であり、かつ下限値以上であるか否かによりパターン
に欠陥があるか否かを検査することｉｗ徴とするパター
ン検査方法が提供される。(4) According to the present invention, in a pattern inspection method in which a pattern stored in a storage device k is inspected using a sensor that scans in two mutually perpendicular directions, a sensor that scans parallel to the two directions is used in each direction. At least two sensors are provided in each direction, and each sensor is used to measure the reason why logic "0" is consecutive. A pattern inspection method is provided in which whether or not a pattern has a defect is inspected based on whether or not the number of logic "0"s is less than a predetermined upper limit value and greater than a predetermined lower limit value.

（５）発明の実施例以下、本発明を実施例により添付図面を参照して説明す
る。(5) Embodiments of the Invention The present invention will now be described by way of embodiments with reference to the accompanying drawings.

第２図は本発明に係るパターン検査方法の概念図であり
、Ａ、Ｂ、Ｃ，Ｄはそれぞれセンサで計測される論理「
ＯＪＯ数である。FIG. 2 is a conceptual diagram of the pattern inspection method according to the present invention, where A, B, C, and D are the logic values measured by the sensor, respectively.
This is the number of OJOs.

Ａ、Ｂ、Ｃ，Ｄについて次の（１）式の条件が満足され
かつ（２）式の条件が満足しないとき、検査対象である
パターンに欠陥がある。When the condition of equation (1) below is satisfied for A, B, C, and D, but the condition of equation (2) below is not satisfied, there is a defect in the pattern to be inspected.

ＩＡ−Ｂｌ≦αかつＩｃ−ＤＩ≦α　　・・・・・・（
１）上記（１）（２）式を内容とする本発明方法を実施
するための回路構成図を第３図に示す。IA-Bl≦α and Ic-DI≦α ・・・・・・(
1) FIG. 3 shows a circuit configuration diagram for implementing the method of the present invention having the above formulas (1) and (2) as contents.

減痒器ｔｏ、ｉｔはそれぞれＩＡ−Ｂ１．ＩＣ−ＤＩを
計算する。比較器２０．２１はそれぞれＩＡ−８１とα
Ｉｃ−ＤＩと（χとを比較する。′また第１アンドゲー
ト３０は上記（１）式が満足されるか否か判断する。そ
して各上限比較器Ｕと下限比較器りはＡ、Ｂ、Ｃ，Ｄが
（２）代金それぞれ満足するか否かを判のテする。最後
の第２アンドゲート５０はｈ　ｉｉ’ｒ　ｍ　＊　＜２
）式共にン角足されるか否かを判断する○ 次に上記回路の動作全説明する。The antipruritic devices to and it are respectively IA-B1. Calculate IC-DI. Comparators 20 and 21 are IA-81 and α, respectively.
Ic-DI and (χ are compared.' Also, the first AND gate 30 judges whether the above equation (1) is satisfied.The upper limit comparators U and lower limit comparators A, B, Check whether C and D satisfy (2) each price.The final second AND gate 50 is h ii'r m * <2
) to determine whether the angles are added together. Next, the entire operation of the above circuit will be explained.

各センサで８１側された論理「０」の数は各減算器ｔｏ
、ｉｔに供給されＩＡ−Ｂ１．ＩＣ−ＤＩがＲＨＷされ
る。この計算は比較器２０．２１に入力される。ＩＡ−
Ｂｌ≦α、ＩＣ−１）ｌ≦（ｔのｊ烏合にＶｉｉｉｌｉ
ｉｉ理「ｌ」が出力され・それぞれ第１アンドゲート３
０に入力される０人力が共に：ｒＩＪである、即ち（１
）式を満たすので論理「１」の出力は第２アントゲ−１
・５０に供給される。The number of logical "0"s placed on the 81 side in each sensor is determined by each subtractor to
, it is supplied to IA-B1. IC-DI is RHWed. This calculation is input to comparator 20.21. IA-
Bl≦α, IC-1)l≦(t)
ii logic “l” is output and the first AND gate 3 respectively
The 0 human power input to 0 is both:rIJ, that is, (1
) satisfies the formula, so the output of logic "1" is the second ant game -1
・Supplied to 50.

一方、Ａ、　！己、Ｃ，Ｄの値は上限比較器Ｕ、丁眠比
較器ｆ７に入りされ、欠陥のあるとき即ち（２）式がＷ
％足されないときはＵ、Ｌの出力は論理「０」となりナ
ンドゲ−１・４０で反転されて論理１１」がル２アンド
ゲート５０へ入力される。On the other hand, A! The values of self, C, and D are entered into the upper limit comparator U and the sleep comparator f7, and when there is a defect, that is, the equation (2) is
When the percentage is not added, the outputs of U and L become logic "0", which is inverted by the NAND gate 1.40, and the logic "11" is input to the NAND gate 50.

従ってに１シ２ア：／トゲー１−５０は、パターンに欠
（慟があるとき、論１．；ｄ　ｌ’　Ｉ　Ｊ　ｆ出力す
る。Therefore, 1S2A:/Toge1-50 outputs logic 1.;d l' I J f when there is a deficiency in the pattern.

（６）発明の効果本発明によれば、渠４図に示す如くＡとＢの差が大きい
場合ニ（１）式を満足せず正常パターンと判断するよう
に、複雑なパターンでも誤動作゛すること々く、パター
ン検ｆ：精１ｙが向−トする。(6) Effects of the Invention According to the present invention, even complex patterns can malfunction, such as when the difference between A and B is large as shown in Figure 4, Equation 2 (1) is not satisfied and the pattern is determined to be normal. Often, pattern detection f: precision 1y is directed.

[Brief explanation of the drawing]

第１図は従来技術の説明図、第２図は本発明に係るパタ
ーン検査方法の概念図、稟３図は第２図の方法を実施す
るための回路構成図、＠４図は本発明の効果説明図であ
る。１０．１１・・・・・・減算器、２０．２１・・・・・
・比較器、３０・・・・・・第１アンドゲート、４ｏ・
旧・・ナントゲート、５０・・・・・・第２了ンドゲー
ト。！階軒出願人富士通株式会に１：特許出願代理人弁理士　背　木　　　　朗弁理士　西　舘　和　之弁理士　内　１）幸　男弁理士　山　口　昭　之！’、’５１　１乎１３１′・ｊ：：’、　４１　＋Fig. 1 is an explanatory diagram of the prior art, Fig. 2 is a conceptual diagram of the pattern inspection method according to the present invention, Fig. 3 is a circuit configuration diagram for implementing the method of Fig. 2, and Fig. It is an effect explanatory diagram. 10.11... Subtractor, 20.21...
・Comparator, 30... 1st AND gate, 4o・
Old... Nantes Gate, 50... Second End Gate. ! To Kaiken applicant Fujitsu Limited 1: Patent application agent Akira Seki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yuki male patent attorney Akira Yamaguchi! ', '51 1 乎1 31'・j ::', 41 +

Claims

[Claims]

In a pattern inspection method in which a pattern stored in a storage device is inspected by a sensor that scans in two directions perpendicular to each other, at least two sensors f scanning in parallel to the two directions are provided in each direction. The number of consecutive logic "0"s is measured by each sensor, and if the difference in the number of logic "0"s of the sensors in the same direction is less than a predetermined value, the logic "0" of each sensor in the two directions is counted. 1. A pattern inspection method, comprising: inspecting whether or not there is a defect in a shiba turn by determining whether or not the number is below a predetermined upper limit value and above a lower 1 (fl value).