JPS5958580A - Masked vector arithmetic processing unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an apparatus for calculating vector data at high speed.

[Prior art]

In order to achieve faster processing by a vector processor, it is a challenge to enable the vector processor to process more types of processing at higher speed. Among them, FOR
In order to process a DO loop containing an IF statement at high speed in a TRAN program, it is said that a more advanced processing device is required. This will be explained using FIG.

In the DO loop shown in Figure 1, the value of the result of the logical product 9 as shown in equation (1) is "door", and the logical operation result shown in equation (2) is "true". or the corresponding index value: Expression (3) is added and substituted between elements with index values such that either expression (1) or expression (2) does not hold. 3)
Additions and substitutions are not made. Such processing is repeated for N sets of elements.

In Figure 2, the number of elements 2N is 6, and the operand A (1
-6), B (1-6), C (1-6).

This figure shows the flow of data when the calculations shown in FIG. 1 are performed assuming appropriate values for D (1 to 6), F' (1 to 6), and G (1 to 6).

In Figure 2, the value ゛X# is not changed by these processes,
It also indicates that it is not involved in this process.

The processing procedure is shown below.

Step 1: Operands A (1-6) and B (1-6)
A vector mask: VM (1 to 6) is created by comparing the corresponding niremen. In this case, when the values of both corresponding elements match and the logical operation result is "true", the VM has the value at 1py, and when they do not match, the VMK has the value It 071. In the example, the values of VM (1-6) are 0, 1, 0, 1, respectively.
, 1°0.

Step 2: In the next step 3, vector mask: V
In order to use the vector mask register storing M for writing again, the contents of VM (1 to 6) are saved to another register SR,1.

Note that this SR,1 is not a register dedicated to vector masks, and can only process all elements of held data at once. Therefore, this step
This is performed after Step 1 is completed.

Step 3: Similar to step (1), equation (2
) and write the result to VM (1 to 6).

Again, the value ``t1n'' for the logical operation value ``true''.

If we associate the value at O with “false”, in this case (7) VM (the values 1 to 6 are 0, 1, 1°1, respectively)
．． It becomes 0.1.

Step 4: In the next step 5, in order to perform logical operations between general-purpose registers using a general-purpose arithmetic unit that can only process all elements at once, the value of 7M (1 to 6) is stored in general-purpose register SR2. evacuate. This step is also performed after step 3 is completed for the same reason as step 2.

Step 5: Find the logical product of SRI and SR, every 20 bits, on SR,3. This step is performed after step 4 is completed.

Step 6: VM(
1 to 6).

Step 7: Based on the value of VM (1 to 6) obtained in Step 6, addition and substitution shown in equation (3) in FIG. 1 are performed. At this time, the result of the calculation is invalidated for elements whose corresponding vector mask VM(I) has a value of 0''.

That is, the value of E(1) at that time is not changed. In this example, the operation is performed such that the calculation results for only the second and fourth elements change the value of E(1) in the main memory.

The state of the above processing is shown in the time chart of FIG.

The vertical axis of the time chart indicates each step, and the horizontal axis indicates time. Each number indicates the first cycle of processing for that element number, and the time lag between steps indicates the start-up time lag.

As mentioned above, in the conventional technology, processing of DO loops including complex conditional statements in the vector processor has only one vector mask register. Conditional arithmetic processing cannot be performed unless the arithmetic processing is performed and the final vector mask created is transferred to the vector mask register again. Therefore, as shown in Figure 3, in the conventional technology, vector processing is divided into three processing time periods: step 1, step 3, and step 7, and processing cannot be parallelized or accelerated between these steps. There was a problem.

In general, vector processors achieve high speed by processing different elements of multiple vector operations in parallel, but steps 2, 4, 5.6
Since the processing is not suitable for a vector processor, it is difficult to process steps 1.about.3.7 in parallel as shown in FIG.

[Purpose of the invention]

An object of the present invention is to provide a vector arithmetic processing device that can perform vector mask generation, vector mask arithmetic processing, and conditional vector arithmetic processing all in parallel.

[Summary of the invention]

Therefore, in the device according to the present invention, (1) a plurality of registers dedicated to vector masks that can be simultaneously written to and read from;

(2) One or more vector mask-dedicated arithmetic units that calculate a new vector mask value by inputting data in a vector mask-dedicated register.

(3) Means for synchronizing writing of the vector mask and reading to the vector mask dedicated arithmetic unit.

(4) Means for synchronizing writing of the vector mask and reading to the masked vector arithmetic processing arithmetic unit.

By newly providing these, it is possible to process vector mask generation, inter-vector mask calculations, and nine conditional vector calculation processes all at the same time.

However, in this specification, the term "arithmetic processing" refers to
It refers to all operations such as main memory references, operations such as addition and subtraction between vectors, and storage of the results in the main memory.In the embodiment of this specification 1, masked main memory storage will be taken as an example.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to examples. Fifth
The figure shows an embodiment of the invention.

It is assumed that the device parts not directly related to the present invention have the same configuration as a normal vector processor, and the description of those parts will be kept simple.

In FIG. 5, 101 is a main memory device, 102 is a main memory control device, 103 is a scalar processing device, 104U is a part of the scalar instruction control device, and 105 is a vector instruction control device.

The scalar instruction control device 104 decodes the instructions sequentially read from the main memory device 101 via the main memory control device 102 and the signal line 201. If this is a normal scalar instruction, the scalar processing device 103 Arithmetic processing is performed and the results are written to the main storage device 101 via the signal line 202. If the instruction decoded by the scalar instruction control device 104 is an instruction to start a vector instruction sequence, the signal line 20
3, the start address of the vector instruction sequence on the main storage device 101, the number of vector elements to be processed,
The activation signal is passed to the vector instruction control device 105. Subsequently, the vector instruction control device 105 reads the petator instruction string from the main memory 101 via the signal lines 201 and 204 in accordance with the given address, decodes the vector instruction, and stores the registers specified in the instruction. arithmetic unit,
The commands 75) which determined that the memo 1, 1, etc. are in a usable state, signal lines 205, 206, and 20, respectively.
7 to activate the resources necessary for the instruction, and at the same time, start the resources necessary for the instruction via
Transfer Wandering 1 + Aoho. The vector register control device 110 or the vector mask register control device 120 sends out processing for each vector instruction.

The process proceeds according to the permission signal for processing for each element.

Below, the Do roof shown in Figure 1 is shown.

The execution of a vector instruction according to the present invention will be explained by taking as an example the case where processing is performed. In this example, a buffer storage called a vector register is used, and a series of data each consisting of N elements, A (1 to N), B (1 to N), C
(1-N), D (1-N), E (1-N), G (1-N
) must be stored in the vector registers 111-116, respectively, via the signal lines 211-2167.
5: Processing during this period follows processing by a normal vector processor.

To execute the process shown in Figure 1, in addition to the six instructions that perform the above process, A(I) and B(I) are compared element by element,
A seventh instruction that writes the comparison result to the vector mask register. The eighth instruction writes the result of the element-by-element comparison of the values of C(I) and D(I) to a different master register than the one written in the seventh instruction. A ninth instruction that performs a logical operation between the two vector masks obtained by the seventh and eighth instructions and writes the result to the third vector mask register. F
A 10th instruction that adds (I) and G(I) element by element and stores the result in a vector register, and a vector mask that uses the addition result obtained by the 10th instruction and a vector mask obtained by the 9th instruction. only if takes to 1n (or
0″′), an eleventh instruction is used which writes to the memory address corresponding to E(I).

The processing shown in FIG. 1 will be explained below using FIG. 5.

In response to the seventh instruction, the vector instruction control device sends the values in the vector registers 111 and 112 to the arithmetic unit 131, and compares the expressions (υ). In this case, if the relationship of equality is established, , the value PA1'' is written, and if the value II0++ is not established, the value II0++ is written to the vector mask register 122 via the signal line 231.This comparison operation can be performed in one cycle by using a pipeline arithmetic unit in the signal line 231. can be advanced at a pitch of one element.

The eighth instruction similarly compares Equation (2), and if it is true, it is 61'', and if it is not true, it is It07+, which is sent from the pipeline arithmetic unit 132 to the vector mask register 123 via the signal line 232. Blinded by.

Between the values written in 122 and 123, a logical AND operation is performed according to the ninth instruction.

This uses vector mask registers 121 to 123 and a dedicated pipeline arithmetic unit 141 instead of registers and arithmetic units that can only perform batch processing as described in the prior art, so that the necessary data can be The elements that have been completed are synchronized so that the logical product processing is immediately performed.

Also, the value of the vector mask created by the ninth instruction is
When referenced by the eleventh instruction, data to be stored in memory and elements whose vector masks are complete are synchronized so that processing is performed immediately.

The former synchronization mechanism between vector mask registers will be explained with reference to FIG. 6, and the latter synchronization mechanism between vector mask registers and vector registers will be explained with reference to FIG. 7, taking conditional vector operations as an example.

7th. The value of the vector mask register written by the 8th instruction can be read from any point as long as writing has been completed for all elements, but if an element in the middle is being written, the value before writing is read. If so, the process shown in FIG. 1 will not be executed correctly. For the purpose of knowing this written range, for example, the vector mask register 12 is read out to take the logical product after writing the comparison operation result.
2 (hereinafter referred to as VMR2), an up/down counter 322 that stores how much the number of written elements exceeds the number of read elements, and a register that stores the status of writing or reading. Prepare 321.

Permission signal 404 for reading one element from VMR2
For example, it is issued when the VMR2 is not being written, or when it is being written but the element to be read from now has already been written. Since the counter 322 holds the difference obtained by subtracting the number of read elements (or the number of planned read elements) from the number of write elements, the signal 401 and VR4R2 indicating that the value of this counter is positive is in progress and read. A signal 402 indicating that the VM is inside
An AND circuit 323 and an OR circuit 3 are connected to a signal 403 indicating that R2 is not in a writing state and is in a simple read state.
A signal 404 can be obtained by taking the logic of 24.

Also, it is possible to perform calculations between VMR,2 and the vector mask register 123 (hereinafter referred to as VM L3), V
This is limited to the case where both MR2 and VMR3 have permission signals for reading one element.

The 1-element operation permission signal 406 is the 1-element read permission signal 404 of the VMR2 and the VMR.

AND circuit 3 of 1 element read permission signal 405 of 3.
#) can be obtained by ANDing with 01. This one
V11V12 by element operation permission signal 406
1 is added to the value of the read address 302 of and 3, and if the value of the counter 303 storing the number of unprocessed elements is not 1, it is subtracted by 1 and the process proceeds to the next element. This logical product operation is performed at each stage of the pipeline operator 141.
11 to 1413, the vector mask register 121
(hereinafter referred to as VMR1). At this time, the data processing is synchronized by appropriately adding the writing side address 304, addition fd to the up/down counter 312, and synchronous flip-flops shown in 306 to 307. In order to read the element data written to VMR1 at the same time as writing, if necessary, the time difference between when the up/down counter 312 is incremented by +1 and when the data is actually written to 122 is determined by up/down/
It is necessary to design the time difference to be equal to the time difference between when the color/read 312 operation is performed and when reading is performed. In this example, the signal 407 bypasses the flip-flop group 307 and is sent to the up/down counter 312.
is being sent to. The transmission time of the signal from the first one of these 307 flip-flops 3071 to 7MR1, and the transmission time from 312 to the VRI bladder output address (503 in Figure 7), which is omitted in Figure 6. By making them equal, it is possible to immediately read out the data stored in the VMRI.

In FIG. 6, WT indicates a signal issued by a write command to each vector mask register. In this example, the equation of FIG.
Set to write state and press up/down color/re32
2-Reset to QO.

Then, the number of writes is counted up by the write signal 422 for each element, and the signal 423 is counted up.
writes the result to VMR-'1. Then, the value of the counter 303 is 1″t″ to indicate the end of processing for all elements.
It is detected by the signal 424 indicating that it is in the write state, and the record that it is in the write state is canceled from 311, and the record that it is in the read state is canceled from 321 to 331.

The above operation is the same as the VMRl write control method using the vector mask register interaction explained in FIG. 6, so I/iVMI'? , 2 and the write side control circuits of VMR3 are omitted.

Without waiting for all elements of equations (1) and (2) in Figure 1 to be processed, when the vector mask operation instruction of equations (1) and (2) is issued m11, 1NiT is written. The signal 207 instantly sets the state 311 of VMRl to the write state, and the up/down counter 31
2 is reset to 0 in the same way as the process of equation (1) described above, but it is also set to the state of VNR2 and VMR3 or to the read state. Therefore, in this example, when the program shown in FIG.
Since 03 is off, control is performed to permit reading of only written elements.

The counter 322 is incremented by 1 each time one element is written by the instruction in equation (1) above, so in vector mask operations using the result, reading is permitted as long as the value of the counter 322 is positive. A signal 404 is issued and the counter 322 is decremented by 1.

In the example, -1 is added to 408 for simplicity, but 40
It may be -1 by 6.

If the value is decreased by 1 due to 408, the performance may deteriorate compared to when the value is decreased by 1 due to 406, but this deterioration is 3
This can be avoided by using the circuits 91 to 394. signal 406
When the value is -1, the circuits 391 to 394 are unnecessary. In the following, for the sake of simplicity, the circuits corresponding to 391 to 394 at the time of generating the read permission signal of the hector register and vector mask register and the calculation permission signal are omitted in the drawings.

Similar to VMR2, VMR3 also creates a read permission signal, and 406, which is an AND condition of both, becomes the final calculation permission signal, advances the value of read address 302, and passes through read selectors 326 and 336. At the same time as sending data to the vector mask dedicated arithmetic unit 305, +1 is added to the value of the counter 312 as a write permission signal, and the value of the write address 304 is advanced. Here, by using the arithmetic unit 141 exclusively for calculations between vector mask registers, it is possible to speed up the processing with a small addition of cost. In Fig. 5, the configuration is three vector register arithmetic units and one vector mask only arithmetic unit, but the input data width of the vector mask only arithmetic unit is 32 to
Compared to 64 bits/element, the latter uses 1 bit/element, and the cost can be reduced accordingly.

It can be seen that the control shown in FIG. 6 synchronizes the 7th to 8th commands and the 9th command, but in FIG.
This shows the method for synchronizing instructions in step 2. MR2 and MR
Since the readout control circuit No. 3 employs the same circuit as that of the vector mask registers VMR2 and VMR3 of FIG. 6, the explanation thereof will be omitted here. The difference between the read control circuit of VMRl and the read control circuit of FIG.
The flip-flop is newly provided to record that it is not a conditional instruction, and in that case, the vector mask value 603 sent to the arithmetic unit etc. is always set to '1' via the signal 602'. This flip 70 tube allows the same arithmetic unit 505 to be used for other than conditional vector arithmetic instructions.

Furthermore, in addition to the signal 406 obtained by ANDing the read permission signals of VMR2 and VMR3 in FIG. 6, the arithmetic processing permission in FIG. 7 (in this example, one element main memory storage permission) is applied.
Signals 606i,j: Vector mask register VMRI
and the vector register VR,1.
read permission signal 634 and main memory write control circuit 10
The reception from 21 is an AND operation with the permission signal 601. In the case of processing a main memory write instruction other than a conditional instruction, 1 is stored in the register 502 by the signal 207, and the signals 602 and 011. By the circuit 543,
Signal 644 is always set to 1.

〔Effect of the invention〕

As described above, as shown in the time chart of FIG. 4, the process that conventionally took 3N+3 cycles can be processed in N+3 cycles according to this patent.

The breakdown of this shortened 2N cycles is that the conventional method loses N cycles due to non-parallel processing between the vector mask generation comparison operation instruction and the AND operation instruction between vector masks. The loss in the conventional method due to non-parallel processing between the instruction and the conditional vector operation processing (conditional main memory storage in this example) instruction is N cycles, and to improve both losses, the The two types of synchronization mechanisms shown in FIGS. 6 and 7 each contribute. Both improvements can be achieved by expanding the normal vector register without using a dedicated vector mask register and arithmetic unit, but by dedicating it, it is possible to obtain the same performance at a lower cost. It is clear that there is a 32- to 64-fold advantage in

[Brief explanation of drawings]

Figure 1 shows FORTRAN including masked vector processing.
Program example. FIG. 2 shows the processing procedure of the program shown in FIG. 1 according to the prior art. FIG. 3 is a time chart of the process of FIG. 1 according to the prior art. FIG. 4 is a time chart of the processing of FIG. 1 according to the present invention. FIG. 5 shows an example of the configuration of a processing device according to the present invention. FIG. 6 shows an example of control of execution of operations between vector mask registers, and FIG. 7 shows an example of control of execution of conditional vector main memory storage processing. 121 to 123 are registers dedicated to vector masks. 1st mouth p million Ill:l' U=l, N IF('ic CA(r-), E(L
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Claims (1)

[Claims] 1. Two or more vector mask exclusive registers, at least one vector mask exclusive arithmetic unit, and a system for performing read processing from the same vector mask exclusive register in parallel with write processing to the vector mask exclusive register. Means for synchronization, synchronization means for reading and computation between required mask information when processing arithmetic instructions between registers dedicated to vector masks, and vector data and masks required when processing vector arithmetic instructions with masks. A masked vector arithmetic processing device having means for reading out information and synchronizing arithmetic processing. 2. The synchronization means between write processing and read processing for the same vector mask dedicated register is performed in the processing of a read command that reads after a write command.
1. The device according to item 1, having means for synchronizing each vector element. 3. The device according to item 1, which includes a vector register for holding and reading the vector data in the masked vector operation instruction. 4. The device according to claim 3, further comprising means for storing data in a vector register in a main memory with a mask in the masked vector operation instruction. 5. The means for reusing the arithmetic unit used for the masked arithmetic instruction as the arithmetic unit selected as the decoding result of the arithmetic instruction other than the masked vector arithmetic instruction, the means for synchronizing vector data and vector mask data, and the vector 1. The device according to item 1, which is included as part of the mask data reading means.