JPS5960281A - Time corrector for time piece having electrochromic display section - Google Patents

Abstract

PURPOSE:To achieve reduction in current consumption and a longer life of the display element with a higher response speed by applying an erasion/writing pulse only to a segment provided in a section for altering the current state to correct the indication when correcting the time. CONSTITUTION:Time is counted 22 and 26 with a reference signal, counts are decoded 28 into a display signal and an electrochromic display 128 thereof is done with a plurality of segments in response to the display signal. In this case, in response to the operation of a switch 30, a correction pulse for varying the contents of the counts is applied from switches 34 and 36 to generate writing pulses and erasion pulses for display segments each time the correction pulse is generated as shown by 42, 62, 40 and 60. Mutual shift in the erasion and display for the segments is detected and a writing pulse only for the segments in the display shift and an erasion pulse only for the segments in the erasion shift are distributed with gates 100 and 102.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time adjustment device for hour chanting having a display section using an electrochromic (hereinafter referred to as EC) display element, and in particular, it dramatically improves the display correction distance. E
This invention relates to a C display correction device.

In recent years, display devices using EC display elements have been proposed as electro-optical display means for digital or analog display. A display device using this EC1 display element gold has a better display effect than conventional light emitting diodes, CDs, or crystal display devices! It has been found that

This EC display element t, the EC object '1 placed between the poles.
Electrochromic jJt which can improve image quality by coloring and decoloring due to Sakamoto oxidation reaction when voltage is applied to 1.
Viologen compounds and 1l-iW03 thin films are known as such EC materials.

Unlike a light emitting diode, this EC display element is of a non-emissive type, so the quenching S2 current is small, and a clear display can be obtained even under direct light.

In addition, it is possible to obtain extremely bright colors compared to liquid crystal, and it is also possible to obtain a clear display from any angle.

That is, it has many characteristics such as no viewing angle dependence, and is extremely suitable as a time display means for watches and the like.

Furthermore, a major feature of ECR display elements is that they have a non-volatile memory function that allows the coloring to remain for a certain period of time even after the voltage is turned off after being colored by applying a voltage. A voltage opposite to the voltage must be applied.

Therefore, when correcting the display, it has been said to be necessary to first apply an erasing pulse to erase all display sound, and then apply all writing pulses to the necessary segments.

Progress has been made to make the pulse 11J of this erasing pulse shorter year by year, and it is currently about 1 second, and the pulse 11J of the write pulse is currently about 0.5 seconds. It is. Therefore, one display correction requires 1.
A time of about 5 seconds is required.

In this way, the E C display element requires 1.5 times for one display correction.
Since a time of about seconds was required, the time on the clock [S1
I had a hard time getting used to something like F, which requires a lot of display corrections. Furthermore, when using -'EC display elements for all watches, when correcting the display, erase pulses are applied to all segments to erase all display sounds, and then all writing pulses are applied to the necessary segments to display the display. It is considered standard practice to make corrections, but with this type of display, the entire display disappears for about 1 second, causing a sense of uneasiness to the user. and 11°) Problems such as increasing the current consumption 11 and shortening the lifespan of the display device 11 due to the extended lifespan have arisen.

Misfire]! :%EC Among the multiple segments for forming all characters, numbers, etc. displayed on the display device, erase pulses or Ij, After applying all the writing pulses, the display section iE'(4'
? By doing so, the drawbacks of the conventional example described above are eliminated, the speed is increased, and the consumption is increased by 61%.
, the overall purpose is to extend the life of the display element.

The present invention will be described in detail below based on the drawings.

First, the transition of numbers, etc. displayed on the time display section of a clock will be explained using FIGS. 1 and 2.

FIG. 1 is a diagram showing a time display section in a time display mode or a time correction mode.

1 is a time display device i2: 2 is a tenth digit display section, 4 is an hour digit display section, 6 is a tenth digit display section, 8 is a one minute digit display section, 10
11i, j: Mode changeover switch,
120, minute correction switch, 16 is l),'; fJfi
jJ varnish inch.

Temporary digit 7 when the display is corrected by operating the hour correction switch 13 in the display state shown in No. 1121
) A change in the display state of the receiving part 4 will be explained below, taking as an example.

As shown in FIG.
It consists of seven segments a to g, and in order to display the number "2", segment a + br d
r er g is in display state.・Due to the strange operation of the correct switch 7, the number displayed on the temporary digit display part is "2".
Assuming that there is a transition from ``3'' to ``3'', segment a)
, b, c, d+ If only g is fully displayed, the number "6" will be displayed.
” can be displayed.

Therefore, instruct each segment to put segment ef, which is currently in the display state, into the erased state, and set segment c, which is currently in the erased state, into the display state, and to keep the segment) a, b r d+g fully displayed. The display can be changed from the number "2" to "16" when all the lines are turned on.

If you change this to an EC display element, the display state is pure gold 12.
When moving r3Jil# from d:, the entire display state can be changed by simply applying an erasing pulse to segment e and a rock-cutting pulse to segment c. This is due to the fact that the segments a, b, d, and g maintain all their states due to the non-volatility of the EC display element, so there is no need to apply all the signals.

In this way, if we pay attention to each segment when adjusting the time, in the Ec'fv display element, the display state is determined by fully determining whether to fully apply only one of the erase pulse and the write pulse for each segment. It can be changed to pure gold.

Therefore, if all four erasing pulses and writing pulses are applied to each necessary segment at the same time, the absorption time to change the water saving state can be approximately 1 second, which is equivalent to the pulse width of the erasing pulse. .

FIG. 6 shows an embodiment of the time adjustment device δ of time F1, which has an EC display section of the present invention based on the above principle. FIG.

14 is a reference signal generator such as a crystal oscillator; 16 is a reference (frequency divider circuit that appropriately divides all the signals from the H force generator 14; 18 is a second counter that counts the signal from the frequency divider circuit 16; and 22 is the signal from the seconds counter all-or gate 20i
26 is an hour counter that inputs and counts the signal from the minute counter 22 through the all-OR gate 24; 28 is a decoder that converts the minute counter 222 into a signal indicating the count contents of the hour counter 26; be.

60 is a mode changeover switch, 62 is a second correction switch, 6
4 is a minute adjustment switch, and 66 is an hour adjustment switch.

The operation signal from the second correction switch 62 is the AND gate 3
8 and the voltage is applied to the reset input of the second counter 18.

These are an erase pulse generation circuit and a write pulse generation circuit consisting of a 40.42kJ, one-shot multivibrator, etc.

When the erase pulse generation circuit 4o and the input pulse generation circuit 42 are in the correction mode, the AND gate 44.
An erasing pulse J and a 9-input pulse L are output at the same time in response to the operation signal A of the correction switch 64 which is input through the OR gate 46.52''K valve.

In addition, when switching from correction mode to time display mode, or when currently in time display mode, the signal E or By inputting all numbers 4B from the OR gate 2o, the erase pulse generating circuit 4o outputs an erase pulse Jv, and writes by the function of the Noritsubu flops 56 and 58 which change all output states according to the erase pulse J. The pulse generation circuit 42 outputs write pulses Lf and r.

60 and 62 are erase pulse generation ports (T1?) which function in the same way as the erase pulse generation circuit 40 and the old pulse generation circuit 42. This is a pulse generation circuit.

When the erase pulse generation circuit 60 and the write pulse generation circuit 62 are in the correction mode, the AND gate 64. When input to the OR gates 66 and 72, the operation signal of the correction switch 36 simultaneously outputs the erase pulse and the write pulse.

゛Also, when switching from correction mode to time display mode or when in time display mode, or game 1-
68, ANDGATE 70. By inputting the signal E through all OR gates 72 or the signal from the OR gate 24, the erase pulse generating circuit 60 outputs all erase pulses, and this erase pulse changes all output states by the action of flip-flops 76 and 78. The write pulse generation circuit 62 outputs all loss@bit pulses.

Erasing pulse generation circuit 40, which is activated by operating the minute correction switch 64, etc. Write pulse generation circuit 42° gate circuits 44 to 52, 59, flip-flop 56
, 58, and an erasing pulse generation circuit 60, which is activated by operation of the time correction μ switch 36, etc. The structure and operation of the vj-reading pulse generation circuit 62, the gate circuits 64 to 72, 79, and the flip-flops 76 and 71i1 are as follows:
The only difference is whether it is used to correct the display of the minute digits or the hour digits.

Reference numeral 80 denotes a segment drive circuit, and the same number of circuits are provided as the number of segments for displaying minutes. This segment drive circuit 80 includes flip-flops 82 and 84 that detect the transition of a segment from a display state to an erase state or from an erase state to a display state during modification, and ('1) a write pulse and a write pulse when in the modification mode. Antgame that distributes pulses) 86.
88, and when in the correction mode, one correction operation is all detected and the flip-flops 82, 847 . Reset and gate 90. A flip-flop 92, AND gates 94 and 96 that distribute erase pulses and write pulses when changing from correction mode to timetable ice mode or when in time display mode, and mode changeover switch 3.
All 7 rip 70 signals from 1.0 are applied to the AND gates 94, 96, and the OR gate 98 applies the erase pulse to the segment 1.0. It is composed of 4M of write pulses and an orchestra 100 and 102 that apply the input pulses.

104 is a segment drive circuit having substantially the same configuration and operation as the segment drive circuit 80.

This segment drive circuit 104 also has segment drive circuit 8.
Flip-flop IJ) d~1 corresponding to each Ume component of 0
10, AND gate 112-120, OR gate 122
−． The number of segments is equal to the number of segments for displaying hour digits. 128 is an EC display section having an hour digit display section and a minute digit display section consisting of a plurality of segments.

Next, the operation of the embodiment shown in FIG. 3 will be explained using the time chart sounds shown in FIGS. 4 and 5.

Note that the two-minute display correction operation and the hour display correction operation are performed using the corresponding circuit 2, for example, the segment drive circuit 80 z 1 (
) 4% operations are the same, so only the minute display and its correction operations will be explained.

First, the operation when all phases of the time chart shown in FIG. 4 are in the time display mode will be explained.

In the normal time display mode, the mode selector switch 30 is in the OFF state, the signal B is fixed at L level, and the signal F3 C is fixed at H level.

When the signal +jC is held at the I level, the AND gate 50 is held in the Fl state.

In such a state, when a pulse signal (for example, output is output once every 60 seconds) is output from the J counter 18, this pulse signal is sent to the (F
It occurs at the fth number and is applied to the input terminal of the AND gate 50 after t.

ANDGATE 50 is in its opening stage, so ORGATE 48
The signal F is generated as a signal G through an AND gate 50, and is further applied to the erase pulse generating circuit 40 through an OR gate 52.

The erase pulse generation circuit 40 generates an erase pulse Jff having a predetermined pulse width in synchronization with the rise of the signal I.
i come out. This erase pulse J is segment drive 'H'Q
r) applied to the circuit 80 and also applied to the clock input of the solid tube 70 tube 56;

The flip-flop 56 makes the output Ql t H level in synchronization with υ when the erase pulse J falls. This output Q+
The 1 (number) from 1 is applied to the write pulse generation circuit 42 via the OR gate 46, and the write pulse generation circuit 42 generates 1 write pulse having a predetermined pulse width in synchronization with the rising edge of the signal. Full output of pulse L.

At the same time ΦJ falls on this d) input pulse L, the flip-flop 58 outputs Qzf! The I:H level is set, and the flip 70 knob 56 is reset by ignition) 59'(i;r), and the flip 70 knob 56 is also reset to return to the initial state.

As a result, when the erasing pulse J is output, the cutting pulse L is subsequently output, and both of these signals are applied to the segment driving circuit 80.

To the segment drive circuit 80, a signal C of -I level is applied via an OR gate 98), and this signal N of II level is applied to the reset input of the clip-flops 82 and 84 and one of the AND gates 94 and 96. Applied to the input terminal.

When the erase pulse J is applied to the segment drive circuit 80 in such a state, the erase pulse is applied to the segment via the AND gate 94 and the OR gate ioo which are already in an open state. Thereafter, the downward-looking pulse L is applied to one input terminal of the AND gate 96.

At this time, when the output 2a of the decoder 28 is at H level, the AND gate 96 is in the 1 south state, so the heating pulse L is applied to the segment via the AND gate 96 and the OR gate 102, and the segment)'kff state.

When the output 2a of the decoder is at the L level, the AND gate 96 is closed, so the write pulse L is not applied to the segment, and only the erase pulse J is applied to the segment.

Such an operation is performed every time a pulse signal is output from the second counter to determine whether to display or erase each segment.

Next, the entire operation in the time correction mode will be explained using the time chart shown in FIG.

When changing from the normal time display mode to the time adjustment mode, set the mode selector switch 60 to the δN state (No. A
′j? It is necessary to have someone to bring it to C level.

Shin-Q B Ka J (When it reaches level, AND gate 44
becomes open.

At this time, if the minute correction switch 64 is operated, the operation (r
The T number A is generated on the signal FI via the AND gate 44.

This signal (is applied to the minute counter 221 through the OR gates 2 [1, 46, 52ffi, and the pulse generation circuit 42 and erase) is applied to the pulse generation circuit 40, respectively, to correct the count value, write pulse L, and Erasure no Kurusu J
Prompts the output sound.

In this way, when in the correction mode, the writing pulse L and the erasing pulse J are simultaneously output in response to the operation of the minute correction switch 4.

At this time, the flip-flop 56 is at H level f8-
The flip-flops 56 and 58 are kept in the reset state by the output of the flip-flop 56, and the 7-tube 70-tube 58 is also kept in the reset state by the output of the flip-flop 56.
iJ erasing pulse J) The output state does not change at the same time as +1jJ at the falling edge of write pulse L.

In this way, the write pulse L and the erase pulse, which are output at the same time, are applied to the segment (drive circuit 80).

segment) 4 applied to the lff1K dynamic circuit 80
No. 6C is inverted by the action of the inverter 61 and becomes the L level when the mode selector switch 60 is turned on, so that it becomes an ant game) 94.96i1. is maintained in the closed state, and the reset state of the seven ribbed floats 82 and 84 is also released.

Therefore, by operating the minute correction switch 64, the count value of the minute counter 22 is corrected, and the output 2 of the decoder 28 is
When a transitions from the H level to the L level, the flip-flop 82 synchronizes with this fall and its output Qs
k Set to H level. Since the flip 70 knob 84 opens and turns off the output only at the rising edge of the signal from the output 2a of the decoder 28, its output Q4 remains at the L level.

Therefore, only the AND gate 86 is in an open state, and the erase pulse J is applied to the AND gate 86. The segment is marked through 100 OR gates.
Since the output Qs'c is switched to the H level, the flip-flop 82 is returned to its initial state via the OR gate 9El, and as a result, the flip-flop 92 can also be reset.

The next operation of the minute correction switch 64 causes the poisoning pulse L and the erasure pulse J to be output at the same time, as described above, and the count value of the minute counter 22 is further corrected. The output 2a of the decoder 28 is at L level■■
When the signal shifts to the high level, the flip-flop 81:i in the segment drive circuit 80 switches its output Q4k to the H level in synchronization with this rising edge.

Therefore, the AND gate 88 becomes open and 1. ■・The key pulse L is this AND gate 88 and or game)
102 is fully applied to the segment.

At this time -'i! ) In synchronization with the falling edge of the erase pulse J applied to the segment l:J at the same time as the input pulse L, the flip-flop 92 sets its output to the Qs k Fi level, and the OR gate 98 is operated to close the flip-flop. Reset all the steps 84 and AND gate 90
Through this process, it will also reset itself.

In this way, when 11≦positive mode, the erase pulse J and write pulse L are simultaneously applied to the segment drive circuit 80, and depending on the output state of the decoder 28, erase pulse J or ■: write pulse L is applied to all segments.

After the correction operation is completed, when the mode changeover switch 50 i is turned off, the signal C rises from the L level to the H level due to the action of the inverter 61. In synchronization with the rise of this signal C, the one-shot multivibrator 54ij outputs a pulse signal Ek, and applies a pulse to the AND gate 50 via the OR gate 48.

Since the -rn gate 50 is already in the open state,
The pulse signal is applied to the erase pulse generation circuit 40 through an AND gate 50 and an OR gate 52.

Therefore, 40 erase pulse generation circuits output the erase pulse Jt. At this time, the flip-flop 56, which has already been released from the reset state 1, sets its output Qlk to H level in synchronization with the falling edge of the erase pulse J.

The signal from this output Q1 is passed through all OR gates 464)
It is applied to the write pulse generation circuit 42, and the write pulse generation circuit 42 outputs the old write pulse Lk.

In this way, the mode selector switch 6D is changed from the ON state to 0.
When switching to the F-type mode, an erase pulse J and a rock insertion pulse L are outputted from the erase pulse generation circuit 40 and the υ1 insertion pulse generation circuit 42, respectively, and applied to the segment drive circuit 8[1]. That will happen.

AND gate 94 in segment drive circuit 80 is
When l'iC reaches the fl level, it is in an open state.

Therefore, the erase pulse J is supplied to the segment via the AND gate 94 and the OR gate 1oo2.

On the other hand, AND gate 96 with 6 inputs has 1JS
'+i'C and the output 2a of the decoder 28 go to the H level, resulting in a "med" state, so when both are at the H level, the input pulse L' (T- is passed, and the OR gate is Segment via ID2'.

In this way mode VJYA switch 30 i ON state 1
When switching from the river to the OFF' state (Δ), all the displays are erased once and returned to the original display state pζ (++j<c, so that the user can visually recognize the end of the correction operation. At the same time, it is designed to prevent changes in coloring density due to correction operations of the EC element.

Next, what are the features of the above invention? The benefits and effects are listed below.

(1) When in the correction mode, the current state VB is applied simultaneously to each of the minimum required segments that must be completely changed, so the display is corrected and all erased. This can be done within the time corresponding to the pulse rlJ of the pulses, and the response speed of display correction can be increased.

Is this all segments when corrected? <It is designed so that the corrected display state appears instantaneously without having to go into the erased state once.

(2) Since the configuration is such that the erase pulse or the pull-in pulse gold is applied only to the minimum recessed segments, the current consumption can be reduced along with the memory function of the EC element.

(3) Erasure 1-1: Display change of interest is performed only for the minimum necessary segments, so EC
It is possible to store substances and extend their lifespan.

(4) After the correction is completed, all the displays are erased once, and then the display state is returned to the state before the 111-degree erasure, thereby preventing changes in the coloring density of the EC element due to the display correction.

As described above, the present invention provides a display correction device for an EC display unit that makes it possible to speed up the reaction speed of the E Cj6 display at the time of correction.

[Brief explanation of drawings]

Figures 1 and 782 show the display of tears ↑ display state j7 in Sls. 41F of i+ (a diagram showing all the details, Wj6 is a diagram showing one of the embodiments of the present invention hU1 and U, FIGS. 4 and 5 Q), and a time chart of implementation 11 shown in FIG. 6. 14.・Su、+4・(4、IJ、Yumi Jō 4I- device、16・
... Frequency divider circuit, 18... Second counter, 22... Minute counter, 26... Hour counter, 28... Tecoder,
60...Mode changeover switch, 64...Minute correction switch, 6...Hour correction switch, 40.60...Erase pulse generation circuit, 42.62...Moji-in pulse generation circuit, 80 .104...Segment, drive circuit,
128...EC display 751 Toki

Claims (2)

[Claims] (1) Counter means for counting the entire time according to the time stamp; a decoder means for converting the counted contents of the counter means into a display signal; A timepiece having an electrochromic display section that displays count contents using a plurality of segments; correction means that applies a correction pulse to the counter means to vary the count contents in response to an operation of an external 75β operation section; At 1σ when the correction pulse is generated by the correction means, °t is set to display all segments of the electrochromic display section.
;1. Pulse generating means for outputting a full erasing pulse for causing the writing pulse and the segment to perform an erasing action;
transition detection means for detecting the transition of a segment of the electrochromic display from an erased state to a display state or from a display state to an erased state in response to the output of the decoder; The pulses from the pulse generating means are applied such that the write pulse gold is applied only to the segment where it is detected that the transition is from the display state to the erase state, and the erase pulse gold is applied only to the segment where the transition from the display state to the erase state is detected. 1. A time adjustment device for a watch having an electrochromic display section, characterized in that the device includes a distribution gate means for distributing distribution. (2) The time adjustment device a0 for a watch having an electrochromic display section according to item 1, wherein the pulse generating means outputs the write pulse and the erase pulse at the same time.