JPS5960476A - Graphic japanese character pattern memory reading system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a kanji no-turn memory reading system used, for example, when printing kanji with a serial dot printer. [Technical background of the invention and its problems] In general, in serial dot links that print kanji, etc., the head bins are usually arranged vertically, and when printing kanji characters horizontally, the data is oriented vertically as shown in Figure 1 (5). 0 that needs to be sent to the head with
By the way, the kanji pattern data necessary for printing the kanji characters as described above is usually stored in a storage type memory (hereinafter referred to as kanji ROM) for use in a CRT display or the like, which costs 1 yen. That is, for example, in the case of a 24x24 focus 1st level Kanji ROM O,), the data is horizontally aligned as shown in Figure 1). Therefore, conventionally, for example, in Figure 2 In the system shown in FIG. 1, the kanji ROM 3 cannot be directly connected to the pass line 2 of the CPU 1. If the kanji ROM 3 were directly connected and the CPU 1 processed the kanji pattern data to be rearranged, the kanji ROM would be accessed, for example, 576 times for one character, which would consume a lot of processing time and would be impractical. isn't it. In order to solve such problems, conventionally, a ROM read controller 4 for the kanji ROM 3 is provided, whereby data is read from the kanji ROM 3 in the vertical direction. Specifically, this ROM a output controller 4 has a configuration as shown in FIG.

Now, to briefly explain the operation, as shown in FIG. 4 (6), the horizontal direction fC8, C8°C, and
,, Vertical direction 'd: "o + V + r V2.

First 2. First, write the kanji ROM in kanji address register 4.
The address of 3 is set, and then the start command K is set to the flip-flop 5. In addition, the address counter 6 starts counting at the timing of the clock φ. , Address (RA2゜RA, , RAo) = (ooo)
Counts up from (111), and Kanji ROM3'
r, access. Then, the 7th bit (LSD) of that address is selected by the i selector 7, and 8-bit data is sequentially given to the shift register 8. When the data has been stored in the shift register 8, the address counter 6
A timing signal is outputted from the Nutrope timing generation circuit 9 to the NOR circuit 10 using the timing of the carry outputted from the NOR circuit 10. In response to this timing signal, a control signal 5TII is sent to the printer (not shown) via the NOR circuit 10, and at the timing of this control signal STB, the data in the shift register 8 is transferred to the printer. Due to the carry, the contents of the vertical calculation shift register II become V. is shifted from V to V. And this vertical direction 1t7F shift register 1
The content of 1 changes from ■ to V, and from v2 to V. Then, the bit select counter 12 counts down from 7 to 6. When this bit select counter 12 counts down from 1 to O, a borrow is output, and this borrow changes the contents of the horizontal calculation shift register I3 to 00.
is shifted from C1 to C1.

In this way, the address layer of the kanji ROMJ is determined, and the data is read out and transferred to the printer. and,
Finally, when C2, v2, address Rh=(111), and the bit select counter become O, the process ends. Note that when the control signal STB is transferred to the printer, it is when the Kanji ROM 3 is being accessed, and the path driver I4 is connected to the data bus 15, so that data can be transferred by outputting 5TI3 from the CPU. It has become.

As described above, even in the past, by transferring the data read from the kanji ROM 3 to the printer, kanji can be printed in horizontal writing. However, in the conventional method, the circuit configuration is complicated and the timing of data transfer is extremely difficult. Furthermore, Figure 4 (
When reading out and printing half-width characters as shown in 5) from the kanji ROM 3, there is a disadvantage that circuits are added, which increases the complexity.

[Purpose of the invention]

Is this invention due to the above circumstances? r: This was done in consideration of the
To provide a kanji pattern memory reading method which uses a simple circuit configuration to read out kanji pattern data at high speed in a predetermined order in the vertical or horizontal direction, and reliably transfers the data to a serial dot printer if I;'+1. All purposes. .

[Summary of the invention]

That is, in the present invention, the address information and control information necessary to output the kanji pattern information in a predetermined order to the kanji pattern memory are stored as I'-1 (OM-?
It is stored in the control memory of v. This control memory is accessed by counting its microsteps, for example, by a programmable counter. In the programmable counter, the microstep start address and the number of steps in the control memory are set in advance by the CPU or the like.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to four aspects. FIG. 5 is a block diagram showing a combination according to the present invention. In the figure, 2I is a memory for calculating Kanji pattern addresses, which is usually a P-ROM.0 Memory for dividing Kanji pattern addresses (hereinafter referred to as control memory) 21 stores Kanji pattern data D from Kanji ROM3. -D.

Address information and control information necessary for reading out in a predetermined order (for example, horizontally or vertically) are stored.

This control memory 21 stores address information and control information (hereinafter collectively referred to as a microstep) for each address, and the address is counted and designated by a program 2 mapple counter 22. In other words, a programmable counter (hereinafter simply referred to as a counter)
22, the 0 counter 22 to which the specified microstep of the control memory 2I is accessed is set in advance by the CPU (not shown) to the start address and step number of the microstep of the control memory 2I.
3 is a flip-flop whose output signal (l counter 22 and path driver 1
4, that is, the start and end when reading one character of Kanji pattern data from the Kanji ROM 3 is determined. A decoder 24 converts the microsteps (4-bit signals RC8o-RC8,) from the control memory 21 into nine chip select signals cso-cs.

In addition, the selector 7 selects microstep signals B SEL, ~BSE determined by the control system 21 from the 8-bit data Do-D output from the kanji ROMJ.
Select 1 bit by L and . Furthermore, the strobe timing generation circuit 9 outputs a timing signal based on the microstep signal IFSTI) from the control memory 21. Note that the other configurations are the same as those shown in FIG. 3 above, so their explanation will be omitted. The operation of this configuration will be explained. first,
CPU not shown! First, the first Kanji address is set in the Kanji address register 4, and the microstep start address and step number of the control mechanism 21 are set in the counter 22. Then, the kanji ROM read start command K is given to the flip-flop 23. As a result, the output signal Q of the flip-flop 23 is outputted, and the counter 22 starts the counter operation f:. Similarly, the output of the bus driver 14 has a high impedance. The counter 22 counts in synchronization with the clock φ and outputs the count value to the control memory 2I. Control memory 2
are Kanji ROM address RAo-RA, ROM chip select address 8o-RC8, bit select 13 S E L6-BSF; L, j,; and strobe signal IFSTB-(i- output according to the above count value). 6 shows, for example, the contents stored in the control memory during normal printing of a serial dot printer, and FIG. 7 shows the case of vertical printing of a serial dot printer. step 5
76 is set to 0 in the counter 22. Then, as described above, the start command K is given to the flip-flop 23, and when the counter 22 operates, microsteps proceed as shown in FIG. 6, for example. That is, starting from bit 7 of address 0 (BSEL) and ending with address 7 of C8o.
When progressing to bit 7 of , the output from the Kanji ROM 3 is considered by the selector 7. The selector 7 performs a select operation at 'BSEL, and outputs the output from the Kanji ROMJ to the shift register 8. When all 8 bits are in this shift register 8, IFSTB becomes 1, so
A timing signal from strobe timing generation circuit 9 is applied to NOR circuit 10, and signal STB is output.

In this way, one byte aligned vertically as shown in FIG. 1(5) is output to the printer every eight steps. Then, the steps progress and finally, when it reaches 575@ ground, the counter 22 counts out and the flip-flop 23 is reset. Also, in FIG. 7, the start address 600. By setting the number of steps 72 in the counter 22, the output from the kanji ROM 3 is given to the shift register 8 in parallel by the output of the control memory 21.

Since IFSTB is output at each step, at the same time as STB output from the NOR circuit 10, the shift register 8
The output from is sent to the printer. Note that control commands such as the LF command are executed when the bus driver 14 is in the on state.
Data D for shift register 8. -D7 work 8T
By outputting Bi, both are sent to the printer.

〔Effect of the invention〕

As detailed above, according to the present invention, the address information and control information for the Kanji ROM are stored in the control memory in advance, and by accessing this old memory, Kanji pattern data is transferred from the Kanji ROM in a predetermined order. It can be read extremely quickly. Since the reading order is determined by the address information and control information stored in the control memory, it is extremely easy to change the order, for example, kanji pattern data can be read vertically or horizontally. . Therefore, by transferring this kanji pattern data to, for example, a serial dot printer, horizontal writing and vertical writing! You can easily print kanji such as

Further, since most of the reading operation of the kanji ROM is controlled by the operation of the control memory and the programmable counter 22, the circuit configuration is simplified and the timing of the circuit operation can be easily controlled. Therefore, it is possible to provide an extremely superior Kanji pattern memory reading method.

[Brief explanation of drawings]

Figure 1 (A, l, (B)) is a diagram for explaining the reading method of a conventional kanji pattern memory, Figure 2 is a diagram showing the configuration of a data processing system using the kanji pattern memory, and Figure 3 is a block diagram showing the configuration of a conventional kanji pattern memory reading method, and FIG. 4(A), (1
3) is a diagram for explaining its operation and effect, FIG. 5 is a block diagram showing the configuration of a method for outputting the kanji pattern to the kanji pattern memory according to an embodiment of the present invention, and FIGS. 6 and 7 are diagrams for explaining the kanji pattern. It is a figure which shows an example of the storage content of P-ROM for address Itng. 3... Kanji ROM, 21... P-ROM (control memory) for kanji pattern address calculation, 22... Programmable counter, 23... Fritsubun Rob.

Claims (1)

[Claims] A kanji pattern memory for storing kanji pattern information, a control memory for storing address information and control information necessary for reading kanji pattern information from this kanji pattern memory in a predetermined order, and a control memory for accessing this control memory. A kanji pattern memory reading method, comprising: an access control means, and reading out kanji pattern information in an arbitrary 7N order according to the contents stored in the control memory.