JPH0481072A - Picture memory circuit for printer device - Google Patents

Picture memory circuit for printer device

Info

Publication number
JPH0481072A
JPH0481072A JP2192774A JP19277490A JPH0481072A JP H0481072 A JPH0481072 A JP H0481072A JP 2192774 A JP2192774 A JP 2192774A JP 19277490 A JP19277490 A JP 19277490A JP H0481072 A JPH0481072 A JP H0481072A
Authority
JP
Japan
Prior art keywords
address
image memory
register
bit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2192774A
Other languages
Japanese (ja)
Inventor
Yutaka Shiraku
裕 志楽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2192774A priority Critical patent/JPH0481072A/en
Publication of JPH0481072A publication Critical patent/JPH0481072A/en
Pending legal-status Critical Current

Links

Landscapes

  • Controls And Circuits For Display Device (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Record Information Processing For Printing (AREA)
  • Storing Facsimile Image Data (AREA)
  • Editing Of Facsimile Originals (AREA)

Abstract

PURPOSE:To enable drawing without rotationally operating a processor by setting a data read direction vertical on a picture memory in the case of rotational printing. CONSTITUTION:In the case of rotational printing, after the second word, an adder 7 calculates the sum of the A-side value (X value) of an increment storage register 6 and a preceding address value, this sum is set to a second address register 4 as the next high-order address, and this value is applied through an address selector 5 to a picture memory 1. The picture data is selected by a selector 14 and outputted to an output (g) for each bit and when the number of count clocks (d) in the data reaches Y, a carry signal (f) is outputted from a data counter 10. At such a time, the B of the increment memory register 6 is selected, and the address of the head bit in the next scan line is calculated by the adder 7 and stored in the second address register 4. Thus, it is not necessary to write a dot image in the picture memory after rotation, and performance is improved in the case of rotational printing.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は、プリンタ装置に関し、特に、画像メモリに描
画されたデータの読み出しを行なうプリンタ装置の画像
メモリ回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printer device, and more particularly to an image memory circuit of a printer device that reads data drawn on an image memory.

[従来の技術] 従来この種のプリンタ装置は、印刷モードとして、非回
転印刷と回転印刷とを有している。非回転印刷では上位
装置から与えられた符号データを復号して、ドツトイメ
ージのまま画像メモリに書き込み、回転印刷ではドツト
イメージを画像メモリに書込む際に回転させていた。
[Prior Art] Conventionally, printer devices of this type have non-rotational printing and rotational printing as print modes. In non-rotational printing, the encoded data given from the host device is decoded and written as a dot image into the image memory, and in rotary printing, the dot image is rotated when it is written into the image memory.

[発明が解決しようとする課題] 上述した従来のプリンタ装置は、回転印刷モードの際に
、ドツトイメージを回転した後に、画像メモリに書込む
必要があったので、回転印刷時の性能が悪くなってしま
うという欠点があった。
[Problems to be Solved by the Invention] In the conventional printer device described above, in the rotation printing mode, it was necessary to rotate the dot image and then write it to the image memory, so the performance during rotation printing deteriorated. There was a drawback that

[課題を解決するための手段] 本発明は、1ページ分の画像メモリを有し、上位装置か
らの符号データに従って1ページのデータを画像メモリ
に展開して出力するプリンタ装置の画像メモリ回路にお
いて、1ワード1ビットのチップで構成される画像メモ
リと、該画像メモリ上の1ビットをアクセスするための
アドレス供給手段と、比回転1回転を通知する記憶手段
と、前記画像メモリの1ワード中の1ビットを選択する
手段とを具備することを特徴とするものである。
[Means for Solving the Problems] The present invention provides an image memory circuit for a printer device that has an image memory for one page and expands and outputs one page of data in the image memory according to code data from a host device. , an image memory consisting of a chip of 1 word and 1 bit, an address supply means for accessing 1 bit on the image memory, a storage means for notifying one rotation of the specific rotation, and an image memory consisting of a chip of one word of the image memory, an address supply means for accessing one bit on the image memory, a storage means for notifying one specific rotation, The invention is characterized by comprising means for selecting one bit of the .

[実施例コ 次に本発明について図面を参照して説明する。[Example code] Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。画像メ
モリ1は1ワード1ビットのメモリチップ16個で構成
される。制御部2は画像メモリ1のリードライトをコン
トロールする。1スキヤンラインの先頭アドレスはホス
トプロセッサより信号aを介して第1アドレスレジスタ
3および下位アドレスレジスタ9に書込まれる。印刷の
方向はホストプロセッサより信号eを介してモードレジ
スタ8に記憶される。非回転印刷の場合、2ワード目か
らは、第2アドレスレジスタ4からのアドレスがアドレ
スセレクタ5を介して画像メモリ1に与えられる。2ワ
ード目以降は引取り信号dで第2アドレスレジスタ4が
1ずつカウントアツプされる。この場合、下位アドレス
4ビットは意味を持たず、したがってセレクタ11はB
を選択し、画像メモリ1の16チツプ全てがアクセス可
能状態になる。画像メモリ1のデータは制御部2からの
出力信号で読み出されシフトレジスタ13でシフトクロ
ックに従って1ビットずつgに出力される。
FIG. 1 is a block diagram of one embodiment of the present invention. The image memory 1 is composed of 16 memory chips each having one word and one bit. The control unit 2 controls reading and writing of the image memory 1. The start address of one scan line is written to the first address register 3 and lower address register 9 from the host processor via the signal a. The direction of printing is stored in mode register 8 by the host processor via signal e. In the case of non-rotational printing, the addresses from the second address register 4 are given to the image memory 1 via the address selector 5 from the second word onwards. From the second word onward, the second address register 4 is counted up by one in response to the take-up signal d. In this case, the lower 4 bits of the address have no meaning, so the selector 11
is selected, and all 16 chips of image memory 1 become accessible. The data in the image memory 1 is read out using an output signal from the control section 2, and is outputted bit by bit to g in a shift register 13 in accordance with a shift clock.

一方、回転印刷の場合、2ワード目からは、増分記憶レ
ジスタ6のA側の値(第2図のX値)と、前のアドレス
値との和を加算器7で求め、この和を次の上位アドレス
として第2アドレスレジスタ4にセットし、この値は、
アドレスセレクタ5を介して画像メモリ1に与えられる
。下位アドレスレジスタ9に格納されているビットアド
レスはデコーダ12でデコードビットアドレスに対応す
るチップに対するセレクト信号がセレクタ11を介して
画像メモリ1に与えられる。画像データはセレクタ14
でセレクトされ1ビットずつgに出力される。データの
カウントクロックdの数がYに達したとき、データカウ
ンタ10よりキャリー信号fが出力され、このとき増分
記憶レジスタ6のBがセレクトされ、次のスキャンライ
ンの先頭ビットのアドレスが加算器7で演算されて第2
アドレスレジスタ4に格納される。
On the other hand, in the case of rotation printing, from the second word onwards, the adder 7 calculates the sum of the value on the A side of the incremental storage register 6 (X value in Figure 2) and the previous address value, and this sum is added to the next This value is set in the second address register 4 as the upper address of
It is applied to the image memory 1 via the address selector 5. The bit address stored in the lower address register 9 is sent to the decoder 12, and a select signal for the chip corresponding to the decoded bit address is applied to the image memory 1 via the selector 11. Image data is selector 14
is selected and output one bit at a time to g. When the number of data count clocks d reaches Y, the data counter 10 outputs a carry signal f, and at this time B of the incremental storage register 6 is selected, and the address of the first bit of the next scan line is transferred to the adder 7. The second
Stored in address register 4.

[発明の効果コ 以上説明したように本発明は、画像メモリを1ワード1
ビットのチップを用い、回転印刷のときデータ読出し方
向を画像メモリ上で垂直方向とすることによって、プロ
セッサは通常通りすなわち回転操作することなく描画で
き、したがって従来回転印刷のとき要していた時間が不
必要になり、プロセッサの処理速度を見かけ上向上させ
るという効果を奏する。
[Effects of the Invention] As explained above, the present invention has the advantage that the image memory can be
By using bit chips and making the data readout direction vertical on the image memory during rotational printing, the processor can draw as usual, that is, without rotational operations, thus saving the time previously required for rotational printing. This becomes unnecessary and has the effect of apparently improving the processing speed of the processor.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図、第2図は画像
メモリの概念図である。 1・・・画像メモリ、2・・・制御部、3・・・第1ア
ドレスレジスタ、4・・・第2アドレスレジスタ、5・
・・アドレスセレクタ、6・・・増分記憶レジスタ、7
・・・加算器、8・・・モードレジスタ、9・・・下位
アドレスレジスタ、10・・・データカウンタ、11・
・・セレクタ、 12・・・デコーダ、 3・・・シフ ト レジスタ、 14・・・セレクタ。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a conceptual diagram of an image memory. DESCRIPTION OF SYMBOLS 1... Image memory, 2... Control unit, 3... First address register, 4... Second address register, 5...
... Address selector, 6... Incremental storage register, 7
... Adder, 8... Mode register, 9... Lower address register, 10... Data counter, 11.
...Selector, 12...Decoder, 3...Shift register, 14...Selector.

Claims (1)

【特許請求の範囲】[Claims] 1ページ分の画像メモリを有し、上位装置からの符号デ
ータに従って1ページのデータを画像メモリに展開して
出力するプリンタ装置の画像メモリ回路において、1ワ
ード1ビットのチップで構成される画像メモリと、該画
像メモリ上の1ビットをアクセスするためのアドレス供
給手段と、比回転、回転を通知する記憶手段と、前記画
像メモリの1ワード中の1ビットを選択する手段とを具
備することを特徴とするプリンタ装置の画像メモリ回路
In the image memory circuit of a printer device, which has an image memory for one page and expands one page of data into the image memory and outputs it according to coded data from a host device, the image memory consists of a chip of 1 word and 1 bit. and address supply means for accessing one bit on the image memory, storage means for notifying the specific rotation and rotation, and means for selecting one bit in one word of the image memory. An image memory circuit of a printer device featuring features.
JP2192774A 1990-07-20 1990-07-20 Picture memory circuit for printer device Pending JPH0481072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2192774A JPH0481072A (en) 1990-07-20 1990-07-20 Picture memory circuit for printer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2192774A JPH0481072A (en) 1990-07-20 1990-07-20 Picture memory circuit for printer device

Publications (1)

Publication Number Publication Date
JPH0481072A true JPH0481072A (en) 1992-03-13

Family

ID=16296801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2192774A Pending JPH0481072A (en) 1990-07-20 1990-07-20 Picture memory circuit for printer device

Country Status (1)

Country Link
JP (1) JPH0481072A (en)

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