JPS596108B2 - Teletext receiver crosshatch generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to increasing the functionality of a television multiplex teletext receiver.

More specifically, this proposal concerns a device that receives text broadcasts that are multiplexed with regular television broadcasts and generates crosshatch signals (baseline signals) using the internal counters of this receiving device. This signal is used to monitor various characteristics of a television receiver, and in particular, it provides an apparatus for measuring the linearity of a deflection system and generating a convergence adjustment signal.

2. Description of the Related Art In recent years, technology related to multiplex television broadcasting has rapidly developed, and with this development, various methods of television multiplexing have been proposed.

For example, what is shown in "Experimental System for Teletext Broadcasting" described in Material IT-21-2 of the Image Transmission Study Group of the Television Society of Japan, August 26, 1976, is based on the vertical retrace period of the current television broadcast signal. Control code signals such as channel codes and line number codes, and character signals are sequentially transmitted as pulse signals, and the receiving side stores the character signal pulses corresponding to the specified channel code and stores them, for example, in 15 rows. Eight lines of characters are displayed as one page. In this case, in teletext broadcasting, by providing a channel code before the text signal, one unit of text information is, for example, 15 characters per line and 8 lines per page, and the channel code is specified on the receiving side. By doing so, any program can be displayed.
In a receiver using such a broadcast system, character signals transmitted for each field are temporarily stored in a memory, and after accumulating character signals for one page, they are sent to a cathode ray tube display and displayed on the screen.

Therefore, in TV multiplex teletext broadcasting, one
Character information is transmitted one scanning line at a time in the field, and the receiver stores this information sequentially in its memory. For this reason, the teletext receiver requires a memory for one page of images and a logic circuit to process the information. Built-in. The present invention aims to utilize the above logic circuit more effectively and add new functions. FIG. 1 is a block diagram of an embodiment in which the present invention is implemented in a teletext receiver.
Figures 1 to 5 are conventional television receivers, and Figure 5 is a multiplex teletext receiving apparatus including the crosshatch signal generator of the present invention.

FIG. 2 is a system diagram of the main parts of the multiplex teletext receiving apparatus shown in FIG. Sync separation circuit, 3 is synchronous separation circuit 1
4 is a horizontal synchronization counter that counts horizontal synchronization signals sent from the horizontal synchronization counter 3, and 4 is a multiplex line sampling that detects lines on which teletext is multiplexed (for example, lines 20 and 283) by inputting the count output signal of horizontal synchronization counter 3. 5 is a character signal extraction circuit for extracting a character signal included in a video signal using the output signal of the multiline extraction circuit 4, and 6 is an S as a start signal included in the character signal.
7 is a subcarrier regeneration circuit that extracts a 3.58 MHz subcarrier signal from the video signal; 8 is a clock generation circuit that uses a PLL circuit to generate a 5.73 MHz clock signal synchronized with the subcarrier signal. , 9 is the STX signal extraction circuit 6 to S
a bit counter 1 that starts counting a clock synchronized with the phase of the STX signal every time the TX signal is supplied;
0 is a control code extraction circuit for extracting a control code that extracts a line code and a channel code from a control signal; 11 is a counter that uses the count value of the horizontal synchronization counter 3 as input to count the number of lines in a character signal display; The counting start position is configured to change depending on the output signal of the waiting time gate 18.

In other words, when the set output of the wait time gate 18 is supplied, counting starts when the count value of the horizontal synchronization counter 3 reaches 223, and when the set output is supplied, counting starts from 41. is configured to do so. 12 is a line code comparison circuit that compares the count value of the horizontal line counter 11 with the control code supplied from the control code extraction circuit 10 and sends out a matching output when the two match; 13 is the count output of the horizontal synchronization counter 3; and a display gate 14 which takes the output of the bit counter 9 as input and generates a 1-line display gate signal for displaying only the first line of character display and an 8-line display gate signal for displaying all of the character display. The count value of the horizontal synchronization counter 3 and the output of the bit counter 9 are used as inputs to generate a full-screen blanking signal for blanking the TV signal when full-screen characters are displayed, and a full-screen blanking signal for blanking the television signal when displaying full-screen characters, and a bottom line part of the character display (10 15 is a tuning switch, 16 is a channel encoder that encodes the output of the tuning switch 15, and 17 is a channel encoder. A channel code comparison circuit 18 detects the coincidence between the output of 16 and the channel code supplied from the control code sampling circuit 10; 19 is a buffer memory for sequentially temporarily storing character signals in response to a clock supplied from the bit counter 9; 20 is a buffer memory to which a match signal is supplied from the channel code comparison circuit 17; and a line code comparison circuit 12. This is a transfer gate that sequentially transfers the character information in the buffer memory 19 to the main memory 21 when a match signal is supplied from the buffer memory 19.

Note that the main memory 21 is driven by a clock supplied from the bit counter 9. 22 is a gate switching circuit that selects a display gate signal and a blanking gate signal according to the output signal of the waiting time gate 18; 23;
is a mixing circuit that mixes a television signal and a character signal and supplies the mixture to the video output terminal 24.

In a circuit configured in this way, when the television receiver is set to a channel on which multiplex teletext broadcasting is being performed and the selection switch 15 is operated to select a channel with teletext broadcasting, the channel corresponding to this channel is selected. switch 1
The output signal No. 5 is encoded by the channel encoder 16 and supplied to the channel code comparison circuit 17.

Note that the waiting time gate 18 is set at the same time as the channel selection switch 15 is operated. On the other hand, the synchronization separation circuit 1 separates a horizontal synchronization signal HD and a vertical synchronization signal VD from the video signal supplied to the terminal 2 and supplies them to the horizontal synchronization counter 3.

The horizontal synchronization counter 3 is reset each time the vertical synchronization signal VD is supplied and identifies the display line position by counting the horizontal synchronization signal HD. When the count value of the horizontal synchronization counter 3 reaches a predetermined number of multiplexed character signals (for example, 20 lines and 283 lines), the multiplex sampling circuit 4 detects this and extracts characters only during that line period. A signal is supplied to the signal sampling circuit 5.
The character signal extraction circuit 5 opens a gate circuit (not shown) in response to a signal supplied from the multiple line extraction circuit 4, and supplies only the character signal to the buffer memory 19. Further, the character signal separated by the character signal extraction circuit 5 is STX
It is supplied to a signal sampling circuit 6, which detects a fixed STX code meaning a start located at the beginning of the character signal, and supplies a detection signal to a bit counter 9.

On the other hand, the character signal separated by the character signal extraction circuit 5 is also supplied to the control code extraction circuit 10, where the channel code and line code are extracted, and the channel code is supplied to the channel code comparison circuit 17, which is described above. The output of the selected channel selection switch 15 is matched with the encoded signal.

The Rice code is supplied to a line code comparison circuit 12.

Further, the count output of the horizontal synchronization counter 3 is supplied to a horizontal line counter 11, and the set output from the waiting time gate 18 is supplied to this horizontal line counter 11. Therefore, the horizontal line counter 11 starts counting when the output of the horizontal synchronization counter 3 matches the first line at the position where the eighth line of character information is displayed, that is, when it reaches the 223rd line. As a result, by performing such an operation, the line number is converted into a line code in character display.

In this way, the count output of the horizontal line counter 11 is supplied to the line code comparison circuit 12, where it is compared with the line code supplied from the control code extraction circuit 10, and if they match, the character information in the buffer memory 19 is transferred to the main memory. 21 sequentially. Further, the count output signal of the horizontal synchronization counter 3 described above is also supplied to the display gate 13, and the display gate 13 receives the count output of the horizontal synchronization counter 3 from the count output signal of the horizontal synchronization counter 3.
A 1-line display pulse (from 223 lines to 240 lines) corresponding to a scanning period for one line and an 8-line display pulse (from 41st line to 240 lines) corresponding to a scanning period for displaying 8 lines of characters are generated. Further, the blanking gate 14 inputs and decodes the count output of the horizontal synchronization counter 3, thereby generating an entire surface blanking signal and a lowest row blanking signal that can blank the entire display screen. On the other hand, the aforementioned bit counter 9 counts the output pulses of the clock generating circuit 8 which oscillates a 5.73 MHz clock synchronized with the output of the subcarrier reproducing circuit 7 which reproduces the subcarrier from the video signal. When the STX detection signal is supplied from the sampling circuit 6, the count value is reset, thereby matching the phase of the character signal and the output of the bit counter 9. When the count output of the bit counter 9 is supplied to the buffer memory 19 as a memory clock, character signals synchronized with this clock are sequentially temporarily stored in the buffer memory 19. Such a bit counter 9 includes a frequency divider (not shown) that appropriately divides a 5.73 MHz clock in order to input gate pulses of horizontal period to the display gate 13 and blanking gate 14. The circumferential output is input to a crosshatch signal generating section 25.

The frequency-divided output inputted from the bit counter 9 becomes a signal for creating a vertical lattice of a crosshatch pattern on the screen, as will be described later. In addition, this crosshatch signal generating section 2
Reference numeral 5 receives the output of a count value for appropriately determining the line position from a synchronization counter 3 for counting the number of lines of character signal display in order to create a horizontal grid on the screen. Therefore, the output of the crosshatch signal generator 25 is a video signal for drawing a vertically and horizontally lattice crosshatch pattern, and this output is input as one signal selected by the manual changeover switch 26. Ru. At the same time, the output of the main memory 21 mentioned above is input to this manual changeover switch 26 as the other signal to be selected, and the selected signal is input to the mixing circuit 23. As a result, when the selector switch 26 selects the output of the crosshatch signal generator 25 to be input to the mixing circuit 23, a crosshatch pattern is drawn on the screen. As shown in FIG. 3, this crosshatch signal generating section 25 divides the output of the bit counter 9, that is, the 5.73 MHz reference clock pulse of the character signal that vertically divides the screen horizontal line. It is extracted from the frequency divider output.

Therefore, the number of lattice lines in the vertical direction of the crosshatch pattern and the position on the screen are appropriately determined by pulses having a frequency that is an appropriate integer fraction of 5.73 MHz obtained from this frequency divider. This frequency divider (not shown) is built in to generate a horizontal period pulse given from the bit counter 9 to the display gate 13 and the blanking gate 14 from the 5.73 MHz reference clock inputted from the clock generation circuit 8. It is. Therefore, as shown in FIG. 3, in the crosshatch signal generating section 25, the above-mentioned appropriately frequency-divided output is input from the bit counter 9 to the gate circuit 251 via lines 91, 92, and 93. This gate circuit 251 is for adjusting the appropriate number of vertical grids by combining the divided frequency outputs. This means that if the frequency division output input from the bit counter 9 is used as it is as a vertical crosshatch signal, for example, the frequency division ratio of 15 lines will be calculated from the output of the frequency division ratio to obtain the number of 16 lines. It is not possible to obtain an output signal t), and only 8 frequency-divided outputs can be obtained from 16, which are in a multiple relationship. Therefore, by combining the outputs of appropriate frequency division ratios obtained from the bit counter 9 using the gate circuit 251, the outputs are divided into 15 or 14 lines instead of 16 lines. This is to obtain the circumferential output. 2
Reference numeral 52 denotes a changeover switch for changing the number of lattices in the crosshatch pattern in this way.

One frequency-divided output appropriately drawn out from this selector switch 252 is connected to a pulse width adjuster composed of a one-shot monomulti or the like. 253 to adjust the pulse width appropriately,
The thickness of the grid lines is set appropriately. On the other hand, since the output of the horizontal synchronization counter 3 counts the number of horizontal lines as described above, the output of the count value that determines the position of the horizontal grid on the screen is appropriately sent to the second output of the crosshatch signal generator 25. It is pulled out to the selector switch 254.

One output selected by the second selector switch 254 determines the number of horizontal grids, and the output via this second selector switch 254 is a second pulse width composed of one-shot monomulti, etc. The pulse width is appropriately adjusted by the regulator 255, and the thickness of the lines of the horizontal grid is appropriately set. Such first and second pulse width adjusters 253, 25
The output of 5 is input to mixer 256 to produce vertical and horizontal grid or crosshatch signals which are input to manual selector switch 26.

Therefore, when the contact c of the manual changeover switch 26 is turned to the b side, a crosshatch pattern as shown in FIG. 4 is drawn on the screen. The operations and circuit operations in FIGS. 2 and 3 are as follows.

When the manual changeover switch 26 is closed to the contact b side, the character signal main memory 21 is disconnected, and the crosshatch signal is connected and guided to the cathode ray tube.

Next, by operating the first changeover switch 252, a pulse having an integer fraction of the clock frequency of 5.73 MHz of the bit counter 19 can be selected, and the number of vertical lines of the grating pattern on the cathode ray tube can be changed. Further, by operating the second changeover switch 254, a count output indicating an appropriate line position of the horizontal synchronization counter 3 can be selected, and the number of horizontal lines in the grid pattern on the cathode ray tube can be changed. As already mentioned, the first and second pulse width adjusters 253 and 255 are both mono-multipipe radars, and the thickness of the lines of the crosshatch pattern is set by appropriately selecting their time constants.

Therefore, the mixing circuit 256 synthesizes the vertical and horizontal pulses of the grid. Painted.

In a multiplex character signal receiving device, it is desirable that there be no image distortion in the entire vertical and horizontal directions of the image in order to make it easy to see the characters appearing on the cathode ray tube. Test adjustments can be made using the internally added crosshatch signal generator without the need for a new It provides unique functions, is convenient for operational adjustment, and is overall economical. As described above, the present invention utilizes counters used in a multiplex teletext receiver, in particular counters that count positions in the horizontal and vertical directions, extracts pulses as appropriate, and adjusts waveform shaping and pulse width. By doing so, a crosshatch signal can be realized with a simple configuration. As a result, measurements and adjustments of various characteristics of the receiver using this type of apparatus can be carried out extremely easily and accurately, which is extremely advantageous for mass production.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of the apparatus according to the embodiment of the present invention, Fig. 2 is a system diagram of the embodiment proc, Fig. 3 is a block diagram showing the main part configuration, and Fig. 4 is a crosshatch drawn on the screen. It is a conceptual diagram showing a pattern. A: Receiving antenna, Mouth: Tuner, C: Video intermediate frequency amplification and detection, 2:
・Synchronous deflection circuit, ho...cross luminance signal circuit,
・H・・・・・・Cathode-ray tube, 卜・・・Telecasting receiver, １．・・・Synchronization separation circuit, ３・・・・・・
・Horizontal synchronization counter, 4...Multiple line sampling circuit, 5...Character signal sampling circuit, 6...
STX signal extraction circuit, 7... Subcarrier regeneration circuit, 8... Clock generation circuit, 9...
・Bit counter, 10... Control code extraction circuit, 11... Horizontal line counter, 12...
...Line code comparison circuit, 13...Display gate,
14...Blanking gate, 15...
・Tuning switch, 16...Channel encoder, 17...Channel code comparison circuit, 18
...Waiting time gate, 19...Buffer memory, 20...Transfer gate, 21...
...Main memory, 22...Gate switching circuit,
23...Mixing circuit, 24...Output terminal, 25...Crosshatch signal generation section, 26...
...Manual changeover switch, 251...Gate circuit, 252...First changeover switch, 253.
...First pulse width adjuster, 254...Second changeover switch, 255...Second pulse width adjuster, 256...Mixer.

Claims (1)

[Claims] 1. In a teletext receiver, a cathode ray system that projects an image corresponding to the character signal by frequency-dividing the reference clock pulse of the character signal included in the received signal and appropriately combining the frequency division ratios. a bit counter that outputs a signal representing a vertical lattice obtained by vertically dividing horizontal lines on a tube screen; and a bit counter that is reset by a vertical synchronization signal included in the received signal and that outputs a horizontal synchronization signal included in the signal. A horizontal synchronization counter outputs a signal representing a horizontal grid obtained by dividing the screen in the horizontal direction by counting, and a crosshatch signal is generated by mixing the signal representing the vertical grid and the signal representing the horizontal grid. and a mixer for projecting a crosshatch pattern on the screen by producing a crosshatch pattern and supplying it to the cathode ray tube as a video signal.