JPS5961164A - Complementary metal oxide semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a latch-up phenomenon effectively by diffusing and forming high impurity concentration layers of the same conduction type as each substrate region, in which CMOS transistors are formed, to each substrate region up to sections deeper than sources while the high impurity concentration layers are brought into contact with the sources. CONSTITUTION:The p<+> layer 20 is formed brought into contact with the source 18 of the n channel MOS transistor in diffusion depth sufficiently deeper than the source 18. The p<+> layer 20 is connected to VSS in common with the source 18. The n<+> layer 16 is also formed brought into contact with the source 14 on the p channel MOS transistor side in diffusion depth sufficiently deeper than the source 14. The n<+> layer 16 is connected to VDD in common with the source 14. Consequently, even when hole currents are generated by an intense field effect in the vicinity of the drain of the n channel MOS transistor in a p well 12, the hole currents are extracted effectively to the outside by the p<+> layer 20. Electronic currents generated in the substrate are also extracted effectively to the outside by the n<+> layer 16 in the same manner on the p channel MOS transistor side. Accordingly, a parasitic bipolar transistor is not turned ON, and the latch-up phenomenon is prevented positively.

Description

[Detailed description of the invention] [Technical field of invention] The present invention is a CMOS integrated circuit device U using microscopic elements.

Regarding.

[Technical background of the invention and its problems]

As integrated circuits have become smaller and more highly integrated, the problem of heat dissipation has become the biggest problem. Since a large number of electrical elements (such as transistors) are concentrated on the surface of a silicon piece, the energy consumed by each element becomes large per unit area of the silicon piece's surface.

-The consumed energy becomes heat and must be dissipated, but there is a limit because the heat conductor is limited to silicon (semiconductor), and this heat dissipation problem may become a limit to high integration. do not have.

As is well known as a countermeasure against this problem, the use of CMo8 is considered to be an effective means for reducing the power supply voltage and dealing with circuit problems. However, it is not possible to reduce the power supply voltage to an extreme level due to problems such as manufacturing variations in actual integrated circuits and noise from outside and inside the integrated circuit. Therefore, the electric field strength increases with the progress of miniaturization, causing various strong electric field problems in electrical elements.

The CMO8 circuit is an ideal circuit configuration for reducing power consumption. However, since the p-channel transistor and the channel transistor are placed close to each other, parasitic elements between them are also added to form a feedback circuit, causing a so-called latch-up phenomenon. This latch-up phenomenon is becoming an increasingly serious problem with the progress of miniaturization.

The latch-up phenomenon has conventionally been regarded as a problem that occurs in the periphery of integrated circuits, such as 12-inch integrated circuits, and has been regarded as a problem in resistance to external noise.

1 However, as mentioned above, with the miniaturization, various strong electric field effects occur inside integrated circuits, and the integrated circuits themselves begin to generate noise, which triggers the latch-up phenomenon that occurs in integrated circuits. It has started to occur inside the .

For example, an explanation will be given by taking an n-channel transistor as an example.

As devices become smaller, the voltage generally decreases, but the electric field (
−′voltage/channel length) tends to become higher. For this reason, in micro elements, the electric field is strong near the drain, and a carrier multiplication phenomenon occurs even if no avalanche occurs. Electrons injected from the source generate electron-hole pairs near the drain. Most of the generated electrons flow to the drain, but the holes flow to the substrate side and are taken out, for example, to an electrode provided on the back surface of the silicon piece. At this time, if the specific resistance of the substrate is high, the voltage drop due to the hole current will be high. In other words, due to this voltage drop, the substrate part immediately below the channel part has a positive potential υ, and a substrate bias effect occurs when a positive substrate voltage is applied to the transistor.
Further increase the drain current.

This increased drain current is further multiplied to increase the hole current. This phenomenon becomes more pronounced as the electric field near the drain becomes stronger. Therefore, a phenomenon occurs in which the drain breakdown voltage of a transistor with a short channel length is lower than that of a transistor with a long channel length. This strong electric field effect becomes particularly noticeable when the effective channel length is 2 μm or less.

It will be explained that when this phenomenon occurs in the CMO8 circuit, it leads to the latch azo phenomenon. FIG. 1 shows an example in which an n-channel MO8) transistor is formed in the CMOS transistor 2, and a p-channel MO8) transistor is formed outside the P transistor 2. In this case, P
A vertical np with the n+ layer (source) 3 in the well 2 as the emitter, the P well 2 as the base, and the n-type substrate 1 as the collector.
The transistor (TR2) is parasitic. Also, the p+ layer (source) 4 emitters of the p' Yarnel MOS transnostar, n
A horizontal p
np) A run transistor (TR) is parasitic. During this time, the resistance (R+) in the n-type substrate 1 and the resistance (R3) in the P well 2
), the vertical resistances (R2+R4) of the p and n layers 3 and 4 are distributed, and the value circuit shown in FIG. 2 is constructed. In this circuit, latch-up occurs due to disturbances, one of which will be explained in 4 minutes.For example, consider the case where an external disturbance Ig enters node A, as shown in Figure 2. . Initially, this current flows through resistor R3 and the voltage drop is 1
Generates gRg. This is npn) Runcisstar (T
When the base-emitter contact potential difference of R2) is exceeded, n
pn) '9 resistor TR2 becomes conductive. Therefore, a collector current flows through the 75-ball resistor R1. When this voltage drop across R1 becomes large, the pnp) run sister (TRY) then becomes conductive. The collector current of this pnp transistor TR flows through R3, and its voltage drop acts in the direction of bringing the npn transistor TR2 into the conducting state, and both transistors 75 and 75 are stable in the conducting state. state, i.e. a large 1) between VDO and VSS
A latte-up state occurs where current flows.

It is well known that the problem that leads to such latch-up comes from the circuit nomura meter, and that it is necessary to adjust the circuit.

At the current level of advanced miniaturization, the above conditions are met in most cases, and there is a risk of latch-up.

In order for latch-up to occur, another condition, for example a disturbance condition to node A in Figure 2, is VF:) The circuit equation shows that a voltage difference between the pace emitters that makes the transistor conductive is required. It becomes clear by solving.

In many cases, R1>R4rFt3>R4+α2, so the above equation for VF becomes 'g>n. That is, the voltage drop (R
slg) exceeds the contact potential difference (VF) between the pace and emitter of the npn transistor (TR2), which is a condition for the transistor TR2 to enter a conductive state.

As shown in Figure 1, in an example using a P-well structure) n
A multiplication phenomenon due to electrons in the channel transistor is likely to occur, and as described above, a hole current flows into the P-well region. This hole current is taken out to the outside extraction port (p+) of the P well through the resistor R3. If the distance between them is long, the value of resistance R3 will be large, and the n-channel MOS transistor/nostar in Latcher and Zubuel 2 will have a channel width as shown in Figure 3 (plan view) and Figure 4 (cross section). If the resistor R3 is large, the resistance R3 when looking at the P well 2 from left to right is several tens of Ω.

At this time, n-channel MO8) Runnostar has channel length 1
When it is about 5μ, the hole current flowing into the substrate becomes several tens of μA when the drain voltage is about 6V, for example. Therefore, the voltage drop across R3 may approach IV. Since the contact potential difference between the pace and emitter of the npn transformer is about 0.4V, the npn (npn) composed of the source (re+)/P well (p)/substrate (n) near point B in FIG. Transistor TR2 becomes conductive,
This leads to the latch-up described above.

[Purpose of the invention]

The present invention provides a structure that effectively prevents latch-up in a CMO8 integrated circuit using microscopic elements.

[Summary of the invention]

In CMO8, it is not possible to reduce the specific resistance of the substrate region very much for both p'n channels due to the requirement for gate threshold voltage. Therefore, in order to effectively prevent the latch-up phenomenon, it is important to effectively extract the current caused by the majority carriers flowing in the substrate region to the outside.

The present invention is characterized in that a high impurity concentration layer of the same conductivity type is formed in contact with the source in each substrate region where the CMOS transistor is formed and is diffused deeper than the source.

〔Effect of the invention〕

According to the present invention, on the n-channel MO8 transistor side, the p layer provided in contact with the source effectively extracts the hole current in the p-type substrate region to the outside, and similarly
) On the Lanzoster side, the n+ layer provided in contact with the source can effectively take out the electron current in the n-type substrate region to the outside.

As a result, the latch-up phenomenon can be reliably prevented from occurring even in the CMO8 using a fine element with an effective channel length of 2 μm or less, where strong electric field effects tend to occur near the drain.

[Embodiments of the invention]

The configuration of one embodiment of the present invention is shown in FIG. An n-type Si substrate 11 is used, a P-well 12 is formed thereon, and the n-type Si substrate 1
A p-channel MO8) consisting of a p-type drain 13, a source 14, and a dirt electrode 15 is formed in 1.
An n-channel MO8 transistor consisting of an n+ drain 17, a source 18, and a gate electrode 19 is formed in the P well 12. The above basic configuration remains the same as before.

In this embodiment, a p-layer 20 is provided in contact with the source 18 of an n-channel MO8 transistor with a sufficiently deep diffusion depth. This p layer 20 and the source 18 have a common V
! 18 (for example, OV). Further, on the p-channel Mo8 transistor side, an n+ layer 16 is provided in contact with the source 14 and has a diffusion depth sufficiently deeper than the source 14.

And this n-wall 16 is also in common with the source 14 and V
Connected to DD (eg +5v).

Note that the width L2 of the source 18 is smaller than the width L1 of the drain 170, as shown in the figure, so that the p layer 20 is as close as possible to the channel region where substrate current (holes) is generated due to the strong electric field effect described above. Source 18 so that
It is desirable to form them in layers. nN on the p-channel side
The same applies to 16. Also each source 111.14
For high integration, it is preferable to provide the electrodes for the p+ layer 2θ and the n+ layer 16 so as to continuously straddle and contact them, respectively.

According to this embodiment, in the P-well 12, an n-channel MO
8) Even if a hole current is generated due to the strong electric field effect near the drain of the transistor, this hole current is effectively extracted to the outside by the p+ layer 20 without flowing through a long path. Similarly, on the p-channel MOS transistor side, the electron current generated in the substrate is effectively extracted to the outside by nJ16. Hence the parasitic pie? - The latch-up phenomenon is reliably prevented because the transistor does not turn on.

[Brief explanation of drawings]

Figure 1 shows the configuration of a conventional CMO8 integrated circuit;
The figure shows an equivalent circuit diagram to explain the latch-up phenomenon, and Figures 3 and 4 respectively show M
OS) A plan view and a cross-sectional view for explaining the strong electric effect in the lannostar, and FIG. 5 is a diagram showing the configuration of a CMO8 integrated circuit according to an embodiment of the present invention. 1-1- n-type S1 substrate, 12-P well, 13°17
...Drain, 14.18...Source, 15゜19
...Dart electrode, 16...n layer, 20...9 layer.

Claims (2)

[Claims] (1) - Forming a reverse conductivity 1 (re-well) on a conductivity type semiconductor substrate, and forming a different conductivity 4 in each substrate region inside and outside the well.
Channel Mo8) CMO formed by forming a lansosta
8. A CN4O8 integrated circuit device, characterized in that a high impurity concentration layer of the same conductivity type as the substrate region is formed in each of the substrate regions in contact with the source of the MoS transistor by diffusion deeper than the source. (2) The CMO8 integrated circuit device according to claim 1, wherein a source electrode is arranged so as to be in contact with both the source and a high impurity concentration layer formed in contact with the source.