JPS5961326A - Circuit for detecting signal interruption - Google Patents

Abstract

PURPOSE:To detect the signal interrupting state by using a logical circuit so as to detect the missing of a timing wave due to signal interruption. CONSTITUTION:A timing signal is applied to one input A of an OR circuit 5 and the timing signal via a delay circuit 6 is applied to the other input B. In this case, the delay time of a delay circuit 6 is determined to a half of a period T of the timing signal. Thus, when the timing signal is inputted, a high level signal H is outputted from the OR circuit 5 and an output D of a mean value detecting circuit 7 goes to a high level VH. On the other hand, when no timing signal is inputted and only noise exsits, the output of the OR circuit 5 is not always at high level and the output of the mean value detecting circuit 7 goes to a level VL being remarkably lower than the level VH. Then, in selecting a reference voltage VS suitably, the state of signal interruption is detected accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a signal disconnection detection circuit that detects the presence or absence of a signal.
In particular, the present invention relates to a signal disconnection detection circuit that extracts information from a part of a timing circuit in a PCM communication system to detect the presence or absence of a signal.

Prior Art and Problems In the PCM communication system, a repeater 1 as shown in FIG. 1 is used to regenerate and relay signals.

This repeater 1 is equipped with an amplifier circuit (kttzhapin
g) 2 and the timing circuit (Rgtiqncing
) 3 and the identification and regeneration circuit (Re,generation).
There are three basic functional circuits: n)4. In the repeater 1, the high frequency components of the code pulses transmitted from the transmitting side usually undergo significant attenuation distortion, so they are
amplify while compensating. Further, the timing circuit 3 extracts a clock frequency component from the received code pulse sequence and generates a timing pulse using the clock frequency component, and the identification and regeneration circuit 4 generates a timing pulse.
It is triggered to identify [lJ, l'-OJ of the equalized amplified waveform outputted from the amplifier circuit 2. As a result, the identification and reproducing circuit 4 can reproduce and output the same code and orus transmitted from the transmitting side. At this time, the repeater 1 is provided with a signal disconnection detection circuit for detecting whether or not a signal is being transmitted.

The conventional signal disconnection detection circuit extracts a timing signal from a part of the timing circuit 3, clamps it, and detects its peak value. When a signal is present, a timing wave is also obtained, so the peak value at that time has a large value, but when the signal is off, the signal obtained from the timing circuit 3 has a small peak value, so that peak value is the threshold value. When it is larger, it is determined that there is a signal, and when it is smaller, it is determined that the signal is off.

However, with this detection method, it is difficult to accurately detect when the mark rate is small because the S/N ratio of the timing circuit input signal is not very good. The detection level does not change significantly when the mark rate is 0/2'4.
Therefore, there was a drawback that it was difficult to set the determination level.

OBJECT OF THE INVENTION The object of the invention is to remedy this drawback. It is an object of the present invention to provide a signal disconnection detection circuit that can reliably detect a signal disconnection even when the mark rate is low.

Structure of the Invention In order to achieve this object, the signal loss detection circuit of the present invention detects the presence or absence of an input signal.
Delay means, logic circuit, comparator P7. A timing wave is input to one of the logic circuits and also to the delay means, the output of the delay means is combined with the other input of the logic circuit, and the presence or absence of a signal is determined based on the output of the logic circuit. It is characterized by being made to do.

Embodiment of the Invention An embodiment of the present invention will be described with reference to FIGS. 2 and 3.

FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 6 is an explanatory diagram of its operation.

In the figure, 5 is an OR circuit, 6 is a delay circuit, 7 is an average value detection circuit, and 8 is a comparator.

In the OR circuit 5, a timing signal is applied to one input terminal A, and a timing signal via the delay circuit 6 is applied to the other input terminal B. Now, if the period of the timing signal is T, the delay time of the delay circuit 6 is set to K of this period 'r, (7) Then, if the timing signal at the input terminal A is shown in Figure 3, then the OR The other input terminal B of circuit 5
A signal shown in FIG. 3 (CB), which is 180 degrees behind this signal, is applied to the signal.

Therefore, the input terminals A and B of the OR circuit 5 are as shown in FIG. 3 (4).
, (6), a high level signal is applied to one of the input terminals, so the OR circuit 5 outputs a no-y level signal H as shown in FIG. 3). Therefore, the output of the average value detection circuit 7 also becomes the level vH as shown in FIG. 30.

However, when the signal is cut off and no signal is applied to the repeater,
The input signal is only noise, so the signal extracted from the timing circuit is a random noise signal.

Therefore, when this is applied to the OR circuit 5 as an input,
Even if there is a delay between this and the output of the delay circuit 6, one of them will not always be irregular. Therefore, the output of the average value detection circuit 7 will be at the dotted line Vt after T1 in FIG. .

As shown, Vt is considerably lower than the high level VH.

becomes. Therefore, by appropriately selecting the reference voltage Ve, the output E of the comparator becomes as shown in Fig. 3 (■).
When a signal is present, a high level output Ha can be output, and when a signal is disconnected, a low level output can be outputted to O. In this way, a signal disconnection state can be detected accurately and with a simple circuit configuration.

Theory 1 of the second embodiment of the present invention based on FIGS. 4 and 5.
I will clarify.

In Figure 4, exclusive OR (E
X-0R) circuit 9 is used. The timing wave transmitted from the timing circuit is applied to one input terminal A' of this EX-OR circuit 9, and the timing wave transmitted via the u4 extension circuit 6 is applied to the other input terminal B'. Therefore, if the signals applied to the input terminals A' and B' are present, one will be at a high level and the other will be at a low level, as shown in Figure 5 (4)', (13Y). As a result, a high level signal H is output from the EX-OR circuit 9 as an output C'.
is obtained. However, when the signal is cut off, random periodic noise is manually input from the timing circuit, so the output is also random noise. Therefore, the signal-off state can be detected in the same manner as in the case of the filler 216.

A third embodiment of the present invention is shown in FIG. 6 and 5% FIG. 7.

In the case of FIG. 6, a NAND circuit 10 is used as the logic circuit, and the other configurations are the same as those in FIG. 2 and FIG.

In this case as well, when a signal exists, the timing wave input to the NAND circuit 10, its $41f, and the output wave of the circuit 6 are in the state shown in FIG. 7(A)'' and (E3)'. The output C' of NAND circuit No. is shown in Figure 7 (C)'
It becomes a high level H as shown in FIG. But when the signal is cut off.

Since the random noise is manually generated, the output will also be randano noise, which will also be identified in the same way as in the case of Maki 2 diagram.

Effects of the Invention According to the present invention, the disappearance of a timing wave due to a signal cut-off can be easily detected using a logic circuit, so that it is possible to accurately detect a signal cut-off state.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a PGM repeater, FIG. 2 is a configuration diagram of one embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of FIG. 2, and FIG. 4 is a configuration diagram of another embodiment of the present invention. 5 is an explanatory diagram of the operation of FIG. 4, FIG. 6 is a configuration diagram of the third embodiment of the present invention, and FIG.
It is an explanatory diagram of the operation of the figure. In the figure, l is a relay 6.2 is an equalization width circuit, 3 is a timing circuit, 4 is an identification/regeneration circuit, and δ is an OR circuit. 6 is a delay circuit, γ is an average value detection circuit, and 8 is a comparator. 9 is an exclusive-OR circuit, and 10 is a NAND circuit. Patent applicant Akira Yamatani, agent patent attorney of Hadashitsu Co., Ltd. Figure 3 Figure 4

Claims (1)

[Claims] A signal disconnection detection circuit for detecting the presence or absence of an input signal includes a delay means, a logic circuit, and a comparison means. A timing wave is input to one of the logic circuits and also to the delay means, and the output of the delay means is used as the other input of the logic circuit, and based on the output of the logic circuit, the presence or absence of the signal is determined by the comparison means. A signal disconnection detection circuit characterized in that it makes a determination.