JPS5961465A - Drive circuit for amplifying gate type gto - Google Patents
Drive circuit for amplifying gate type gtoInfo
- Publication number
- JPS5961465A JPS5961465A JP57171438A JP17143882A JPS5961465A JP S5961465 A JPS5961465 A JP S5961465A JP 57171438 A JP57171438 A JP 57171438A JP 17143882 A JP17143882 A JP 17143882A JP S5961465 A JPS5961465 A JP S5961465A
- Authority
- JP
- Japan
- Prior art keywords
- gto
- switch
- auxiliary
- gate
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 14
- 230000003321 amplification Effects 0.000 claims description 8
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 101100449816 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GTO1 gene Proteins 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
- H02M1/096—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the power supply of the control circuit being connected in parallel to the main switching element
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Thyristor Switches And Gates (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、増幅ゲート構造のＧＴＯ（ゲートターンオフ
サイリスタ）のターンオン、ターンオフ制御に用いるゲ
ートドライブ回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate drive circuit used for turn-on and turn-off control of a GTO (gate turn-off thyristor) having an amplification gate structure.
ＧＴＯは、通常のサイリスタに比べてゲート点弧電流が
大きく、ゲートドライブ回路が大型となる。これを改善
するものとして増幅ゲート構造のＧＴＯがある。この種
ＧＴＯは、通常の増幅ゲート形サイリスタの場合と動作
原理は同じで、ただ一般的に補助サイリスタと称される
部分もＧＴＯ構造になっている点が異なる。GTO has a larger gate firing current and a larger gate drive circuit than a normal thyristor. To improve this, there is a GTO with an amplification gate structure. This type of GTO has the same operating principle as a normal amplification gate type thyristor, except that the portion generally called an auxiliary thyristor also has a GTO structure.
第１図は増幅ゲート形ＧＴＯのドライブ回路の一例を示
すもので、Ｑｍ は主Ｇ Ｔ Ｏ、Ｑａ は補助ＧＴ
Ｏであシ、ＧＴＯのカソード（主Ｇ Ｔ ＯＱｍのカソ
ード）とオンゲート電極（補助Ｇ Ｔ ＯＱａのゲート
）の間にオン電源ＥＩＯがオンスイッチＳ。Figure 1 shows an example of the drive circuit of an amplified gate type GTO, where Qm is the main GTO and Qa is the auxiliary GT.
0, the on power supply EIO is connected between the cathode of the GTO (the cathode of the main GT OQm) and the on gate electrode (the gate of the auxiliary GT OQa).
を介して接続されるとともに、オフ電源Ｅ２ｏがオフス
イッチＳ、を介して図示極性に接続されている。, and the off power source E2o is connected to the illustrated polarity via an off switch S.
また、補助Ｇ Ｔ ＯＱａ のゲート、カソード間に
ダイオードＤ１が接続されている。このダイオードＤ。Further, a diode D1 is connected between the gate and cathode of the auxiliary G T OQa. This diode D.
の電圧降下分が補助Ｇ Ｔ ＯＱａ のゲート、カソ
ード間に逆バイアス電圧として加わシ、ターンオフする
。A voltage drop corresponding to the voltage drop is applied as a reverse bias voltage between the gate and cathode of the auxiliary GT OQa, and the auxiliary GT OQa is turned off.
ところで、一般に補助ＧＴＯ部分の点弧感度を高めて行
くとダイオード１個分の逆バイアスでは不足するだめ、
ダイオードを複数個直列に接続したシ、第２図に示すよ
うにツェナーダイオードＺＤ。By the way, generally speaking, if you increase the ignition sensitivity of the auxiliary GTO part, the reverse bias of one diode will not be enough.
A Zener diode ZD is a series of diodes connected in series, as shown in Figure 2.
とダイオードＤ１を組み合わせてバイアス電圧を大きく
する方法がとられる。A method is used to increase the bias voltage by combining the diode D1 and the diode D1.
この場合、ダイオードＤ、はオンゲート電流が直接主Ｇ
Ｔ ＯＱ、ｍ のゲートに流れ込むのを閉止する働き
をする。In this case, the diode D, whose on-gate current is directly connected to the main G
It functions to block the flow into the gate of T OQ,m.
しかし、このような方法では、オフゲート電流の大部分
が逆バイアス用の素子、つ”まりツェナーダイオードＺ
Ｄ、に流れるため、その損失が増大するという欠点があ
る。However, in this method, most of the off-gate current flows through the reverse bias element, that is, the Zener diode Z.
D, which has the disadvantage of increasing loss.
第３図は増幅ゲート形ＧＴＯのドライブ回路の他の例を
示すもので、主Ｇ Ｔ ＯＱｍ と補助Ｇ Ｔ ＯＱ
、ａ をターンオフさせるために男ＩＪＩ固のオフ電
源”！Ｉ ｒｌｈｔを備えている。主ＧＴＯ用のオフ電
ＩＪＩｊＫｔ＋と補助ＧＴＯ用のオフ亀源］ｈ２とはオ
フスイッチＳ、。Figure 3 shows another example of the drive circuit of the amplified gate type GTO, in which the main G TOQm and the auxiliary G TOQ
, a is equipped with an off power source for the main GTO and an off power source for the auxiliary GTO] h2 is an off switch S,
Ｂ ／、を直列に介して接続され、両スイッチＳ２．Ｓ
λ′の接続点が補助Ｇ Ｔ ＯＱａ のカソード（主
ＧＴＯＱｍ のゲート）に接続されている。なお、カ
ソードとオンゲート電極の間にオン電源ＥＩＯがオンス
イッチ８１を介して接続されていることは第１図。B/, are connected in series, and both switches S2. S
The connection point of λ' is connected to the cathode of the auxiliary GTOQa (gate of the main GTOQm). Note that, as shown in FIG. 1, an on-power source EIO is connected between the cathode and the on-gate electrode via an on-switch 81.
第２図と同様である。It is similar to FIG.
しかし、この回路構成では、第４図に示すように主ＧＴ
Ｏのゲートと補助ＧＴ○のゲートは同一のＰベース上に
形成されているため、オフの期間中、ｄｖ／ｄｔ耐量を
考慮してスイッチを閉路したままにするとＰベース層４
の横方向抵抗Ｒを通して補助ＧＴＯ用のオフ亀源Ｆｉｘ
ｔにより電流が定常的に流れ、オフ時の定常ロスが増大
する。However, in this circuit configuration, the main GT
Since the gate of O and the gate of auxiliary GT○ are formed on the same P base, if the switch is kept closed in consideration of dv/dt tolerance during the off period, the P base layer 4
Off-camera fix for auxiliary GTO through the lateral resistance R of
The current flows steadily due to t, and the steady loss during off-time increases.
なお、第４図において、１は補強用タングステン板、２
はＰｌｍ（アノードエミッタ）、３はＮ層、４はＰ）−
（カソードベース）、５及び６はカソードエミッタ、７
及び８はＰｌｍ４に形成された埋込みゲート層、９はオ
ンゲート醒極、１０はカソード電極、１１は補助ＧＴＯ
のカソードと主ＧＴＯのゲートを接続する電極、Ｋｍは
主回路電源、２は負荷である。In addition, in FIG. 4, 1 is a reinforcing tungsten plate, 2
is Plm (anode emitter), 3 is N layer, 4 is P)-
(cathode base), 5 and 6 are cathode emitters, 7
and 8 is a buried gate layer formed in Plm4, 9 is an on-gate electrode, 10 is a cathode electrode, and 11 is an auxiliary GTO.
Km is the main circuit power supply, and 2 is the load.
上記のような定常ロスの増大を避けるだめ、補助ＧＴＯ
用オフ鴫源Ｆｉｎを可変電圧とし、定常状態ではオフ電
源Ｆｉｎの電圧を下げて損失を少なくすることが考えら
れるが、そうすると増幅ゲート部のａｖ／ａｔ耐量が低
下し、もし点弧すると第４図に破線で示すように電流が
流れて、素子ばかりでなく、爆合によってはドライブ回
路までも破損するおそれがある。In order to avoid the increase in steady loss as mentioned above, auxiliary GTO
It is conceivable to make the off-power supply Fin variable voltage and lower the voltage of the off-power supply Fin in a steady state to reduce the loss, but this would reduce the AV/AT withstand capability of the amplification gate section, and if it were to fire, the fourth As shown by the broken line in the figure, current flows, and there is a risk that not only the element but also the drive circuit may be damaged depending on the explosion.
なお、第４図では埋込みケ−１・形のものを示したが、
分割カソード形Ｇ、ＴＯの場合にも全く同様である。In addition, although Fig. 4 shows a built-in case 1 type,
The same applies to the split cathode types G and TO.
本発明は上記のような欠点を除去するためになされたも
ので、主ＧＴＯ用オフ電源と補助ＧＴＯ用オフ電源を直
列接続し、その接続点と補助ＧＴＯのカソードの間に双
方向スイッチを接続するとともに、オフ電源の直列回路
にオフスイッチを挿設すること（Ｃよシ、定常ロスの低
減が図れ、充分なｄｖハを耐量を確保できる増幅ゲート
形ＧＴＯのドライブ回路を提供することを目的とする。The present invention was made in order to eliminate the above-mentioned drawbacks, and consists of connecting the main GTO off power supply and the auxiliary GTO off power supply in series, and connecting a bidirectional switch between the connection point and the cathode of the auxiliary GTO. At the same time, the purpose is to provide a drive circuit for an amplified gate type GTO that can reduce steady-state loss and ensure sufficient DV capacity by inserting an off switch in the series circuit of the off-power supply. shall be.
以下、本発明を図示の実施例に基づいて詳細に説明する
。Hereinafter, the present invention will be explained in detail based on illustrated embodiments.
第５図は本発明の一実施例を示すもので、Ｑｍは主ＧＴ
Ｏ１Ｑ、ａ は補助ＧＴＯ，Ｅ、ｏはオン電源、’ｈ
ｌは主ＧＴＯ用オフ電源、Ｅ２．は補助ＧＴＯ用オフ電
源、Ｓｌはオンスイッチ、６２′ はオフスイッチ、Ｓ
、は双方向スイッチである。前記オン電源Ｅ、。FIG. 5 shows an embodiment of the present invention, where Qm is the main GT
O1Q, a is auxiliary GTO, E, o is on power, 'h
l is the main GTO off power supply, E2. is the off power supply for the auxiliary GTO, SL is the on switch, 62' is the off switch, S
, is a bidirectional switch. The on-power supply E.
はオンスイッチＳｅｅ介してカソードとオンゲート′屯
極の間に接続されている。両オフ車源Ｅ２１ ＋ Ｅ２
１はその間にオフスイッチＳ ／、を介して直列に接続
され、オンａ 源Ｅｇｏと同様にカソードとオンゲート
電極の間に接続されている。そして、主ＧＴＯ用のオフ
′屯源Ｅｔ＋の負側か双方向スイッチＳ３を介して補助
Ｇ Ｔ ＯＱａ のカソード、つ寸り主ＧＴＯＱｍ
のゲートに接続されている。is connected between the cathode and the on-gate terminal via the on-switch See. Both off vehicle source E21 + E2
1 are connected in series through the off switch S/, between which the on a is connected between the cathode and the on gate electrode similarly to the source Ego. Then, the negative side of the off source Et+ for the main GTO is connected to the cathode of the auxiliary GTOQa via the bidirectional switch S3.
connected to the gate.
前記双方向スイッチＳｓは、例えば第６図に示すように
主ＧＴＯのオフゲート電流（工ｇｒＩ）を流すだめのサ
イリスタＴＨに補助ＧＴＯオフゲート電流（工ｇ□）を
流すだめのトランジスタＴＲ及びダイオードＤ２の１は
列回路を逆並列となるように舐続した構成とする。ダイ
オードＤ２はトランジスタＴＲのコレクターエミッタ間
に逆方向電、圧が印加されるのを附１１−するためのも
のである。The bidirectional switch Ss includes, for example, as shown in FIG. 6, a thyristor TH through which the main GTO off-gate current (grI) flows, a transistor TR through which the auxiliary GTO off-gate current (g□) flows, and a diode D2. 1 has a configuration in which column circuits are connected in antiparallel fashion. The diode D2 is used to prevent a reverse voltage and voltage from being applied between the collector and emitter of the transistor TR.
次に、動作について述べる。咬ず、ＧＴＯをターンオン
するにｔ、ｊ： 、スイッチＳ′３．Ｓ３ の開路状
態で、スイッチＳ、を閉略すると、オフ電源Ｅ＋ｏによ
りオンゲートｉＭ、 ＭＣ（工ｇｆ ）が流れ、ＧＴＯ
はターンオンする。Next, the operation will be described. To turn on the GTO, press switch S'3. When the switch S is closed while S3 is open, the on-gate iM, MC (engine gf) flows due to the off-power supply E+o, and the GTO
turns on.
一方、（」ＴＯをターンオフさせるには、スイッチＳｌ
全開路し、スイッチ”’２’＋ＳＲを閉路すると、オフ
電源’４１ ＋ ”’２２によりオクゲード覗流（Ｘｇ
ｒｓ Ｌ（工ｇｒ２ ）が各々主Ｇ Ｔ ＯＱｍ の
カソード、ゲート間と、補助Ｇ Ｔ ＯＱａ のカソ
ード、ゲート間に流れ、主Ｇ Ｔ ＯＱｍ 及び補助
Ｇ Ｔ ＯＱ、ａ はオフ状態となる。そして、主Ｇ
Ｔ ＯＱｍ のゲート、カソード間接合が完全に回
復してオフゲート電流楡、。On the other hand, in order to turn off ('TO), switch Sl
When the circuit is fully opened and the switch "'2" + SR is closed, the off-power supply '41 + "'22 causes the ocgade peeking current (Xg
rs L (gr2) flows between the cathode and gate of the main G TOQm and between the cathode and gate of the auxiliary G TOQa, and the main G TOQm and the auxiliary G TOQ,a are in the off state. And Lord G
The gate-to-cathode junction of T OQm is completely recovered and off-gate current.
が流れなくなったならば（通常のＧＴＯでは約１０μＢ
後）、スイッチＳ、を開路する。オフスイッチＢ２１は
オフ期間中閉路状）μに維持する。If the current stops flowing (about 10 μB in normal GTO)
), switch S is opened. The off switch B21 is maintained in a closed circuit (μ) during the off period.
この結果、主Ｇ Ｔ ＯＱｍ のゲート、カソード接合
には両オフ覗源Ｊｌ ＋ ”１２の和電圧が逆バイアス
電圧として印加され、主Ｇ Ｔ ＯＱｍ のｄｖ／ｄｔ
耐量が確保される。一方、補助Ｇ Ｔ ＯＱａ のゲ
ート。As a result, the sum voltage of both OFF sources Jl + "12 is applied to the gate and cathode junctions of the main G T OQm as a reverse bias voltage, and the dv/dt of the main G T OQm
Tolerance is ensured. On the other hand, the gate of auxiliary G TOQa.
カソード間には逆バイアス紙圧が印加されないが、スイ
ッチＳ３が開路しているため、第４図の破線のような電
流ループは形成されない。また、主ＧＴ○Ｑｍ と補
助Ｇ Ｔ ＯＱ、ａ のゲートが同一のＰベース上に
形成されていることから、補助ＧＴＯ用オフ’ｅＪｔ源
ＥｎよりＰベースの横方向抵抗を血してオフ期１…中に
電流が流れることもなくなる。従って、定常ロスは大幅
に低減される。Although no reverse bias paper pressure is applied between the cathodes, the switch S3 is open, so a current loop as shown by the broken line in FIG. 4 is not formed. In addition, since the gates of the main GT○Qm and the auxiliary GT OQ,a are formed on the same P base, the lateral resistance of the P base is drained from the off'eJt source En for the auxiliary GTO, and the off period is reduced. 1. Current no longer flows inside. Therefore, steady-state losses are significantly reduced.
＠記実施例ではオフスイッチｓｌ、を両オフ電源”２１
＋ Ｆ２１２の［Ｈ列回路における双方向スイッチＳ
３の接続点極よシ補助ＧＴＯ用オフ鴫源”、２側に位置
させたが、第７図に示すように双方向スイッチＳ３の接
続点より主ＧＴＯ用オフ電源Ｅ１重側に位置させてもよ
い。ただし、一般に主ＧＴＯのオフゲート電流（Ｉ６ｒ
、 ）は補助ＧＴＯのオフゲート電流（■ｇｒりより何
倍も太きいため、第５図の位置とした方がスイッチＳ１
２は容量の小さいものですむ。In the example described above, the off switch sl is connected to both off power supplies "21"
+ F212 [bidirectional switch S in H column circuit
The connection point of terminal 3 is located on the 2 side of the auxiliary GTO off power source, but as shown in Figure 7, it is located on the side of the main GTO off power source E1 from the connection point of the bidirectional switch S3. However, in general, the main GTO off-gate current (I6r
, ) is many times larger than the off-gate current of the auxiliary GTO (■gr), so the position shown in Figure 5 is better for switch S1.
2 only needs to have a small capacity.
以上のように本発明によれば、オフ電源を主ＧＴｏ用と
補助ＧＴＯ用の２個とし、これらを直列接続してその接
続点と補助ＧＴＯのカソードの間に双方向スイッチを接
続し、オフ電源の直列回路にオフスイッチを挿設したの
で、オフゲート電流が渡れる経路ＫｆＭ失発生の原因と
なる辿バイアス用デバイスが存在せず、主ＧＴＯのゲー
ト、カソード接合の回復後の双方向スイッチの開路によ
シ補助ＧＴＯ用オフ醒源からＰベースの横方向抵抗を通
る電流路が遮断されることと相俟って定常ロスが大幅に
低減するとともに、補助ＧＴＯ用オフ電諒の小容量化が
可能となる。寸７）１オフ期間中ｄｖ／ｄｔ等によシ補
助ＧＴＯが誤ノ舐９ｒ）〜しでも、主ＧＴｏ用オフ電源
を通り、主回路の６源を辿るループ（第４図の破線）が
形成され７ｒいという利点がある。更に、主ＧＴ、Ｏが
完全にターンオフ状態になつ／ζ後、双方向スイッチを
開いても、オン期間中オフ電源直列回路のオフスイッチ
が１３Ｊ路しているため、王ＧＴＯのゲート、カンード
間にはＰベースの横方向抵抗を消して両オフ電源の和′
電圧が逆バイアス電圧として印加されており、充分なａ
ｖＡｔ耐鎗をイ１１′Ｎ保できる。As described above, according to the present invention, there are two off power supplies, one for the main GTO and one for the auxiliary GTO, and these are connected in series, and a bidirectional switch is connected between the connection point and the cathode of the auxiliary GTO, and the off power supply is turned off. Since an off switch is inserted in the series circuit of the power supply, there is no trace bias device that would cause the loss of KfM, a path through which the off-gate current can pass, and the bidirectional switch can be opened after the main GTO gate and cathode junctions are recovered. Coupled with the fact that the current path from the auxiliary GTO off source to the P-based lateral resistance is cut off, the steady state loss is significantly reduced, and the capacity of the auxiliary GTO off source is reduced. It becomes possible. 7) During the 1-off period, the auxiliary GTO is accidentally turned off by dv/dt, etc. 9r) ~ However, the loop (dashed line in Figure 4) that passes through the main GTo off power supply and traces the 6 sources of the main circuit. It has the advantage of being relatively thin. Furthermore, even if the two-way switch is opened after the main GT and O are completely turned off/ζ, the off switch of the off power supply series circuit is in the 13J path during the on period, so there is no connection between the gate of the main GTO and the cand. To eliminate the P-based lateral resistance, the sum of both off-power supplies'
voltage is applied as a reverse bias voltage and sufficient a
vAt can hold 11'N.
第１図〜第３図は増幅ゲート構造のＧＴＯのドライブ回
路の従来・Ｚｌｌｆ示す接続図、第４図は第３図の回路
例しこおける定常ロスの増大ケ説明するだめの構成図、
第５図は本発明に係る増幅ゲート形Ｇ、 Ｔ Ｏのドラ
イブ回路の一実施例を示す接続図、第６図は同実施例に
２ける双方向スイッチの具体的構成を示す接続図、第７
図は本発明の他の実施ｆｌＪを示す接続図でりる。
Ｑｍｌ・、、主ＧＴＯ１゛Ｑａ・・・補助Ｇ Ｔ Ｏ，
Ｅ、、 ・−・オン′亀源、Ｅ□・・・主ＧＴ Ｏ’用
オフ電源、Ｐ２２２ ・補助Ｇ Ｔ Ｏ用オフ′屯源
、Ｓｌ・・・オンスイッチ、８２′・・・オフスイッチ
、Ｓ３・・双方向スイッチ。
第１図 第２図
第４図Figures 1 to 3 are connection diagrams showing the conventional drive circuit of a GTO with an amplification gate structure, and Figure 4 is a configuration diagram that does not explain the increase in steady-state loss in the circuit example of Figure 3.
FIG. 5 is a connection diagram showing an embodiment of the amplification gate type G, T O drive circuit according to the present invention, FIG. 6 is a connection diagram showing the specific configuration of the bidirectional switch in the second embodiment, 7
The figure is a connection diagram showing another embodiment of the present invention. Qml・、、Main GTO1゛Qa...Auxiliary GTO、
E, ... -.n -on 'turtle source, E □ ... off power supply for the main GT O', P222, auxiliary G T O -off ', SL ... Onswitch, 82' ... off -switches , S3...bidirectional switch. Figure 1 Figure 2 Figure 4
Claims (1)
電極の間にオン電源をオンスイッチを介して接続すると
ともに、主ＧＴＯ用、補助ＧＴＯ用の２個のオフ電源の
直列回路を接続した増幅ゲート形ＩＪＴＯのドライブ回
路において、直列接続した前記両オフ亀源の接続点と補
助ＧＴＯのカソードの間に双方向スイッチを接続し、ま
た主ＧＴＯ用のオフ電源の正あるいは負側にオフスイッ
チを挿設し、ターンオフ時に双方向スイッチ及びオフス
イッチを閉路し、一定時間後に双方向スイッチを開略し
、オフスイッチはオフ期間の開閉路状態を維持するよう
に制御することを特徴とする増幅ゲート形ＧＴＯのドラ
イブ回路。(1) An amplification gate type in which an on-power supply is connected between the cathode of the GTO and the on-gate electrode via an on-switch, and two series circuits of off-power supplies, one for the main GTO and one for the auxiliary GTO, are connected. In the IJTO drive circuit, a bidirectional switch is connected between the connection point of both series-connected OFF power sources and the cathode of the auxiliary GTO, and an OFF switch is inserted on the positive or negative side of the OFF power supply for the main GTO. The amplification gate type GTO is characterized in that the bidirectional switch and the off switch are closed during turn-off, the bidirectional switch is opened after a certain period of time, and the off switch is controlled so as to maintain the open and closed state during the off period. drive circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57171438A JPS5961465A (en) | 1982-09-30 | 1982-09-30 | Drive circuit for amplifying gate type gto |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57171438A JPS5961465A (en) | 1982-09-30 | 1982-09-30 | Drive circuit for amplifying gate type gto |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5961465A true JPS5961465A (en) | 1984-04-07 |
| JPH0344502B2 JPH0344502B2 (en) | 1991-07-08 |
Family
ID=15923120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57171438A Granted JPS5961465A (en) | 1982-09-30 | 1982-09-30 | Drive circuit for amplifying gate type gto |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961465A (en) |
-
1982
- 1982-09-30 JP JP57171438A patent/JPS5961465A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0344502B2 (en) | 1991-07-08 |
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