JPS5961875A - Character pattern memory reading circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character pattern memory readout circuit;
In particular, the present invention relates to a character pattern memory readout circuit using a central processing unit having an input bit configuration that is smaller than the number of output bits of the character pattern memory.

The character nozzle memory represents various characters by dots arranged in X rows and y columns, and stores each dot as a character dot display signal. When reading this character pattern memory, by supplying an address signal and a read clock signal corresponding to the character to be read, the m-bit nogular signal is read out n times as a character dot display signal. It is composed of

In this case, numbers, kana characters, and alphabetic characters can be displayed using a relatively small number of dots, but when displaying complex characters such as kanji, a much larger number of dots is required. Character number turn memory i, l for kanji which is currently commonly used has a 18 x 16 bit configuration.

As a result, the commonly used central processing unit with an 8-bit configuration cannot be used to handle read signals from the character turn memory, and a central processing unit with a 16-bit configuration becomes necessary. are doing.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a character number turn memory ml readout circuit which can read out a character dot light indicating signal as a signal having a smaller number of bits than the number of output pits of a five character pattern memory.

In order to achieve such an object, the present invention reads the character pattern memory a plurality of times, and every time the character pattern memory is read, the entire output signal is divided and taken out. DESCRIPTION OF THE PREFERRED EMBODIMENTS A character pattern memory reading circuit according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a character pattern memory reading circuit according to the present invention. In the same figure, 1ill
: A central processing unit with an 8-bit configuration that controls reading of the character pattern memory, and is a port group P! to which the address node AB is connected. , a port P2 to which a read signal (2) is output, a port P3 to which a write signal lamp is generated, and a port group P4 to which a data bus DB is connected. 2t'i A character pattern memory in which each character pattern formed by a dot matrix of 18 rows and 16 columns is stored as a character dot amizumi signal,
Character designation is performed by a signal providing an address supplied from central processing unit 1 via data bus DB.

3 is a decoder that decodes the address signal AS't and generates address enable signals AE1-AE,'i for each part; 4 inputs the address enable signal AE1 and the light signal lamp; 6 is an AND gate that is input to the address enable signals AE2 and AE3', and 7 is an output signal of the AND gate 6 and the central processing unit 1, etc. Input the supplied read signal RD,
Read out the output signal and use it as the clock signal φ.
The OR gate 8°9 that supplies the turn memory 2 divides the 16-pit output of the character pattern memory 2 into two and outputs 8 each.
A buffer circuit 10 receives the address enable signal AE and the read signal (or game) which enables the buffer circuit 8), and 11 uses the address enable signal τL and the read signal as input to enable the amplifier circuit 9t. OR gate, 12 is a data valid signal F generated from the character number turn memory 2
A Nonotsufa circuit 13 supplies the data Nononu DB with an address enable signal and a read signal port as inputs,
This is an OR gate that enables the p-notifier circuit 12 with its output signal.

Further, 14 is an address latch circuit that latches a signal that provides an address supplied from the central processing unit via the data bus, and 15 is an address enable signal A.
This is an OR gate that takes Es and a write signal as inputs and supplies its output to the latch circuit 14.

In the character pattern memory reading circuit configured in this way, when reading out the contents stored in the character pattern memory 2 and displaying all the characters, the central processing unit 1 first operates as shown in FIG. As shown in a), the address is set in the character pattern memory 2 via the address latch 14 circuit by sending a signal giving the address of the target character to the data bus DB. When the address of the character pattern memory 1 is set in this way, a part of this address signal As is decoded in the decoder 3, thereby generating the address enable signal A1. is generated. After the address enable signal AE is determined to match the write signal 1 at the OR gate 4, it is inverted at the inverter 5, as shown in FIG. 2(b). It is supplied to the character pattern memory 2 as an address enable signal AE.

Character pattern memory 2 receives address enable signal A.
When El is supplied, the address signal is latched internally, and a data valid signal (2) indicating data readout is generated as shown in FIG. 2(c). Then, the central processing unit 1 generates an address enable signal AE4' from the decoder 3, and outputs the address enable signal and the read signal to the OR gate 1 as input.
The buffer circuit 12 is enabled by the output of 3, and monitoring is performed by inputting the data nozzle signal DVt[2.

A read signal (2) shown in 21st+(d) is generated.

Next, the central processing unit [1] addresses the decoder 3 and generates an address enable signal AE2. When the address enable signal A E 2 is generated, the output of the AND gate 6 is inverted to "L", so that the read signal R
D is supplied to the character pattern memory 2 via an OR gate 7 as a read clock signal φ. Therefore, characters)
Every time the read clock signal .phi. Output. In this case, the buffer circuit 8.9, which divides the 16-bit output of the character pattern memory 2 into two and inputs it, receives the address enable signal τG output from the decoder 3 as shown in FIG. 2(f).
Only the buffer circuit 8 is enabled by the output signal of the OR gate 10 which receives the read signal (2) and the read signal (2). Therefore, of the 16-bit output of the character pattern memory 2, only the lower 8-bit signals are taken out in order v and supplied to the data bus DB. t, j), 18 lines X1
The left half of the character nomi pattern staggered by the 6-column dot matrix is output as a 15-row x 8-column dot pattern. When the reading of 18 rows is completed, the data valid signal surface is reversed, so
The central processing unit [IFI determines that the first read operation is completed, then generates the address enable signal AE+ again in order to start the second read operation, and selects the buffer circuit 9] Therefore, Figure 2 (g
), an address enable signal τJt is generated. At this point, the character pattern memory 2 starts the second reading operation, but since the signal giving the address remains locked, this second reading is also the same as the first reading. The same content will be read and output. However, Nomatsuf 7 circuit 8.
9, during the second read, only the buffer circuit 9 is enabled by the address enable signal AH. As a result, during the second reading, only the upper 8-bit signals of the 16-bit output generated from the character pattern memory 1 are sequentially output to the data node DB. The right half of the character displayed by the dot matrix of p, xs rows and 16 columns will be output as a character dot signal. Therefore, by displaying each using the first read signal and the second read signal, a total of 18 rows
The target character is displayed using a six-column dot matrix. Since the central processing unit handles the output signal bits of the character pattern memory 2 in two, it is possible to use elements with a highly versatile 8-pit configuration.

By repeating such Nb operations, the character dots (drag) and ff multiplier signals of the desired characters are sequentially outputted, and these operations are shown in a flowchart as shown in FIG. 3.

In the above embodiment, the case where the output signal of the letter R turn memory is divided into two in the column direction and outputted is explained, but the present invention is not limited to this, and any division can be performed. It can be used as a number. However, is it possible to read the number of times that matches the number of divisions? Needless to say, as the number of divisions increases, the readout time increases because of the need for execution.

As explained above, the character pattern memory reading circuit according to the present invention executes reading of the same content multiple times, and for each reading, divides the data into columns according to the number of columns and outputs the character pattern memory. Even when the number of bits increases, it is possible to use a processing circuit that handles a small number of pits, which is an excellent advantage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the character pattern memory readout circuit according to the present invention, FIG. 2 is a waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a diagram showing the operation of the circuit shown in FIG. 1. Here is a flowchart to show you. l...Central performance processing unit, 2...Character pattern memory, 3...Decoder, 4.7.10.11゜13...
OR gate, 5... Innomata, 6... AND gate, 8, 9.12... 79277 circuit, 14... Address latch circuit, 15... OR Kate. Applicant: Nippon Electric Co., Ltd. 11 MPa

Claims (1)

[Claims] (1) By providing a character pattern memory in which each dot of various character patterns represented by a dot matrix of x rows and y columns is stored as a character dot display signal, and an address enable signal being supplied to this character pattern memory. υ, the character pattern information at the specified address is N
A central processing unit that performs all the controls for reading the character pattern memory twice, divides the output pins of the character pattern memory into υ, and sequentially drives the selection every time the same character pattern is read from the character pattern turn memory. 1. A character no-turn memory readout circuit comprising: N buffer circuits for outputting the outputs of the buffer circuits to a data node in common.