JPS5961958A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To form a thick interlayer insulating film, and to enhance the voltage withstanding property of a semiconductor memory device by a method wherein when a polycrystalline silicon layer is to be etched, a silicon oxide film is made as to protect a groundwork silicon nitride film. CONSTITUTION:After the silicon oxide film 12, the silicon nitride film 13 and a silicon oxide film 14 are formed in order on the suface of a P type silicon substrate 10 having insulatingly isolating oxide films 11, the part other than the prescribed region of the silicon oxide film 14 is removed. Then, after the polycrystalline silicon layer is formed on the silicon nitride film 13 and the silicon oxide film 14, the polycrystalline silicon layer of the part other than the circumference of the silicon oxide film 14 and the silicon nitride film 13 is removed, and a capacitor electrode 15 for storage of informations is formed. Then, the silicon oxide film 14 excluding the part covered with the electrode 15 is removed, and the electrode 15 is oxidized to form the interlayer insulating film 17. Then, the silicon nitride film 13 and the silicon oxide film 12 are removed, and a gate oxide film 18 is formed at the region theeof. After a polycrystalline silicon film is formed on the gate oxide film 18 and the interlayer insulating film 17 in succession, a gate electrode 19 is formed. Accordingly, the thick interlayer insulating film 17 can be formed regardless of formation of the gate oxide film 18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a dynamic MOS memory cell.

Dynamic MO8 memory, which is known as a semiconductor memory device suitable for high density storage, is generally made using two layers of polycrystalline silicon.

FIGS. 1A to 1D are cross-sectional views for explaining a conventional method of manufacturing a dynamic MOS memory cell in the order of steps.

First, as shown in FIG. 1(a), a P-type Noricon substrate 1
After forming an insulating isolation oxide film 2 in the field region of
A first silicon oxide film 3 is formed in a region other than the field region. Next, silicon nitride M4 is formed on the insulating valve All oxide film 2 and the first oxide/recon film 3.

Next, as shown in FIG. 1(b), a first polycrystalline silicon film is formed on the silicon nitride film 4, and then the parts other than the predetermined pattern are removed by etching to form the information storage capacitor electrode 5. . At this time, the silicon nitride film 4 and the first silicon oxide film 3 below the first polycrystalline silicon film to be etched are also etched at the same time.

Next, as shown in FIG. 1C, second and third silicon oxide films 6 and 7 are formed on the silicon substrate 1 and the information storage capacitor electrode 5, respectively, by thermal oxidation.

Next, as shown in FIG. 1(d), a second polycrystalline silicon film is formed on the second and third silicon oxide films 6 and 7, and then etched into a predetermined pattern to form a gate electrode 8. . Thereafter, a highly concentrated N-type impurity region 9 is formed by thermal diffusion or ion implantation using the information storage electrode 5 and gate electrode 8 as masks.

In the dynamic MOS memory cell formed as shown in FIG. 1(d), the second silicon oxide film 6 is the gate oxide film, and the third silicon oxide film 7 is the information storage capacitor electrode 5 and the gate electrode 7. It becomes an interlayer insulating film.

In the conventional dynamic MOS memory cell formed as described above, since it is necessary to make the second silicon oxide film 6 as the gate oxide film thin, the third silicon oxide film 7 as the #jflJ insulating film is made thin. It is difficult to form a sufficiently thick layer. Therefore, it has the disadvantage that it does not have sufficient breakdown voltage as an interlayer insulating film.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor memory device in which the above-mentioned drawbacks are eliminated and the interlayer insulating film between the information storage capacitor electrode and the gate electrode is formed sufficiently thick.

The manufacturing method of the present invention includes a step of sequentially forming a first oxide film, a nitride film, and a second oxide film on the surface of a semiconductor substrate having an insulating isolation oxide film, and selectively forming a region other than a predetermined region of the second oxide film. After forming a polycrystalline silicon layer on the nitride film and the second oxide film, a polycrystalline silicon layer is formed on the periphery of the second oxide film on the side selectively removed in the step and on the nitride film. After removing the polycrystalline silicon layer other than the polycrystalline silicon layer and removing the second oxide film except for the portion covered by the polycrystalline 7937 layer, the polycrystalline silicon layer is made into a single layer. The nitride film is removed using the third oxide film as a mask, and the first oxide film is removed after the nitride film is removed. .

Next, embodiments of the present invention will be described using the drawings.

FIGS. 2(a) to 2(f) are cross-sectional views for explaining an embodiment of the present invention in the order of steps.

As shown in FIG. 2(a), the insulation isolation oxide film 11 is
After sequentially forming a first silicon oxide film 12, a silicon nitride film 13, and a second silicon oxide film 14 on the surface of a P-type silicon substrate 10 having
Selectively remove areas other than the predetermined area of No. 4.

Next, as shown in FIG. 2(b), the silicon nitride film 13
After forming the first polycrystalline silicon layer on the second oxide/recon film 14, the second polycrystalline silicon layer is formed on the periphery of the second silicon oxide film 14 (7) on the side selectively removed in the step @ and on the silicon nitride film. The first polycrystalline silicon layer other than the first polycrystalline silicon layer on the film 13 is removed to form the information storage capacitor electrode 15.

Next, as shown in FIG. 2C, the second 7-licon oxide film 14 is removed except for the portion covered by the information storage capacitor electrode 15.

Next, as shown in FIG. 2(d), a silicon nitride film 1 is formed.
Using C1 as a mask, the information storage capacitor electrode 15 is oxidized, and an interlayer insulating film 17 made of a third oxide/recon film is formed on the surface of C1.

Next, as shown in FIG. 2(e), the silicon nitride film 13 and first silicon oxide film 12 are removed using the interlayer insulating film 17 as a mask. A gate oxide film 18 is then formed in the region from which this second silicon oxide film has been removed. Subsequently, a second polycrystalline silicon film is formed on the gate oxide film 18 and the interlayer insulating film 17, and then etched into a predetermined pattern to form the gate i-pole 19. Thereafter, impurities are introduced using the 1-hour storage condenser electrode 15 and the gate electrode 19 as masks to form an N-type impurity region 20. In this way, an N-channel MOS memory cell is obtained.

In the above manufacturing process, as shown in FIG. 2(d),
A gate oxide film 18 is formed on the capacitor electrode 15 for accumulating misinformation.
A thick interlayer insulating film 17 can be formed regardless of the formation of the interlayer insulating film 17. This is made possible because the second silicon oxide film 14 acts as a stopper to protect the underlying silicon nitride film 13 when etching the first polycrystalline silicon layer into a predetermined shape. .

In the above embodiment, an N-channel MOS memory cell has been described, but the present invention is not limited to this, and can be applied to any method of manufacturing a semiconductor memory device that includes a process in which an oxide film is used to protect the underlying layer.

As described above in detail, the method of manufacturing a semiconductor memory device of the present invention has great effects because a thick interlayer insulating film can be formed and a semiconductor memory device with high breakdown voltage can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are cross-sectional views illustrating a conventional method of manufacturing a dynamic MOS memory cell in the order of steps;
FIGS. 2(a) to 2(e) are cross-sectional views illustrating an embodiment of the present invention in the order of steps. 1°-°゛P-type silicon substrate, 2... Insulating isolation oxide film, 3.°°...° First silicon oxide film, 4...
...Nitride/recon film, 5... Information storage capacitor electrode, 6 Pa°・°°second silicon oxide film, 7
...Third silicon oxide film, 8...Gate electrode, 9...N-type impurity region, 10...
. . . P-type silicon substrate, 11 . . . Insulating isolation oxide film, 12 . . . First silicon oxide film, 13.
... Paranitride silicon film, 14 ... Second silicon oxide film, 15° ... Parameter information storage capacitor electrode, 17 ... Interlayer insulating film, 18 ... ...Gate oxide film, 19... . . . Gate electrode, 20 . . . N-type impurity region. Ax l shi 1 (of) 2nd shi 1 ”' ((L) (C)

Claims (1)

[Claims] A step of sequentially forming a first oxide film, a nitride film, and a second oxide film on the surface of a semiconductor substrate having an insulating isolation oxide film; forming a polycrystalline silicon layer on the nitride film and the second oxide film, and then forming a polycrystalline silicon layer on the side selectively removed in the step;
removing the polycrystalline silicon layer other than the polycrystalline silicon layer on the periphery of the oxide film and on the nitride film;
After removing the oxide film, oxidizing the polycrystalline silicon layer to form a third oxide film on the surface thereof; After removing the nitride film using the third oxide film as a mask, 1. A method of manufacturing a semiconductor memory device, comprising the step of removing an oxide film of No. 1.