JPS5961969A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device of high transconductance and moreover having a high Schottky withstand voltage by a method wherein a first semiconductor layer of a large electron affinity, an N type second semiconductor layer of a small electron affinity, an N type third semiconductor layer provided with a recess, and N type fourth semiconductor layers arranged placing the recess between them, etc., are provided. CONSTITUTION:The non doped layer 11, the N type AlGaAs layers 12, 13, and N type GaAs layers 14 are grown successively on a semi-insulting GaAs substrate, and a source electrode 16 and a drain electrode 17 are formed. Then a Schottky gate electrode 21 is formed on the N type AlGaAs layer 13 at the recess part provided with steps. Because the N type GaAs layers 14 are separated by the degree of 0.05-0.4mum from the gate electrode 21, the Schottky withstand voltage is enhanced, and moreover because width of the recess can be narrowed, series resistance can be reduced, and transconductance is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device having monoterojunctions of the same conductivity type.

(2) Conventional technology and problems Conventionally, one telojunction of the same conductivity type, that is, n-type and n-type, n
There are configurations shown in FIGS. 1 and 2 as structures of high mobility transistors having junctions of type and non-doped, p-type and p-type, and p-type and non-doped.

The structure shown in FIG. 1 includes, for example, a GaAs non-doped layer 1, a first n-type AtGaAS layer (electron supply layer) 2, a second n-type AtGaAs layer (electron supply layer) 2, an n-type GaAs
After forming the As layer 4, the source electrode 6, and the drain electrode 7, a recess Ai was formed by wet etching, and then a Schottky gate electrode 8 was formed to complete the structure. On the other hand, the structure shown in FIG. 2 has a first n-type AAGaAs layer on the GaAs non-doped layer 1, as in FIG.
layer (11! child supply layer) 2, second n-type AtGaAs layer 3
, n-type GaAs layer 4, source electrode 6, drain electrode 7
After forming the n-type GaAs layer, a recess was formed in a portion of the n-type GaAs layer by dry etching, and a Schottky dart electrode 8 was formed in the recess, thereby completing the structure. In semiconductor devices having these configurations, non-dorg Ga
A two-dimensional electron gas layer 9 generated near the hetero interface between the As layer 1 and the n-type AtGaAs layer 2 is connected to the gate electrode 8 and the n-type A
It is controlled by a depletion layer formed between the tGaAs layer and the tGaAs layer.

Here, in the case of the semiconductor device shown in FIG. 1, the dart electrode 8 is placed on the recess A with a gap B between it and the n-type GaAs layer 4, and in the case of the semiconductor device shown in FIG. In this case, the dart electrode 8 is on the recess A and the n-type GaA
It is arranged in contact with the s-layer 4.

Figure 3 (a), (b), Figure 4 (a), (b)
are the source-drain voltage (VD8) and the source-drain voltage (VD8) in the semiconductor device shown in Figure 1g1 and Figure 2, respectively.
The static characteristics (&)

Comparing Figure 3 (,) and Figure 4 (a), we find that
In Figure (a), the ratio of current change to voltage change is smaller. That is, the transconductance (Fm) is small. On the other hand, the breakdown voltage of the main key is as shown in Fig. 4 (b) and as shown in Fig. 3 (
b) has a larger value. Therefore, the structure shown in FIG. 2 has a larger amplification characteristic and is preferable in terms of characteristics, but it has a small Schottky breakdown voltage and is disadvantageous in terms of high drain pipe operation and dirt current during operation.

(3) Purpose of the Invention In view of the above drawbacks, an object of the present invention is to provide a semiconductor device having high transconductance and high Schottky breakdown voltage.

(4) Structure of the Invention The object of the present invention is to provide a first semiconductor layer with a large electron affinity;
an n-type second semiconductor layer with low electron affinity disposed on the first semiconductor layer and constituting an electron supply layer; and a second semiconductor layer disposed on the second semiconductor layer and selectively provided with a recess. an n-type third semiconductor layer, an n-type fourth semiconductor layer disposed on the third semiconductor layer across the recess, and a recess provided in the third semiconductor layer. a gate electrode disposed on the fourth semiconductor layer; a source electrode disposed on the fourth semiconductor layer;
This is achieved by a semiconductor device characterized by comprising a drain electrode.

(5) Embodiments of the Invention The semiconductor device according to the present invention will be described in detail below according to its manufacturing process.

FIGS. 5a to 5g are schematic cross-sectional views showing one embodiment of the manufacturing process of a semiconductor device according to the present invention.

According to the present invention, first, as shown in FIG. 5a, a semi-insulating G
A non-doped GaAs layer (n'--GaAs) 11 with a thickness of about 3000[ x] thickness of n-type AtGa
Ag layer (n+-AAo, a GILo, 7 AI) 1
2 and further has a thickness of about soo[l] of n-type AtGa.
As layer (n+-AtxGal-xA@) 13, further about 6
An n-type GaAs layer (n+-GaAs
) 14 has a continuous At6,3 Ga4.7 As composition, and the amount of AAo decreases as it approaches the surface, that is, the n-type GaAs layer 14, and in the portion close to the n-type GaAs layer 14, At is almost zero, that is, GaAs The book is said to have the composition of By using such a compositionally modulated dope, the source and drain electrodes can be well led out through the n-type GaAs layer 14.

In addition, the n-type GaAs+ layer 14 improves the resistive contact between the source and drain electrodes, makes it possible to derive electrodes with much lower resistance, and prevents the formation of a surface depletion layer in the n-type AtGaAs layer 13. be able to. Note that the carrier concentration used during the growth of these layers was 2xlO
It was cm.

Next, the n-type GaAs f@14 was mesa-etched to form an active region, and after patterning a resist layer (not shown), A u/A u G was formed using a vacuum evaporation method.
e (12% by weight) is continuously deposited, and by lift-off, the source electrode 16 and the drain electrode 1 are formed as shown in FIG. 5b.
Source and drain meme contacts 15 were formed by forming 7 and alloying at about 450[deg.]C.

Next, as shown in FIG.
Source electrode 16, drain electrode 17
Then, a resist pattern 18 for a back electrode is formed by coating the n-type GaAs layer 14 using electron beam lithography. After that, using the opening width C of the resist pattern 18, for example, cct2r'2 with a degree of vacuum of 5 Pa and 1 with He
:1 In a mixed gas, the n-type GaAs layer 14 is dry etched using high frequency power with a frequency of 13.56 [■lz] and a power density of 0.18 (WA7rL2).During this dry etching, the opening width of the resist 18 is A first recess 19 having a width C and the same length C is formed in the n-type GaAs layer 1.
4 is formed. Since the etching rate of the n-type GaAs layer 14 is approximately 200 times that of the nmAAGaAs layer 13, the etching of the n-type GaAsN 14 is completed and the dry etching of the recess is automatically stopped on the surface of the n-type AtGaAg layer 13. .

Next, as shown in the mse diagram, the etching rate is approximately 20
0 [X/min] GaAs etching solution, for example (hydrofluoric acid,
Etching is performed using a hydrogen peroxide mixed aqueous solution) to form a recess 20 (hereinafter referred to as a second recess) below the recess 19 (FIG. 5d). By this wet etching, the width of the recess 19 (FIG. 5d) formed in the n-type GaAs layer 14 is widened to form a recess 19'.

At the same time, a second recess 2o is formed in the n-type AtGaAs layer 13, resulting in a stepped recess 20'. Of course, the depth of this second stage recess 20 can be obtained by stopping the etching at a desired position based on (source and drain currents).

Next, as shown in FIG. 5F, using the resist 18 as a mask, a dart electrode forming metal (21, 21 to, for example, aluminum) is vapor-deposited to a thickness of 0.5 to 1.0 [μm].

Next, as shown in FIG. 5g, the resist 18 and dirt metal 21 are removed by lift-off, and the Schottky gate electrode 21' is made of n-type AtGaA film at the stepped recess 20'.
Formed on the s-layer 13 In such a structure, the two-dimensional electron layer 22 generated near the heterointerface with the n-type AtGaAs #l 2 of the non-doped 7'GaA3 layer 11 is controlled by the dart electrode 21'.

The dirt electrode 21' formed in this way is an n-type Ga
Since the As layers 14 are separated by about 0.05 to 0.4 Cμm, the Schottky breakdown voltage is as shown in FIG. 2 of the conventional example.
What was about 0.8 to 1.0 [V] is improved to 5.0 to 12.0 (V). Furthermore, the width of the recess is close to the width of the dart electrode 21', for example, from 0.05 to 0.05.
4 (μm), preferably 0.05 to 0.1 Cμm
), the series resistance can be reduced and the transconductance increases.

(6) As described in detail of the invention, according to the semiconductor device according to the present invention, it is possible to obtain a semiconductor device having both good transconductance and Schottky breakdown voltage characteristics.

[Brief explanation of drawings]

Figures 1 and 2 are schematic sectional views for explaining conventional embodiments, Figures 3 (a), (b) and Figure 4 (
a) and (b) respectively show the static characteristics shown in the embodiments of FIGS. 1 and 2, and FIGS. 58 to 5g show an embodiment of the method for manufacturing a semiconductor device according to the present invention. It is a schematic sectional view. ] + 11-GaAs non-doped JiJ (n
-GaAs), 2.12-n-type ALG aAs layer (n
+-At6.3 Gio, 7 As), 3.1
3...n-type AtGaAs layer (n+-AjxGaI
-xAs), 4.14-=n-type GaAs layer (n-
GaAs), 5.15...ohmic contact, 6,16...
・Source electrode, 7.17...Drain electrode, 18...
・Resist, 19.19'...first recess, 20・
...Second recess, 20'...Stepped recess, 21.
...Dart metal, 8.21'...Dart electrode, 9,2
2...Two-dimensional electronic layer. Patent applicant Fujitsu Ltd. Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney (1) Yukio Patent attorney Akiyuki Yamaguchi #18 Engraving of IJI document (Contents (no changes) No. 11 Invitation No. 21 Figure 3 (Q) (b)-”Vo,s
() Figure 4 (a) (b) 5d 5th mountain λ1 59'l7! i Procedural amendment (voluntary) October 2-8, 1980 Kazuo Wakasugi, Commissioner of the Japan Patent Office1, Indication of the case, 1982 Patent Application No. 1721742, Name of invention semiconductor device3, Dimensions of the person making the amendment Relationship to the matter Patent applicant name (522) Fujitsu Co., Ltd. 4, agent drawings (all drawings) 6 Contents of amendment The official drawings will be deleted. (No change in content) 7. One official drawing of the attached document list

Claims (1)

[Claims] a first semiconductor layer with a large electron affinity, an n-type second semiconductor layer with a small electron affinity disposed on the first semiconductor layer and forming an electron supply layer, and on the second semiconductor layer. an n-type third semiconductor layer in which a recess is selectively provided; a fourth n-type semiconductor layer disposed on the third semiconductor layer with the recess in between; a dart electrode disposed in a recess provided in the third semiconductor layer;
1. A semiconductor device comprising a source electrode and a drain electrode disposed on a semiconductor layer.