JPS5962892A - Graphic display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD OF THE INVENTION This invention relates to a raster scan type graphics display device for displaying, for example, line or area graphics.

<Prior Art/General f This heel raster scan type graphic display device f includes a display monitor device for displaying figures, a buffer memory for storing the brightness or color of each pixel point of this monitor device, and e ( The figure is displayed by decomposing the figure to be displayed into pixel points and storing them in this buffer memory.Then, the figure is displayed on the screen of the monitor device. Each pixel point is given two-dimensional coordinate values (xl, (yl), and the address of the storage element of the buffer memory corresponding to the small pixel is also a coordinate value or information equivalent to this coordinate value. Therefore, in order to display the above-mentioned monitor device π point fK, it is necessary to write the coordinate value of the point as an address and the brightness or color of the point as data to the buffer memory. In addition, when displaying a line figure, the coordinate values of the pixel points constituting the line segment are generated from the coordinate values of the starting point and the ending point of Ivi!51, or information equivalent to these coordinate values. The coordinate values generated for each pixel point can be stored in the buffer memory vrJ as an address (in addition, many graphic display devices i"i V
In r, a line segment mouth I monthly prime point conversion circuit (jlj) is provided.

f+'s Figure 1 is a block diagram showing the location of this I graphic display 4'.
, (5b) and (5c)' (ix) are sent from the buffer memories (2a), (2b), r, and (2c). )
(2b) (2c) fj, pixel point 4tJ, Nirobit data level L, 8 colors can be displayed, and 1 pixel data 'fi: 1 bit each, rEJ--
r It is designed to hold it in a trace. Moreover, π, each of these buffer memories (2a) (2b) (2c) If
&? , one output terminal (Do), ! :, 3 horn input terminals (1) I ) (A) (wID) are provided respectively.
The output terminal (Do) is the output terminal for data to the monitor, and the input terminal (DI) is the input terminal for inputting data to the buffer memory, and the signal line (6a) , (6b) and (6c), write data is supplied from a register (3) that holds color information.

Furthermore, the input terminal (5) is a write address terminal, and the line segment pixel point conversion circuit (
4), the address ♂, that is, the coordinate value of the pixel point is supplied. Furthermore, the above input terminal (
WE) is a terminal that controls whether or not to perform writing, and is set to π so that when the logical value is "moon", the data is written into the buffer memory. generates one pixel point, line 18 (8
), the logical value [Moon is transferred, and the rock is made to perform. Nao, 1tGIJt - For simplicity, the end required to read the buffer memory is omitted as I-. Note that the upper 11 core registers (3) are the signals supplied from the external phase; IJ. Line (1
When 0) is the logical value 1 month, i1 ``Goji (9a), (9b
) and (9c) to set color data supplied externally. Furthermore, f, the line segment pixel point conversion circuit (4) is connected to a signal line (
14) changes from the logic value "0" to the logic pl value [1], the signal line < 14)f logic value [outside the external π
This indicates that the line segment pixel point conversion circuit (4) is in operation, and performs the operation.This 0711 work is based on the logic value K, l: <) C of the signal line (12) supplied from the outside.
Different. In other words, the signal line (12) is a problem! -1! f1
1'1f-month, the conversion circuit (4) displays the immediately previous end point of the T vector (hereinafter referred to as the current position).
is the starting point, and the seat 1'1' is supplied from the outside via the signal line (11) f:7. Convert the line segment with the end point to a pixel point, write it to the buffer memory Vr at l-, write the pixel point fi++ at the warehouse, set the end point of the line segment at the current position, and believe A, +3! (14) is a logical value [river, and the operation is completed externally, and 1 here and 1 are written as (). The current position is 5”f, VC signal line (1
1) Separate the coordinate values supplied via L, signal line (
14) is made to be π for logical iej r.

Next, FIG. 2 (1)) uses the conventional graphic display device ul described above, and FIG. Figure 2(a) shows an example of the processing flow.
), (1”t) (P2), (J'tH1's), (P
3) (1″4), (P4) (1″sL (I”5) (1
−”e) + (I's) (1'?) + (J), ) (J
), )t and (]', )(PF,)r respectively split [
1. A method is used in which one of these line segments is drawn by J≧π and −j.

Furthermore, when using a conventional graph ink display device to fill in the interior of the polygon shown in No. 31'; IJ (a) VC' with the pattern shown in No. 6 (2) (bl When the intersection points of the polygons are (P, &s) and (1' k S), (J'&s, + and 0
-k E), it becomes a figure as shown in Fig.
From the minimum value to the maximum value, f, r, l-1c =
Find r' from y+-j to = yuJw, divide them into short line segments using the method π described above, and draw 1i
1j-4 In particular, it is possible to fill in J: 51. Conventional graphic display device system (#r) when filling in using the r method
FIG. 4 shows an example of the processing flow of the system fδ.

1, that is, as is clear from FIGS.
When displaying in various shapes, or when filling the inside of a polygon or closed curve with various patterns as shown in Figure 6 (b), it is necessary to divide the line molecules into short lines, This invention requires a lot of processing time for r11, end determination, and cycles f and c.
The one period of the shape of the pixel point f is 1i; ,i!l'
;! l1 from the above register every l to convert minutes to fraction points.
11. By controlling the 4° reading of the buffer memory using the 'jth read value, line segments of various shapes can be displayed at high speed π without having to be divided into 5 and 9 parts. In addition, when filling the inside of a polygon or a closed curve with a periodic pattern, we would like to provide a graphic display device that can fill the interior of a polygon or a closed curve with a pattern having a periodic dot pattern at high speed by using various patterns, that is, as shown in FIG. 1 shows the main structure of the present invention, and the same reference numerals as in the above-mentioned conventional structure (Fig. 1) refer to the same 1゛1q component π, and the explanation thereof will be omitted.

(15) is a figure filling circuit [7 circuits, which has a built-in line shape generation circuit. Each signal line (16>, (17), and (18) is a signal line supplied from the outside, and among these, the signal line (16) is connected to a register or memory inside the figure filling circuit (15). The other signal line (17) is a 6-bit signal line that selects the data set 1-sign register and the memory, and the 'il (18) ) is i:12yl value January, the f-ta is selected by the signal line (16) and the K is set so that the T register or the memory π is set.
1. 'c has been. 1"-J, 015Signal line (8a) 1:L above y'i+y pixel point conversion circuit (4)
generates the address of one pixel.2K, logical value 1-IJ
With the signal line)), the signal f9 (81))lβ logical value 11. When J, each buffer memory (2a) (2b)
The conversion circuit (4) of Sd and (2C) generates 1. The contents of address f, 1/register (5) are written. Additionally, the signal line (11a
N' is the signal line (11)σ)[X] coordinate component.

Next, FIG. 6 shows the internal configuration of the figure filling circuit (15), and the same signals as in FIG. 5 described above are the same as those in FIG.

(19) is the m-pit counter, and the terminal (CLJO
When changes from the logical value "0" to the logical value [month], the logical value π of the terminal (SICT) and the terminal (CLII) Therefore, the value of the terminal ((the value of Don't try to change it to FF.

Next i,, Eg8 Figure (a) In Vc, the symbol 112'' is the value of the terminal (■) of the counter (19). Also, returning to FIG. 6, (20) is the circumference m of the counter (19).
It is a register that holds J, and when the terminal (CLK) changes from the logical value ``1'' to the logical value 1, the terminal ([]
D is stored and output from the terminal (Q).

(21) is a coincidence detection circuit that outputs the signal line C27)K logical value [month] when the values of the signal line (25) and the signal line (26) match. Note that the signal line (27) is connected to the terminal ((,'LI?) yr of the counter (19)
Since the contents of this counter (19) and the contents of the register (20) match, 1, the terminal (CLR) of the counter (19) changes from the logical value "O" to the logical value 1.
When the month changes to l-, the contents of the counter (19) are 1-(
It is designed to be Ll. (22) is a memory of 211 bits x 2n1 words for storing patterns, and the address is given from the terminal (5). When the terminals (1. to "E") of this memory (22) have a logical value rDJ, the contents of the address given at the terminal (DO) ff terminal (5) are output, and the terminal (WEi) l + "- sieve 1 Logical value
1, the value of terminal (1)i) is stored in the address given by terminal (8).

[7] The terminal (5) of the memo I+ (22) is connected to the counter (19) via the signal line (25), so J: jjl '2 memory (22) -r address is the contents of counter (19))
Needless to say. (23) fj.

In the diagram 14 generation circuit, FIG. 7 shows the internal configuration of this circuit (23), '(30) is a selector, ψ114 child (8 stations - ring)] 1! value [river or logical value 1
- When the month, the value of QiiA child (AJ or terminal (13) is outputted from terminal (', a K) 77i
It's six years old. (31) is a register that records the shape of the line, with terminals (l M, (CLK) and ((,
-'s λ'1 discharge is the same 4rls as the register (20). Furthermore, this register (31) (7) terminal (1)
The above selector (30) via the j&yo signal line (39)
The terminal (A) of this selector (3[,]) is connected to (line 1 (2B)).
) through the terminal G)0)f of the sixth I memory (22)
', Furthermore, the terminal (11) of the selector (30) is the signal line (
16) Since each Vr is connected, the upper register (61) is connected to the memory (22) or the signal +%+
It goes without saying that the value of (16) can be set. (32) is the remainder circuit that calculates the remainder), 1 is added to the value of the signal line (44) of the value of the signal line (11a)
If the value of the signal line (44) is limited to 12 to 12 months, the N'fl remainder circuit (32) is Signal line (11a
) lower 11. It can be constructed from a circuit that outputs bits. (66) is selected by selector, terminal (A) a)
.

(S) and (Ql mean the above selector (3[])
It is similar to

Next K, (34) is a counter, (65) is a register that records the period of this counter, and (36) is a detection circuit that detects coincidence of signal lines. '-1114 corresponds to the counter (19) and register (2o) matching 4. ．． i,
This is the same as 21). However, the above counter (
The terminal (11 of 64) is connected to the terminal ((,) Ic of the selector (63) via the signal line (42), and also the y/;1 terminal of the selector (33) (N is the signal line 41). The remainder circuit (32) Ic is connected to the terminal of the selector (33) (1 output is the signal line (16) c, further f is connected to the register (
The terminals (Q) of 65) are respectively connected to the remainder circuits (32) via signal lines (44). Therefore, the counter (34) π is the remainder of the value of the signal H (11a) modulo the sum of the contents Vr1 of the register (35).
Or faith + two! It is possible to set all the values of 羞 (16).

(37) selects 1 bit from the 711-bit signal line 41 (circuit 'TE: Yes, terminal (XI)
φ11.
! Selection signal ('+3)l given to child (1.-i to Sl
/", then output]', jA child 0) output one selected signal line with shi, J, ?lf is hitting. Shigashi ゛C
1 Jingo Gen (4[]) is register (31) 0) i:i
! , i-(Risho, also signal line (II 3)) o,
Above, 翫1 counter (3/I) σ' ”II し了((、υ
r each include I) 1; C of 7th round:, 1, 1- No. X'iJ (4+6)x tx, (M'Ft line (4U
) (7> Internal (7) It goes without saying that the counter (64) selects the pit h'' = output. Next π, (68) is an AND gate, and the input is the signal, the terminal ':l'-f''k) of the selection circuit (37) via 1ait (46), and the line segment double point conversion circuit (4) shown in FIG. 5 via the signal line (8a). The outputs are connected to the line segment 1 (Z point conversion circuit (4)) shown in FIG. 5 through line 8 (8b), and the outputs are the signals A'↓1.! (8b) The buffer memories (2a), (2b) and (2c) shown in FIG. (4) is the value of π that generates one pixel, the counter at that time (34)
If the bit of the register (31) selected by the contents of t is the logical value j-month, then FJr 5. The buffer shown in FIG.

Memory (2a) (2b) (2c) K so that rv writing is performed 1. It has been c.

Next π, O 6 in Figure 6, (24) is the figure fill 1
, the register in the circuit (15) and the system 61 (in one circuit, the signal line (18) is logically yY8 value [
According to the value of the signal line (17), the 8th tA
(+1) H-, signal IT gland (
29) Output the K value.

In addition, 888shil (b) K t+; ite, iia
No. [-+I t', t, I: +J cb Indicates that the value on the left side is to be sent to the register or memory on the right side for the day. In addition, in the above-mentioned control circuit (24), when the signal line (8) is a logic value mark, the signal line (8a) is a logic value mark! ]! As shown in Figure 7, the counter (3
4) 'fc1 is increased by 1, so that the signal line (29) K direct is outputted to 5. Therefore, the signal g (18
) is the logical value ``River'', as shown in Figure 5 ° - J blind; W, α6 The bit of the register (61) shown in the figure is selected next to Jll' and is selected as 1.
This 11^&r J: is the 5171st Vr indicating buffer memory (2JL) (2b): t,;

(a) In the case where the graphic display device of this invention is used to indicate the product by displaying the i-g line segment, :ljl 1st work next 5th line/C
be exposed.

-i-j,'cwa1. ,';n 2 [';4 (al
W, J,, 2f1. i min In, No. 9 Lr
(nl K count sand; Yi, L-, display 1.1
It's cool that the little ones don't look at each other. Cocote, S',! ,9
times (al K+t; in,) 64 points (1't) and ()'2), ψ11.1 points (1'2)o). [Beauty()
'l, ), s1° dark point CP, ) and (P4), kA point (7%), I・τ and (P6) spacing: 8 pixels each, 3! l"l! '-k + 3!'!!
I ; (Mi, assume 3 strokes. In this case, the period of &"r', ri ; IζL7 is 141 group elements. Therefore, 21
Register (31) shown in Figure 57, upper 14 bits K, value 1
−+1iii1110[]0111000J, and
The counter (64) sets the value "0", and the register (
35) After setting the iy values r13Jk, 1 old'A (11) output all the coordinate values of the IC end point (Pg), and output the logical value "interest rate" to the signal line (13).As a result, the 7th
When the bit selected from the register/star (31) shown in the figure is the logical value "month," writing to the buffer memory is performed, so a predetermined line segment can be displayed.

Further, when the polygon shown in FIG. 3(a) K is filled in in the four shapes shown in FIG. 3(b), the processing is performed as follows.

In other words, 4 moi ζQ shown in Figure 6 (bj) is shown in Figure 9 (
The pattern shown in bl can be displayed in reverse and can be regarded as one piece. Furthermore, when the ff-mark pattern in FIG. 9(b) is divided into horizontal line molecules, it becomes eight line segments (47a) to (47h) shown in FIG. 9(c) K. Also, the lengths of line segments (47a) to (47h) are 1 pixel and 3 pixels, respectively.

Assuming 5 pixels, 7 pixels, 9 pixels, 7 pixels, 5 pixels, and 6 pixels, in this case, the repetition period in the horizontal direction is 9 pixels, and the repetition period in the vertical direction is 8 pixels. Therefore, the value shown in FIG. 10 π is set to the upper 9 bits of the address mark "to address μ" of the memory (22) shown in FIG.
01, then register (20) Vr value ['', and Vr 7th register (35) ff value 1'8'' respectively) L, 1, as shown in Figure 11. So, in the equation, gill 11. if3. The intersection of the line and the polygon (
Rks) and (P&E) from the minimum value of k to the maximum value of 1. That is, it is chanted sequentially from 1 to 1 = yL'' to 1 to -y11'', and the counter (19)-i shown in FIG.
Increasing by 1, the line segment is doubled, solid! :5π,
In the graphic display device of the present invention, when displaying lines in various shapes, the inside of a polygon or closed curve can be filled in with various shapes i, r (7). , j'i!+i point (7) jil with line segment division f
[79'>) Process ljl i omitted f RukotoK, f,
Excellent for high-speed display
It has this effect.

↑6, the above-mentioned one implementationffJKOi℃ is the specific device i'i li71+'Z <Fll Vr",)
Explanation 1. However, this invention solves these (1(・l,!
(Needless to say, there is no such thing as 戊f'lJ KliN determined.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional graphic display device, FIG. 2(a) is a line segment diagram for display, and FIG.
bl is a flowchart of conventional processing when showing a line segment in FIG. 2 (al is a diagram of a polygon to be displayed,
Figure 3 (b) is a pattern diagram to be filled in, Figure 6 (c+ is a power line diagram displayed after the filling process πO6,
5 is a block diagram showing the basic configuration of the present invention. FIG. Figure 7 is a block diagram of the line diagram generation circuit, and Figure 8 [
Figure 8 (bl is an operation table showing the operating conditions of registers and memory in the figure filling circuit; Figure 9 (al is Figure 2 (
al K line segment diagram, Figure 9 (bl is a pattern diagram of one cycle,
Figure 9(c) is a line segment diagram in which the pattern shown in bl is divided into line segments, and Figure 10 is a diagram of the contents of the memory that stores the pattern shown in bl, Figure 11i. , E7, I)
=), ÷-・row 1. c 5 For the time being, this invention is a flowchart for such a device. [Of 21 pages, (ri is a monitor, (2a) to (2c) t-j
Buffer memory, (4) line segment pixel point conversion circuit, (3
) is a register that stores color information, (15) is a figure paint 9
Crushing circuit, (19) and (34) are counters, (20)
, (35) &1. (21) and (36) are coincidence detection circuits, (22) are memory for storing 812 red numbers, (26) is a line diagram generation circuit, (24) is Control fin1 circuit, (3Ll), (33
), (37) is Hirefta, (32) is remainder circuit, (38
) & Eand Gate. 1. C. The same reference numerals in the figures indicate corresponding parts. Kuzu! [! J Shin - Figure 2 (0) (b) Figure 3 (0) (XL, yL) (b) (C) Kan 4 Copy 1 Figure 8 (0) ) 34) Figure 9 (0) ( b) 1/-47(a) 47(b),,,- ”-47(c) 47(d) Pano □ ~47Te) 47(f) A- to 474g) 47(h) N-12th Figure 10 Figure 11L Masaaki Wa'koura (Voluntary) '1.
t4 57-174121 No. 2, surprise) January ()” (
l T'+, 1 with graphic meeting display device 31 Yamaichi ^-4 old IGr'l! ,! H series f41'it'1
-71'114jI person 11- Location: Dongzhuo [・
-1112ffF, 3>-j name of 111th ward A (
6 (For: Ryoden Isoshikikai to 1゜ generation non, It piece + l +
f: Sambu 4th J A Person 11: Tokoro Higashi l; Toku■・dai 111 Ward Kuunouchi', l112 On No. 3 5 Four layers subject to correction (1 A ('s [Invention 11' to 11 H1^ IV4 and drawings of M-1. 6. Contents of amendment 1) A
(Corrected as IV J. 2) Ming full 14th 600 z io? J's r CP
&s) TOZZ〕と'' is corrected to (' (tea), l-と''. 6) Specification (line 1200, line 5, ``■mo'' is changed to r k J
Correct Category 1. 4) Correct No. 1 of the drawings by adding one note in the appendix [-Drawings 6]. 5] Figure 2 of the drawings 1. 4th (Support 1. Figure 8 and 11
Correct the figures according to the attached drawings. Above Figure 2 (0) Figure 4 Figure 8 (0) (b) 1. C'l: Written by Masa Ura (spontaneous) #: i, i'
l' Ii length 'l';' 111! N1 ・B l
'l table, Jζ '111:+1t,'i 57-1 74 1 2 1 No. 2 Buko November 8th, Graphic-display only 3, 1+I! [4 old, 1 agent 5, drawings subject to amendment. 6. Details of the amendment 1) Figures 7 and 11 of the drawings will be amended in the attached revised drawings. From then on

Claims (1)

[Scope of Claims] Request 1) A register for storing the shape of a line for one cycle, and a register for storing the shape of a line one cycle at a time, in order to display various reduced figures and straddle plane figures that have a circumference of 1). 11
A line figure generation circuit having a function of selecting 1i'i order is generated by this line figure generation circuit. , p; -i'' tb Function is provided with a figure filling circuit that performs rl f here and 't iff sign and -Jro graphic display technique G,?. , a counter, a register, a coincidence detection circuit, a remainder circuit, and an AND gate.
A graphic display device according to claim 1. (3) An ir that makes a figure filling circuit by a counter, a register, a coincidence detection circuit, a memory, a case law circuit, and a line figure generation circuit as 11 yen,
'jFrClaim 1'The graphic display device according to item ff12.