JPS5962934A - Output control circuit of integrated circuit device - Google Patents

Abstract

PURPOSE:To make a drive signal of an external device to a constant frequency at all times by frequency-dividing a system clock corresponding to frequency and selecting only the frequency dividing output of a specific frequency in the frequency dividing output based on the clock switching signal to output the selected output to the external device. CONSTITUTION:A clock signal is outputted from an oscillator 10, a clock SC-b frequency-divided into 1/2 at a D type FF20 and a clock SC-a from an inverter 14 are selected at a selecting circuit 40 with a clock switching signal SL, and a system clock SC is inputted to a frequency division circuit 60. Further, 1/2<7> and 1/2<8> frequency dividing outputs from the circuit 60 are inputted respectively to a selecting circuit 70. A clock switching signal SL in response to the processing state of system from an operation control circuit 30 is applied to the circuit 70, and any frequency dividing output is selected based on the switching signal SL, and applied to an AND gate 81 inputting the output of a buzzer signal output control circuit 80 to make the frequency of a buzzer drive signal BZ constant.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to an output tljf control circuit of an integrated circuit device such as a one-chip computer, etc. Based on the system clock whose frequency changes, it is built into an output circuit that forms and outputs an external drive signal with a surprising frequency.

[Technical background of the invention and its problems] - In digital Il'i'&amp; using an integrated circuit device,
The frequency of the system clock is changed depending on the processing state to reduce power consumption.

For example, in the Shoko 2 tabletop Bt car Iso, the frequency 7JIM of the clock that is used in each cycle of the Hamagai cycle and the displayed cycle is changed, and the system clock during the Enson cycle and the system clock during the displayed cycle are conveniently changed. I understand. In other words, it affects the calculation speed.1. When the clock is displayed, the frequency of the clock M, lower the number and turn off tk kl
'This is a method to reduce force.

However, if such a system is adopted, there is certainly an advantage in reducing power consumption, but what about this system clock?
When trying to use it to drive external equipment, there was one problem.
yields 1μ8-. In other words, even when the external device 5 is being driven, the frequency of the suspension system clock that constitutes the drive signal of the external device changes due to the frequency of the above-mentioned circuit device itself. good'
Indeed, rxI/'1-+JL[ is C.6. 1ri1
1. If the external device is a buzzer, the tone of the buzzer will change depending on the change in the frequency of the clock. In order to eliminate such inconveniences, conventional methods have been to drive the external carrier while the system clock is constant, or to handle changes in the system clock on the external device side. 1 piece.

[Object of the Invention] This invention was made in view of this more practical matter, and even if the system clock is
Even if there is a change within the system, you can safely move external devices and equipment to 7S 1,! and 4J' day circuit - the output of the paper i11 1 time, 17i';IJ', -! − The purpose is to

[Summary of the invention]

In other words, the present invention provides the following advantages: when forming a drive unit for an external device based on a system clock that is switched between two frequencies of 44 by a constant clock switching signal of 19r, *
(j) the frequency division of the system clock with different frequency divisions respectively corresponding to the two base frequencies; 9 of each of the different frequency division outputs; By selecting one item at any time based on the clock signal and outputting it to the external table device,
ll114 This is an attempt to control the output so that it depends on a constant frequency and 7 by suspending one ringer No. 18 of one external sound device.

[Embodiments of the invention]

Hereinafter, the output 1ti1. of the nesting circuit device according to the present invention will be described.
The vertical circuit will be explained in detail according to the embodiment shown in the trend diagram.

Fig. 1 is a circuit diagram showing the implementation of the output control circuit according to this invention, and in particular, a one-chip microcomputer with a pre-operation No. 1g output terminal is used as an integrated circuit device. Example:

In the same figure, the oscillation unit 1 () is an external crystal J.
and the innovators 12 and 13 inside the chip and the resistor R1.
゜Crystal 1 composed of R2+ R3, R, s
It is a dragon circuit, and this circuit V serves as the source of the system clock. Most of the source excavation signals generated in the Kamomebe IO become the buffer [4 fff'r clock 5C-a, and this clock 5C-a is also connected to the D-type flip-flop 2U.
It is frequency-divided from VC and logically inverted by an inputter 2'' to become a clock 5c-b. The Hama 4-kan control circuit section 3o responds to the processing status of the system, and depending on its internal contents, these clocks S C-a and Clock 5c.
-b outputs a clock switching signal SL that selects one of the clock switching signals SL.1. If the processing state of the system is in the calculation cycle period, this clock cutoff signal SL is set to still level at the cooking level, and the cycle period +
That is open in i41, ia 1g SL 1,1I
Ii theory level is considered low. inverter 4], AND gates 42, 43. The selector circuit 40 constituted by %- and OR gate lI3 is nil:4e,
iii based on the control signal Sl, the clock S C-a
4 or 5c-b and output the selected clock as the system clock SC.
Do n. 4 [In other words, if the ir+ notation lock switching key signal SL is at the surface level at the processing level, the clock 5C
-a is output as the system clock sc, and each switching issue SL is l! +If the level is 1 Mr. level, the clock 5c-b is output as the system clock SC.

The system clock 2 set' outputted by this
r,, the processing status of each system! To my father-in-law) 76 years ago 1
1 Do not send power to the part A that is not displayed or the display section, etc.
It has an asynchronous counter configuration consisting of an innovative flip-flop 6j or half 68, and performs an operation of sequentially dividing the frequency of the system clock SC from 4 to 78. That is, from the output of the D2 type flip-flop 61, the system clock 2
The system clock 5C0)/22 frequency divided output is obtained from the output of , and the same goes for vCDq flip 70 tube 63,
From 64, 65, 66, 67, and 68, the system clock sc is 3, /4, 5, white, and shift, respectively.

2222 , Y is obtained.

However, the output of the frequency dividing circuit 60 in this 7+1I89131r is the D-type flip-flop 67 minus 7.
Two divided outputs are selected: the frequency-divided output and the '/s frequency-divided output of the D-type flip-flop 68.
0K manpower is required. This selector circuit 70 selects and outputs one of the above two branch outputs based on the above-mentioned clock signal/1 key number SLK, and outputs the output of the D-type fritz flop 67 via the above-mentioned input terminal 71. Inversion of the 7th branch output and the clock cutoff SL 18
The AND gate 73 uses human power as the input signal, the AND gate 74 uses the /28 frequency divided output of the 0-type 7 limp front 68 that outputs the innoguita 72, and the clock cut-off signal B SL as human power. The OR gate 75 receives the output Q of the doors 3 and 74 as input. Then, the output of the selector circuit 70, that is, the output of the OR gate 75 is outputted by the AND gate 81vc, which outputs a buzzer signal 1Ijll (logic 4* is taken from the signal BO output from the groan circuit 80, and the signal BO is at +1 level). Buzzer 1 drive signal BZ is output under certain conditions.

In addition, the above-mentioned 81 hard D type flip 70zzzo 61no-
! I5.68 is reset to the groove chamber based on the reset signal outputted from the reset circuit 5o.

The operation of the entire circuit of this embodiment will be briefly explained with reference to the time chart shown in FIG. However, for the sake of clarity, here, the operation of this embodiment circuit will be explained separately in the following two cases.

I) When the clock cutoff signal SL is still at the level (period T1 in FIG. 2) This state is during the so-called calculation cycle period, and the clock 5C-a with the same frequency as the original oscillation signal is sent to the selector circuit 4.
0, and this clock 5C-a is output as the system clock SC (see Figure 2+a+).
. Therefore, the output of the inverter 71 is
The frequency is divided by a frequency division ratio of 7 (see Figure 2, Figure 1),
Further, the output of the I/NO-72 is obtained by dividing the frequency of Ik by a frequency division ratio of /280 (see FIG. 2, 1g+). In this case, since the clock signal SL is at +'lZ+ level, the selector circuit 70
output, that is, the original axis (Tatsu 1 number divided by Shi 8 minute Ird ratio)? rJ is selected and output from the OR gate 75 (see FIG. 2, 1h'l). Then, No. 18B
Since O is also at the It% level, it is suspected that the buzzer i+ is a signal obtained by dividing this source signal by /28f as the signal BZ for movement 1 (see Fig. 2).

11) When clock off 4” Ali No. SL is low level (
In this state 11, the so-called display cycle is in progress, and the clock 5C-b obtained by dividing the frequency of the partner oscillation signal by 4 is selected by the selector circuit 40Vc, and this clock 5C -b is set as the system clock SC (see tdl in FIG. 2).

Therefore, the output of Inno-Yu 71 is the one obtained by dividing the original oscillation signal with a frequency division ratio of 480 (see Fig. 2 tfJ
), and the output of Inno-Ni-Yu 72 is 1
The frequency is divided by a frequency division ratio of 79 (see FIG. 2, 11gJ). In this case, since the clock switching signal SL is at a low level, the selector circuit 70
In other words, the signal obtained by dividing the source @11 signal at a frequency division ratio of 1/8 is selected and output from the OR gate 75 (see 1(9) in FIG. 2).

Since the signal BO is also at a high level, the buzzer l
1M! This source light eye is divided into 48 stations as the auxiliary signal BZ (21st 11ll illumination).

In this way, whether the processing status of the relevant prefectural circuit device light is a calculation cycle or a display cycle), the frequency of the signal is divided by a frequency division ratio of 48 as the buzzer body movement information signal BZ. You can get something.

Therefore, when it is desired to output the buzzer check signal BZ to the external fR finger, if the signal BO output from the Zuzer output width 11 circuit &) is set to the level,
4 o'clock, 9 [The above buzzer is activated for the desired time - i RZ
can be output with a constant circumference.

1. c o'214Σ ￥1. In the example circuit, there are two types of frequencies, so ``LJ'' and one system clock are used.
zBy opening it by dividing it into a different frequency by 1,
-jF IIIUi=Ichihoshi's 11'' will become obsolete'): 1jll 111ti, but 2 (city)
, [1's 11''6 + 47.l'l ICpl (Razu341 y7.1 fxa sword, --) Even if it is a collection of system tarok with circumference rW uncle for IJZ + lt times 1 design -- It goes without saying that this invention could easily be completed in less than 1'1:3 years.

The above-mentioned East KD 1/11 4] Road Q died, and the buzzer 1j (be 1° 1 s 1; Although the frequency division ratio inr is set to be output as G<l, it is of course arbitrary, and it is sufficient if the frequency division ratio inr is set to 16 and then transferred to the external equipment to be used.

Furthermore, in the fruitful example circuit that was broken in the 11th number 1, the frequency division is 1! : J i total 660;14. : Non-identical J1. consisting of 9Y D type flip-flop. JJ type counter groove formation is adopted, but this frequency division is 1! ,! Those who operate the Nij System Talonk with the In formation of the J road (each frequency of the Enostem clock x 1, 1, 2, A ratio), If it is the same for other circuits, and has the same function as the circuit shown in Example 1-1, then Any other l'17tIi may be used.

By the way, the first car was VC'd! 7y kr
In this case, the external word 5 is sent to the buzzer j4 and the buzzer j4 is moved to the buzzer j4 →)
However, in addition to using this invention as a J4, it is of course possible to use any other type of device for <15.

[Effect of the invention J As explained above, according to the present invention h) According to the output of the Toko circuit device, the frequency 1-k of the system clock, which changes depending on the processing frequency, can be transmitted to an external device. On the other hand, since the internal part of the 14ξ 1st generation device 6) is outputted as a constant frequency without any trace, the external part can be used to improve the quality of the equipment. It will be more than I can do.

[Brief explanation of the drawing]

The first disadvantage is that the present invention does not include the structure of the integrated circuit device' (the output lI+lI circuit of the actual circuit 1). - It is a time chart showing an example of the adult operation of the column circuit.
0.70...Selector, 5()...Reset circuit,
60... Frequency division 1 separate path, 80... Buzzer signal output 11
i11 f Same day 1 omitted.

Claims (1)

[Claims] A clock signal excavator, and a clock switching signal for specifying the switching of a system clock, which is supplied according to its logic content in correspondence with two different processing cycles of an integrated circuit device. a first means for outputting a signal of logical product with a clock value number written in NiI; and a branch station of the clock signal (m is a natural a);
a second means for obtaining a signal output of a combination of the signal output of the second means and a signal obtained by inverting the clock switching signal; and 1g of the first and third means. An n-stage (n is a natural number) frequency divider circuit that is supplied with a signal output of the logical sum of the signal output, and a signal that is the logical product of the signal output of the next stage of this frequency divider circuit and the previous ml clock cut signal 1g. output and a fourth means for outputting a signal of the logical sum of the signal output of the logical product of the output of the 1h signal of the low m iMth signal and the inverted signal 1g of the clock switching signal 1g; An integrated circuit (
b) Doso Hitomi no Dekani, ill, 1III L! J.M.
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