JPS5962966A - Data transfer circuit between CPUs - Google Patents

Abstract

PURPOSE:To transfer data between two CPUs with less queuing time, by controlling a switching circuit by a signal, which is generated by discriminating memory states of two CPUs, to connect memories to each other. CONSTITUTION:When a timer is started, CPU2 checks the inversion state of an output Q of an FF12. If it is not inverted, data is not taken in; but if it is inverted, the state of a memory 8 is checked, and the error processing is performed when it is wrong. When it is correct, data is taken in from the memory 8. The CPU2 processes taken-in data and writes it in the memory 8 again by a write instruction. Thereafter, the CPU2 issues a switching request to connect the memory 8 and a CPU1. Then, outputs 8A, 8B, 9A, and 9B of output ports of memories 8 and 9 and the output Q of the FF12 are inverted. Consequently, the CPU1 is connected to the memory 8 and the CPU2 is connected to the memory 9 through a bus by a switching circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a take transfer circuit between C P jJ in a plurality of CIs.

An example of a control device equipped with a plurality of C11Us is a control device for a multi-joint robot. In the control device for an articulated robot, for example, 1.i) Old 111 articulated robot yl
・Hekii☆Okima's complement [IY Hesitation 1]
In addition, the precondition 171 of this interpolation training calculation, the +riζ coordinate conversion that converts the can 1 vator of the rectangular position (vote system) into the position -7-k of the multi-joint system, and the interpolation aIn of the position data of the multi-joint system. Is it necessary to do a lot of 8-point work]?If you use a CI'tJzunawai microphone [J Brosenza] in such a control device, you should use one CI'tJ and two rivers and two. However, there is a possibility that -Σ-Ichiyo cannot be processed within the time required for control. You will need to do 1 and 11 minutes. 1 like this
7M K
Become.

And, initially, -tsu (7) CP IJ or others (7) C
I' jJ K 7 accesses (7, Jl imports data from its internal memory, that is, register section, but it is one CI) [Even if J requests data import, other CIs) jJ must respond to this request. (other CI) U
It is often necessary to wait until someone responds, which often results in a long wait time, which is inefficient.

Therefore, one CI and other CI) LJs are connected so that they can share one independent memory, and one
・Data processed by the other CP LJ is stored in this memory)
A data transfer circuit is also used that allows data to be imported from either C11II after it has been imported, but none of the
1 or one of the CIs) [When J is accessing that memory, even if any of the other CPUs tries to access it, it will have to wait until the access by the earlier CI) tJ is completed. Well, it still requires waiting time. When using the FIFO method as memory, for example, instead of reading data only from the address where the necessary data is stored, it is possible to read all the data in the order in which it was written, and then import only the necessary data from among them. As a result, the waiting time could become noticeable.

This invention was made with the above-mentioned points in mind regarding the data transfer circuit between a plurality of CIs, and is a data transfer circuit that allows data transfer between two CPUs to be performed with less waiting time. The purpose is to provide transfer circuits.

In this invention, one memory is made to correspond to each of the two 'cp LJs, the states of each of the 11 memories are determined, an il control signal is generated, and the switching circuit is controlled by this control ll (indicator). A data transfer circuit is configured to connect seven CPUs and their corresponding memories.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a diagram of this embodiment. @1 In the figure, 1 is the first CI'LJ, 2 is the second CP j, J, and executes the program controller l that controls this data transfer circuit together with the RAM and ROM (not shown).

3 is the first switch, and human power (till is the first switch (
The output (tl,l) is connected to the first memory 8.When the control signal is 1, it becomes conductive.

4 is the second switch, and the input G11l is the second CI
) jJ 2, and the output side is connected to the first memory 8. Conducts when the control signal is 0.

5 is the third switch, the input terminal d, the second Cp t
+2, and 113 power (1111i, J: connected to the second memory 9).When the i control signal is 1, it is conductive.

6 is the fourth switch, which is connected to the first CI' (, Ti, and 111 is connected to the second memory 9; it is conductive when the control signal is 0). .

7; 1 switching circuit, which in this embodiment consists of a first switch 3 to a fourth switch 6; S'f;

8L [first memory, via first switch 3;
It is connected to the first CPU Ui via the second switch 4, and to the second CI U2 via the second switch 4.

The first memory 8 has an input port and an output port.
It is AM. When the output of the output port 8A is 1, the output of the output port 8B is 0, and when the output of the output port 8A is 0, the output of the output port 818 is 1. Switching between these states is performed by writing from the first CPU.

The output port aAt/i is connected to one input of the first AND circuit 10, the input port 8) of the first memory 8, and the input port 9FK of the second memory 9. In addition, the output port 813 is connected to the second A N J) circuit 1
1, the input port 8C of the first memory 8 and the input port 9E of the second memory 9.

9 is a second memory, which is connected to the second CPU 2 via the third switch 5 and connected to the first memory P tJ i via the fourth switch 6; 'ic is there.

The second memory 9 also has an input port and an output port.
It is M. When the output of the output port 9A is O, the output of the output port 91) is 1, and when the output of the output port 9A is 1, the output of the output port 9I3 is FiO.

Control of these states is performed by writing from the second CPU.

And, the output capo) 9A is the second A N l) circuit 11
another input of the input port 9T of the second memory 9)
and the input port of the first memory 8) 8FK is connected.

'Also, the output port 9J: J - the first A, N1) another human power of the circuit 10, the input port 9 of the second memory 9
C and the input bl#-1 of the first memory 8, 8E.

10 is the first ANL) circuit, and one human power e'
It is connected to the output port 8A of the first memory 8, and the other input is connected to the output port No. 91 of the second memory 9. The output is connected to the set manual S of the Soliso non-flow knob circuit 12.

11 is a second A N D circuit, one input is connected to the output port 9A of the second memory 9, and the other input is connected to the output port 8B of the first memory 8. There is. The output is connected to the reset input of the flip-flop circuit 12.

12 is a flip-flop circuit, and the first ΔN I)
The outputs of the circuit 10 and the second A N I) circuit 11 are connected to the first switch 3, the second switch 4, the third switch 5 and the fourth switch 6. At the same time, it is connected to input ports 8G and 9G of the first memory 8 and the second memory 9, respectively.

13-1iff control 8 is a generation circuit, and in this embodiment, d: the first A N +) circuit 10, the second A
N+) circuit 11 and a flip-flop circuit 12.

The operation will be explained below based on the configuration described below.

In this embodiment, the data of the first CI' IJ l is transferred to the first memory 8 by starting the timer at regular intervals, and the data of the first CI' IJ l is transferred from the first memory 8 to the second CI
2 and processed/After that, 111 degrees, it is transferred to the first memory 8, and then 3t'I, 1 l) U
1 shows the portion of the take that is transferred from the first memory 8 to the second CI U2 and then transferred to the first memory 8 again. Then, this part of the data transfer is performed by the programmer of the second CI' tJ 2, and after the take transfer is completed, each CP
Change the connection relationship between U and each memory (ヅC1 2nd
This will be explained with reference to the flowchart in the figure.

First CP [J i and 1. When the boot process is performed and the first CI)'tJ i and the first memory 8 are connected, that is, when the q output of the Sorisozov 1 knob 12 is 1, the first memory is transferred from the first CPU 1. After the IJ, 8K data is transferred, from the first CP IJ 1. so that the first memory 8 is connected to the second CPU 2,
From the second CI')U, the second memory 9 is transferred to the first (CI')U.
:P [I'I have requested UJJ change to be connected to J. That is, the output of the output port 01813 of the output port 8A of the first memory 8 is 1, and the output Q of the output port 9A of the second memory 9 is 0, and the output of the output port 9A of the second memory 9 is 0. ``It is assumed that the 9th output of the J knob 12 is set to O.

Therefore, by starting the timer, the output of the second cp4J2i flip-flop 12 is inverted from 1 to 0 by reading the capo 1 of the second memory 9 using J41 (step S1). Therefore, data will not be captured unless it is inverted. Inversion I~11 is the first
Whether it is possible to read data from the memory 8 of
In other words, the second memory determines whether the state of the first memory 8 is correct.
read through the manual boat of memory 9 (step S
2). The reason why this condition is not correct is due to an error.''Kosa, 11
(Step ν)"S6), 1", that is, in this case, the output of the output port 8A of the first memory 8 is O1 output capo-1
・If the output of 813 is 1, d', the first
The data is imported from the memory 8 of the memory 8 to the second C1, 2 (step S3).
The data that is about to be imported into the second memory 8 is processed, and during this time there is no request to disconnect the first memory 8 and the second CI' tJ, and the processed data d] The data is read into the first memory 8 by the read command. (Step S4). After the peak, the first memory 8 is transferred to the first CI'
II makes a switching request to connect to i (step S
5). As a result, the output iJi of the output port 8A of the first memory 8, the output of 313 is changed to O, the output of the output port 9A of the second memory 9 is changed to 0, the output of 0.913 is changed to 1.1, and the output of 313 is changed to 0.

In this case, the output kl 1 of the first A N +) circuit 10 is the output of the second AND circuit 11, which becomes O, and the outputs of the circuits 71 and 71 are connected to the output 12 of the synchronous signal (not shown).
-tq is input to the flip-flop I block 12, so it is inverted to the q output trii of the flip-flop 12. Therefore, the switching circuit 7 causes the first (7) CI
' U 1 is bus connected to the first memory 8 and to the second memory 9 .

This completes the execution of the second CI) tJ 2 transfer blog, and from now on, the data is transferred from the first memory 8 to the first memory 8.
CP u 1. The data acquisition from the first memory 8 to the first CP Ll l and the data writing from the first CI U l to the first memory 8 are performed in the same manner as described above. CP (Summer 1
It is carried out by the execution of Zorograno.

As described above, the hetator of the first memory 8 is transferred from the first 01'U i, and the data of the second Ct'u2 is further transferred from the first memory 8.
We have explained the operation of transferring the data to the first CI', U1 via the first memory 8, and then processing the data. After transferring the data to the first c p U 1 via the memory 9 and processing the data, the data is transferred to the second c p U 1 via the second memory 9.
The operation when transferring to i'u2 is the same as described above, and these transfers are not limited to being carried out to China and Germany, but can also be carried out at the same time.

As mentioned above, in this embodiment, data transfer: JX &
:l, Since it is performed at regular intervals by a timer interrupt, even if the data processing time of each CI) U is different, the data transfer and the data processing in CI) U will not overlap. still,? A1 C11U i table 1 memory 8 and second CPU 2 and second memory 9
IRJ when the first CP 1, 1 i and the second memory 9 and the second CI' Ll 2 and the first memory 8 are connected respectively.
The change is performed synchronously so that the first CI)
is the first memory 8r (when reading/writing, the second CP
[Since it is impossible for 72 to try to read and write to the first memory 8 at the same time, the first CI) Ll i
This has the advantage that data transfer between the CPU 2 and the second CPU 2 can be performed without waiting time. - Also, since RAM is used as memory, only the necessary data can be imported, which has the effect of reducing the reading time to 1r.

In other embodiments, the first CI) [J 1- or the second CP tJ 2 may optionally be the second CI
2 or the first c 1'u 1, and when the other side's (:PU responds to the interrupt, it switches as described in 011 &4-"i and controls the switching circuit. It is also possible to perform data transfer.And if it can respond to interrupts, it is also possible to perform data transfer in this case.
) when Ul is being read into the first memory 8, the second
CI) LJ 2 reads simultaneously into the first memory 8 t'
), data can be transferred without waiting time. ! :＾Cure the effect.

Furthermore, when the output of the free-lag flop circuit 12, that is, the output of the control loop generation circuit 13, is 0, the first CI' tJ
i and the first memory 8 and the second CPU 2.i.
L-to complete the bus connection of the second memory 9; to read the switching states of the first switch 3 to fourth switch 6 from these switches;
It is also possible to read the completion of the reading from CI) LJ l and the second CI) (J 2 to the first memory 8 or the second memory 9 between the CP 17, etc.) The effects of either embodiment are similar to those of the previous embodiment.

In addition, as another embodiment, as shown in FIG. 3, this data transfer circuit is used in several units and is implemented as 1111 paths for data transfer between microcomputers in two or more slots (three in this embodiment). This is also possible, and the effect in that case is similar to that of the previous embodiment.

As stated above, the implementation of this invention is not limited to the above-mentioned embodiments, and replacement with equivalent components is possible, and even in that case, it falls within the technical scope of this invention. .

As detailed above, according to the present invention, two CP
It is said that data transfer between U can be performed with less waiting time! The effect of having one is demonstrated11.

[Brief explanation of the drawing]

The drawings are illustrative of embodiments of the present invention; FIG. 1 is a block diagram, FIG. 2 is a sorJ-diagram, and FIG. 3 is a block diagram. In FIG. 1 and FIG. 3, 1...first CPU, 2...second C: P jJ
, 7... Reno replacement circuit, 8... First memory, 9...
Second memory, 13...Control (No. 1i generation circuit. In FIG. 2, 14...Third CPU 115 Third memory, 16/Fourth memory. Applicant ShinMaywa Industries Co., Ltd. Agent I (11 (and 1 other person) Figure 1 Figure 2

Claims (1)

[Claims] (1) If the first CPU and the second CI) jJ, the first memory corresponding to the above CI) L and I are connected to the second memory (+iii L, the control signal is manually input). 1 horn exchange circuit η~ and the first C11U and the first
If the memory and the second CPU are the second memory, the first CI" tJ and the second memory and the second memory and the second CPU and the first memory are interchanged.
Take transfer circuit between CI) j and JJ. 2. The control signal controls the first memory and the second memory.
A signal indicating the state of each memory output by each memory.
The signal should be output from the control signal generation circuit that is manually operated!
- The data transfer circuit between the CPUs according to claim 1. (a) The take transfer circuit between ni[CI' and jJ according to claim 1, wherein the control tlj signal is output from the first CI' tJ and the second CPU.