JPS5962999A - Apparatus and method of generating trip signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to measurement, and in particular to the need to accurately and continuously extract test data during the operation of a measurement device or the system in which the measurement device is operating. Regarding measurement in environments where A particular application of the invention is to
This is the case for level detection, such as in an operating atomic couplet or process where it is necessary to detect the occurrence of an analog signal that falls below a predetermined threshold level. Failure of monitoring and test equipment cannot be tolerated in these critical environments. Therefore, a device incorporating fail-safe testing techniques must be implemented.

Description of the Prior Art Analog trip devices are relatively well known in metrology technology. Modularization of such devices is also well known. For example, in the field of atomic couplants, Rosemont Corporation
A series of analog trip modules, called analog control units, are manufactured by tCorporation.

However, until now no analog trip device is known that can be tested at any point in time, particularly during normal system operation. As a result, extensive efforts are currently being expended in off-line testing, which is often performed on such devices.

Therefore, there is a need for an analog trip device that can be tested while in operation. In particular, there is a need for a modularized analog trip device that is self-testable without disrupting or degrading the proper functional operation or integrity of the device.

SUMMARY OF THE INVENTION In accordance with the present invention, a short test protocol (Proiocol
), and provides an apparatus for precisely detecting analog levels that automatically returns to the precise state that existed before implementing the test protocol. A time on the order of /millisecond is provided for the injection of the test pulse, the settling time and the return of the device to the initial state. Proper recovery of the device to its initial state prior to testing is important to avoid state ambiguity due to programmed hysteresis of the analog trip level. According to the embodiment, the analog
The knob module has a preprocessing circuit coupled to the analog signal source and the diagnostic test circuit, and a circuit module coupled to receive signals from the preprocessing circuit. The module includes a plurality of trip indicators and a circuit module for detecting gross failures. The diagnostic test circuit is also operative to provide a test signal to the preprocessing circuit for testing and resetting the trip indicator.

These and other features and various advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

DESCRIPTION OF SPECIFIC EMBODIMENTS Referring to FIG.
A block diagram of trip module 1o is shown. Transducer means are coupled to the preprocessing circuit 14 and provide analog function input signals.

This signal is sensed by the trip circuit 18.20.22 of the analog trip module 10.

The transducer means 16 has a current source 24 coupled to the transducer 28 via an isolation circuit, e.g. a magnetic coupling 26. A typical transducer is a hydraulic quadrature transducer that adjusts the resistance to change the current. The output of transducer 28 is coupled to a functional input 30 of preprocessing circuit 14, as described below.

Central test control system 12 provides automatic or manual diagnostic function control signals to the analog trip modules. The control signal is the force on the card selection line 32.
A clock signal 35 is included to control the mode select signal and test condition signal on the data bus 34, as well as the data input and data output rate. The diagnostic circuitry of the analog-to-trip module 10 includes an injection register 36 for storing digital values identifying test conditions, a monitoring register 38 for recording the gage value of the test result, and an input register 38 for storing the digital values identifying the test conditions. has first and second off-scale trip sensors 40 and 42 for sensing analog signals over a range of .

The press-fit resistor 36 also has three command bits: a trip up signal to set the maximum overscale signal, a trip down signal to set the maximum underscale signal, and an out-of-scale trip sensor 40.42. Stores the global fault reset signal for resetting the device.

The monitoring register 38 is connected to the module 10 as described below.
provides temporary digital storage of selected output function instruction values. This monitoring register 38 is connected to the serial data output line 4
8 provides a serial data output to a central test control system 12.

Analog trip module 10 in combination with central test control system 12 and preprocessing circuitry 14 operates as follows. In normal functioning, a switch 50 within the preprocessing circuit 14 transfers the signal from the transducer means 16 to the common human power bus 5 of the analog trip module 10.
Send it to 2.

In this case, the levels of the signals thus supplied are respectively 1. 1st U and 3rd trip level sensor 1
Detected by 8.20.22. In addition, the input bus 52
The above analog signal is propagated through an analog trip module to an analog output 54, which allows trip functionality to be extended to multiple systems in parallel. Meanwhile, the output status of the trip level sensor 18, 20.22 is transmitted to the monitoring register 38. This status indication signal is clocked and transmitted via serial data output line 48 to the central test control system to enable continuous monitoring of the status of trip modules 1B, 20, and 22. .

According to the test protocol, it is necessary to provide a fraction of a millisecond to perform the test of each element of the analog trip module 10(7). The entire system of analog electric trip module 1° is such that a /millisecond signal is connected to this analog trip module 1°.
is designed not to produce any meaningful functional response, except for diagnostic purposes, even if transmitted through the A low pass filter may be used for this purpose on selected 4a of the output channels of the system.

To initiate the diagnostic sequence, the central test control system 12
inputs the test conditions to the injection register 3 via the data input line 34.
6. Injection register 36 transmits a trip up or trip down signal via line 37 or 39 having a duration of up to about 1/2 millisecond. When one of trip signal lines 37, 390 is active, the input of switch 50 is captured and an analog signal is applied to input bus 52. /millisecond pulses at least one of the off-scale trip sensors (40);
and causing each of the trip modules 18, 20, 22 to generate a positive indication signal. These instruction signals are transmitted to and temporarily stored in the supervisory register 38, and then serially read out to the central test control system 12 under conventional clock control.

A calibration/
Function line 56 provides an indication of the mode of operation of analog trip module 10 to central test control system 12.

Referring to FIG. 2, seven trip indicators 18, the first
A circuit diagram of a third off-scale trip sensor 4o and a third off-scale trip sensor 42 is shown.

Trip indicator 18 is a precision positive feedback latch circuit with adjustable hysteresis to prevent loss of the trip indicator signal and off-scale trip sensor 40.4.
2 and in parallel to a common input bus 52. In an embodiment, the input to trip indicator 18 is voltage/
It is fed via a current conversion resistor 58 to a summing junction 60 of a precision level comparator 62. This summing junction 60 is associated with a precision reference level that is adjustable via voltage divider network 64. Comparator 62 is designed to trip if the voltage at node 60 falls below the voltage at node 66. This node 60 and the non-inverting input node 66 are each connected to a clamp diode. 68.70 to a voltage reference node 67 slightly above ground potential. The purpose of these clamp diodes 68.700 is the comparator 62
This is to ensure that the input at connection point 50.66 to is never driven to a negative voltage. Therefore, during normal operation, the diode 68,70 is not part of the circuit.

According to the invention, switch control hysteresis network 72
is provided, the network 72 being coupled between the adjustable precision voltage reference and the non-inverting input at node 66. The hysteresis network 72 also includes a hysteresis switch 76. The hysteresis switch 76 is connected, for example, to a gated cuff 8 coupled to receive a human input signal from an inverter 80, a drain electrode 82 coupled to a wiper arm 84 of a potentiometer 86, and a high impedance resistor 90. M with a source electrode 88 coupled to the inverting node 66
It is a voltage controlled analog switch like an OS transistor. This hysteresis network 72 also connects the connection point 66 and the connection point 6γ and therefore the potentiometer 8.
6 and a first high impedance resistor 92 coupled between the first terminal 94 and the first terminal 94 of the first terminal. Note that this connection point 67 is a stable voltage reference commonly used as a virtual ground reference. Further, the third terminal 96 of the potentiometer 86 is connected to a stable voltage reference (VuEF/VuEF/
) is coupled to 74.

The output of the comparator 62 is coupled to an inverter 100;
The output of this inverter 100 becomes the output of the analog write trip module 10. The output of this inverter 100 is also coupled to a /millisecond low pass filter 102 . The output of filter 102 is coupled to an inverter 800 Å in the gate circuit of switch 76 .

Next, the operation of the trip channel (18) will be explained.

The analog signal applied to common FJ line 52 is transmitted via voltage/current conversion resistor 58 to the inverting input of comparator 62. When the input terminal level becomes more negative than the voltage at the non-inverting input at node 66, the output of comparator 62 goes "low".
, causing the inverter 100 to trip instantly and generate a high output level signal. The signal thus generated is provided to the /millisecond low pass filter 1020 input and transmitted to the output of the analog trip module 10. If the duration of the state change signal does not exceed 749 seconds, hysteresis switch 72 will not close and the hysteresis level will not change. The comparator then switches back when said input reaches a substantially less negative signal level;
The system output indication signal changes, ie, returns to its initial state. However, a 749 second pulse is of sufficient duration to transmit the signal at the comparator output to monitoring register 38.

If the duration of the analog input signal is greater than 749 seconds, hysteretic regeneration occurs, ie, the trip level is switched to latch the output of the trip indicator to its on level. Specifically, the input signal is passed through the /millisecond low-pass filter 102 and the inverter 8.
0 to the gate electrode of the MO8 type switch 76. As a result, gate electrode r8 opens inverter switch 76 to reduce the voltage on node 66 toward the virtual ground reference at node 67. Otherwise, switch 76 remains on, relating node 66 to the voltage selected by the setting of wiper arm 84 on potentiometer 86.

The trip channel (1 day) therefore has a precisely programmable hysteresis level so that the trip indicator (1 day) can be tested without disrupting its normal operation. In other words, the trip indicator 18 is tested without causing hysteresis regeneration that would create ambiguity in the trip level.

Next, the first off-scale trip sensor 40 and the first off-scale trip sensor 42 will be explained. A common input signal on the common bus 52 is connected to each input resistor 106,1.
08 respectively. Each off-scale trip sensor 40.42 has a voltage divider network 110, 112 with adjustable trip level thresholds, each output of which is common to the output of a corresponding input resistor 106.108. Connected to a connection point. Comparator 1160 inverting input is the summing junction of voltage divider 110 and the input via resistor 106. The relatively more negative voltage is input resistance 1
06, the output of comparator 116 is triggered to generate a positive logic "/" signal to OR gate 118.

The non-inverting input connection of comparator 120 acts as a summing connection between input resistor 108 and voltage divider 112.

A relatively non-negative going input signal (toward zero volts) produces a logic "/" output to the input of OR gate 118. The trip level of the voltage divider 110, 112 is set such that an input signal applied above either of this trip level is immediately sensed for operation of any of the trip channels in the analog trip module. selected as the outer limit boundary. Whether during normal functional operation or brief diagnostic operation, each human power signal applied to common input bus 52 sets a preselected trip level for off-scale trip sensors 40, 42. If exceeded, it will be detected and indicated. Each trip-level indication signal is passed through an OR Φ gate 118 and a low pass filter 300 to a flip-flop 4.
4 and any positive results are stored. The output of flip-flop 44 is transmitted to monitoring register 3. This clip-flop 44 is reset by a signal applied from the injection register 36 to a reset input 45 (see FIGS. 1 and 2). Since there is virtually no time delay in the circuitry of the off-scale trip sensors 40, 42, the system can return from any diagnostic routine almost instantaneously.

There are two types of diagnostic routines. That is, the scale upper limit test and the scale lower limit test.

Referring to FIG. 3, a block diagram of a portion of the diagnostic circuitry associated with the present invention is shown. The injection register 36 is
Data line 34 is controlled by clock line 350jljlJ
receives serial data input that determines the test conditions for the diagnostic routine via the The clock input to the injection register on line 43 is applied through an AND gate 39 controlled by the card select signal on card select line 32. If there is no activation signal on card select line 32, injection register 36
is on hiatus. At least three output bits are provided from injection register 36: trip-down, trip-up and global reset. The test sequence is enabled by applying an enable signal on card select line 32 to the seven groups of AND gates 41 to which the output of injection register 36 is fed.

The trip up bit is applied to a first input of preprocessing circuit 14 (see FIGS. 7 and 7). on the other hand,
The trip down fist bit is applied to the first input of preprocessing circuit 14. In addition, the entire reset bit is manually reset 45 of the flip-flop 44 (see Figure 1).
be supplied to.

The normal/millisecond test order has a trip up bit; 0 other tests have a trip down bit.

Supervisory register 38 is a parallel-in, serial-out shift register with input connections to preselected test points in analog trip module 10. These inputs are for total failure, trip 1. t′″l) Tube 2
, Trip 3, Global Fault Upper Limit, Global Fault Lower Limit, and Calibration/Function.
and a card selection signal (32). This activation signal is also applied to the injection register 36. Data is serially clocked out on data line 48 to central test control system 12 (see FIG. 1). All clock functions are controlled by new data in the monitoring register 38.
The data is overramped so that it is clocked out as it is loaded into the memory.

Next, FIG. 7 shows a schematic diagram of the preprocessing circuit 14 according to the present invention. This preprocessing circuit 14 is a new switch circuit 50
The switch circuit 50 applies either a functional signal or a test signal to the common bus 52. The test signal, optically isolated by optical isolators 130 and 132, is applied to high pass filters 134 and 136. Only short duration pulses are passed to the switch 50 to prevent the device from locking into the test mode in the event of a failure of the test mode component. The switch 50 is comprised of a pair of solid state single pole double throw switches 138, 140 in the form of push-pull MOS gates.

The push-nable output of each switch 138, 140 is connected to a high impedance voltage/current conversion resistor 142, 144.
common input connection point 14 of the isolation operational amplifier 146 via
5. The input from the transducer is applied to node 145 via switch 50 by voltage/current summing resistor 148 . The transducer 28 receives power from a stable voltage source.

This transducer 28 also provides a variable current output proportional to the parameter to be sensed.

The output of the transducer 28 is fed through a calibration switch 29 which can be configured to apply a calibration current to an input load resistor 31 via a functional input line 30 .

The operation of the switch 50 is as follows. During normal functional operation, the trip up and trip down input signals are normally not present, so switches 138, 14
4 holds the inputs to conversion resistors 142, 144 referenced to ground. Input connection point 145 of isolation operational amplifier 146
is the current connection point. Therefore, under normal conditions, no current flows from switch 138 to node 145. However, whenever switch 138 is switched to the high voltage reference or switch 140 is switched to the low voltage reference, current flows to node 145.
Flow to.

In this case, the current level is selected to be large enough to negate any functional input current, thereby minimizing any effect the functional input current has on the input node 145 of the isolation operational amplifier 146. It also has a prioritizing effect. Since there is no voltage change at input node 145, switching is rapid. Therefore, tests of relatively short duration can be performed with little or no effect on the overall system functionality.

The isolation operational amplifier 14G has the function of an operational amplifier to isolate the circuit between input and output. Suitable equipment to meet these requirements is provided by Analog PC Viccs, Norwood, Massachusetts.
This is an Otsu 0 Wag type isolation operational amplifier manufactured by Inc.

The invention has been described with reference to specific embodiments. However, other embodiments will be apparent to those skilled in the art. It is the intention, therefore, for the invention to be limited only by the scope of the claims that follow.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an analog trip module including diagnostic circuitry, pre-processing circuitry, global fault circuitry and trip indication circuitry; FIG. 2 is a schematic diagram of seven trip indicators and global fault detection channels; FIG. 3. The figure is a schematic diagram of a diagnostic circuit according to the present invention, and FIG. 7 is a schematic diagram of a preprocessing circuit according to the present invention. 10...Analog-trip module; 12...
・°°Central test control system; 14...Pre-processing circuit; 1
8.20.22...Trip level sensor; 30.
・Functional power; 3G ・Injection register; 38 ・Monitoring register; 40, 42 ・Out-of-scale trip sensor; 50 ・Switch; 52 ・Common input bus; 72 ・・
. Switch control hysteresis network.

Claims (7)

[Claims] (1) In a self-test device that generates a trip indication at a precise analog level, in response to an analog function input signal, when the analog function input signal changes, a first trip indication occurs at a first precise trip level. means for generating a positive trip indication signal of: in response to the analog function input signal, the analog function input signal being maintained at a level above the first fine trip level for a minimum amount of time; means for setting a hysteresis threshold at a precise trip level of m2 of said analog function input signal; means for applying a first diagnostic level signal exceeding the first trip level at any time; and means connected to the first and first generating means to substantially control all operations of the generating means; self-testing apparatus, characterized in that it comprises monitoring means capable of functioning without causing any ambiguity between said trip levels during any operation of said generating means. (2) said monitoring means is connected to receive said functional input signal in parallel with said generating means, and said analog input signal outside either a first predetermined limit value or a second predetermined limit value; 12. The apparatus of claim 11, comprising a first trip level sensor and a second trip level sensor operative to provide a positive indicating signal indicative of . (3) an injection register operative to receive and store the injected test signal, and to supply the first diagnostic level signal to the generating means and the first diagnostic level signal to the generating means; An apparatus according to claim 1 or 2, further comprising: (4) coupled to receive a functional input signal in parallel with a diagnostic input signal and operative to send either of the functional input signal and the diagnostic signal to the generating means via a common input bus; 3. The apparatus of claim 3, further comprising input processing means operative to apply said diagnostic signal for a period of time less than . (5) further comprising storage register means coupled to said generating means, said monitoring means and said preprocessing means and operative to receive in parallel a plurality of signals representative of a response to said diagnostic level. The device described in (4). (6) exhibiting hysteresis between the first precision trip level and the second precision trip level only in response to a human input signal having a duration greater than the minimum time and trip indication at the precision analog signal level; A method of testing a device that generates a trip e for a period of time less than the minimum period of time
applying a diagnostic level signal at a level exceeding the diagnostic level signal at any time during operation of the device; and storing a response of the device to the diagnostic level signal within the minimum time. A method characterized by: (7) The method according to claim (6), wherein the minimum time is /millisecond.