JPS5963571A - Integrator for alternating current voltage - Google Patents

Integrator for alternating current voltage

Info

Publication number
JPS5963571A
JPS5963571A JP12599283A JP12599283A JPS5963571A JP S5963571 A JPS5963571 A JP S5963571A JP 12599283 A JP12599283 A JP 12599283A JP 12599283 A JP12599283 A JP 12599283A JP S5963571 A JPS5963571 A JP S5963571A
Authority
JP
Japan
Prior art keywords
voltage
integrator
output
circuit
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12599283A
Other languages
Japanese (ja)
Inventor
ゲルハルト・ル−モルト
ヘルマン・ワルトマン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Schuckertwerke AG
Siemens Corp
Original Assignee
Siemens Schuckertwerke AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Schuckertwerke AG, Siemens Corp filed Critical Siemens Schuckertwerke AG
Publication of JPS5963571A publication Critical patent/JPS5963571A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0084Measuring voltage only
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R17/00Measuring arrangements involving comparison with a reference value, e.g. bridge
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06GANALOGUE COMPUTERS
    • G06G7/00Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor
    • G06G7/18Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for integration or differentiation; for forming integrals
    • G06G7/184Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for integration or differentiation; for forming integrals using capacitive elements
    • G06G7/186Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for integration or differentiation; for forming integrals using capacitive elements using an operational amplifier comprising a capacitor or a resistor in the feedback loop

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、キャパシタンスを介して負帰還された演算増
幅器により交流電圧を積分するだめの装置に関する。こ
のような積分器は公知であり、計測制御技術如おいて直
流量を処理するため如用いられている。しかし、このよ
うな積分器は、出力制限が常に存在するだめ、またオフ
セット電圧によりドリフトが生ずるため、そのままでは
交流電圧の積分には適していない。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for integrating an alternating current voltage by means of an operational amplifier with negative feedback via a capacitance. Such integrators are well known and are commonly used in measurement and control technology to process direct current flows. However, such an integrator is not suitable as it is for integrating alternating current voltage because there is always an output limit and drift occurs due to offset voltage.

従って、本発明の目的は、冒頭に記載した種類の積分器
を交流電圧の正確で位相忠実度の高い積分に適するよう
に構成することである。この目的は本発明によれば、特
許請求の範囲第1項記載の積分装置により達成される。
It is therefore an object of the invention to design an integrator of the type mentioned at the outset in such a way that it is suitable for accurate and phase-fidelity integration of alternating voltages. This object is achieved according to the invention by an integrating device according to claim 1.

本発明を、特許請求の範囲第2項以下に記載されている
実施態様を含めて、以下て図面により一層詳細て説明す
る。
The present invention, including the embodiments described in claims 2 and below, will be explained in more detail with reference to the drawings.

第1図て示されている積分器1は、通常の仕方でコンデ
ンサC1を介して負帰還されており抵抗R1およびR2
を介して積分すべき入力電圧UEを与えられる演算増幅
器からなっている。積分器1の積分時定数はコンデンサ
C1のキャパシタンス値とR1およびR2の抵抗値の和
との積から定まる。入力信号UEが正弦波状であれば、
積分器1の出力端には同じく正弦波板の信号UAが現わ
れ、その位相は入力電圧UEの位相よりも正確に90°
(電気角)だけ遅れている。しかし、たとえば演算増幅
器の入力回路内の直、流源により常にオ狂いおよび零点
通過のずれが生ずる0このドリフト現象を回避するため
、抵抗R5およびコンデンサC2からなる低域通過フィ
ルタ(平滑回路)によりこの直流分が取り出され、低域
通過フィルタの後に位置し抵抗R6およびR7ならびに
コンデンサC3と共にPI回路として接続されている演
算増幅器2に与えられ、その出力電圧が積分器1の入力
側に負帰還電圧として与えられる0このPI回路はドリ
フト補償用調節器として作用し、その出力電圧は、出力
信号UA中の直流分が消滅して出力信号UAが純粋な正
弦波電圧となるので、出力信号UA中の直流分を減少さ
せる方向に変化する。抵抗R5の抵抗値およびコンデン
fC2のキャパシタンス値により定まる平滑回路の時定
数は交流電圧UEの周期Tにくらべて大きな値に選定さ
れるのが目的にかなっている。
The integrator 1 shown in FIG. 1 is negatively fed back via capacitor C1 in the usual manner and resistors R1 and R2.
It consists of an operational amplifier fed with an input voltage UE to be integrated via . The integration time constant of the integrator 1 is determined from the product of the capacitance value of the capacitor C1 and the sum of the resistance values of R1 and R2. If the input signal UE is sinusoidal,
At the output end of the integrator 1, a signal UA of the same sine wave plate appears, and its phase is exactly 90° more than the phase of the input voltage UE.
(electrical angle) is behind. However, in order to avoid this drift phenomenon, which always occurs due to a direct current source in the input circuit of an operational amplifier and a shift in zero point passage, a low-pass filter (smoothing circuit) consisting of a resistor R5 and a capacitor C2 is used. This DC component is taken out and given to an operational amplifier 2 located after the low-pass filter and connected as a PI circuit with resistors R6 and R7 and capacitor C3, and its output voltage is negatively fed back to the input side of the integrator 1. This PI circuit acts as a drift compensation regulator, and its output voltage is equal to the output signal UA since the DC component in the output signal UA disappears and the output signal UA becomes a pure sinusoidal voltage. changes in the direction of decreasing the DC component inside. The time constant of the smoothing circuit, which is determined by the resistance value of resistor R5 and the capacitance value of capacitor fC2, is suitably selected to be larger than the period T of alternating current voltage UE.

さて、積分器1の出力電圧UAは演算増幅器の供給電圧
により制限されているので、入力交流電圧UEの大きな
振幅変動に際して出力電圧UAは、特別な対策が講じら
れていなければ、上記の制限に突き当る。それにより、
一方では入力電圧UEの振幅またはその時間積分に関す
る情報が失なわれ、まだ他方では出力電圧UAに位相誤
差が生ずる。このような現象を回避するだめ、抵抗R2
を橋絡する双極性電子式ゲート回路3により積分器1の
積分時定数が出力制限への到達前に適時に、積分器1の
出力電圧がもはやこの制限に突き当らないように高めら
れる。そのために、出力電圧UAを与えられるしきい値
回路4が用いられる。このしきい値回路はそのブロック
シンボル内に記入されているような特性を有する。すな
わち、その入力電圧eが設定可能なしきい値+Usおよ
び一〇sにより境いされる範囲内にあれば、電子式ゲー
ト回路3の開閉間隙を閉じて抵抗R2を短絡する信号a
が生じ、他方、入力電圧eが上記の範囲を越える場合に
はこの信号aは消滅し、それによりゲート回路は第1図
に示されている開閉位置にもたらされ、この状態では抵
抗R2に電流が流れ、積分時定数が高め、られる。しき
い値回路のしきい値が演算増幅器の出力制限値よりも低
ければ、R1およびR2は、入力電圧UBの振幅変動に
際して積分器1の出力電圧UAがその出力制限値を越え
ないように、すなわちその演算増幅器が決してオーバー
ドライブされないように選定され得るO第2図には、オ
ーバードライブに対する保護効果が示されている。第2
図の左側に■と記入されている部分で、UA′は、かり
に出力制限がこの演算増幅器に存在しないとすれば生ず
るであろう積分器の仮想的出力電圧である。これは、た
とえば電圧U八′の零点通過が正確に入力電圧UEの極
太の時点で行なわれることかられかるように、入力電圧
UEの正確な積分に相当する。しかし、出力電圧UAは
値UAmまだは−UAmに制限されるので、出力電圧U
Aに望ましくない位相ずれが生ずる。この位相ずれは、
本発明によればオーツ(−ドライブに対して保護が行な
われるので、第2図の右側部分■に示されているように
回避される。すなわち、しきい値回路4の応動しきい値
+Usiたは−Usの超過後に積分器1の時定数が高め
られるので、出力電圧UAはもはやその制限に到達せず
、入力電圧UEの位相忠実度の高い積分がその後も擾乱
なしに行なわれ得る。
Now, since the output voltage UA of the integrator 1 is limited by the supply voltage of the operational amplifier, in the event of a large amplitude fluctuation of the input AC voltage UE, the output voltage UA will exceed the above limit unless special measures are taken. I bump into it. Thereby,
On the one hand, information about the amplitude of the input voltage UE or its time integral is lost, and on the other hand, phase errors occur in the output voltage UA. To avoid this phenomenon, resistor R2
By means of the bipolar electronic gate circuit 3 which bridges the integrator 1, the integration time constant of the integrator 1 is increased in time before the output limit is reached, such that the output voltage of the integrator 1 no longer hits this limit. For this purpose, a threshold circuit 4 is used which is provided with an output voltage UA. This threshold circuit has the characteristics as written in its block symbol. That is, if the input voltage e is within the range bounded by the settable threshold +Us and 10s, the signal a closes the opening/closing gap of the electronic gate circuit 3 and short-circuits the resistor R2.
If, on the other hand, the input voltage e exceeds the above range, this signal a disappears, thereby bringing the gate circuit into the open and closed position shown in FIG. 1, in which case the resistor R2 Current flows and the integral time constant increases. If the threshold value of the threshold circuit is lower than the output limit value of the operational amplifier, R1 and R2 are such that the output voltage UA of the integrator 1 does not exceed its output limit value upon amplitude fluctuations of the input voltage UB. That is, the operational amplifier can be chosen such that it is never overdriven. In FIG. 2, the effect of protection against overdriving is shown. Second
In the area marked ■ on the left side of the diagram, UA' is the virtual output voltage of the integrator that would occur if no output limit existed in this operational amplifier. This corresponds to a precise integration of the input voltage UE, as can be seen, for example, from the fact that the zero-point crossing of the voltage U8' takes place precisely at the extreme instant of the input voltage UE. However, since the output voltage UA is still limited to the value UAm -UAm, the output voltage U
An undesirable phase shift occurs in A. This phase shift is
According to the present invention, protection is provided against the auto (-) drive, so that it is avoided as shown in the right part (2) of FIG. After -Us has been exceeded, the time constant of the integrator 1 is increased so that the output voltage UA no longer reaches its limit and a phase-fidelity integration of the input voltage UE can subsequently be carried out without disturbances.

本発明による積分装置は大きな導体電流の測定のだめに
ロゴウスキ(Rogouski )・コイルと組み合わ
せて用いるのに良く適している。ロゴウスキ・コイルは
、公知のよって、非磁性材料から成るコアを有し7導体
を包囲する巻線から成っている。
The integrator according to the invention is well suited for use in conjunction with a Rogowski coil for the measurement of large conductor currents. The Rogowski coil is known in the art and consists of a winding surrounding seven conductors with a core of non-magnetic material.

導体を流れる交流電流によりロゴウスキ・コイルに誘起
する電圧が入力電圧として本発明による積分装置に与え
られ、その出力信号UAが導体を流れる交流電流の写像
として用いられ得る。
The voltage induced in the Rogowski coil by the alternating current flowing through the conductor is applied as an input voltage to the integrator according to the invention, the output signal UA of which can be used as a mapping of the alternating current flowing through the conductor.

しきい値回路4の応動しきい値+Usまたは−Usの超
過時間中に入力電圧の振幅忠実度も高い積分が望まれる
場合には、第3図に示されている追加装置を設ければよ
い。これは、スイッチ3の開s#による積分時間の増大
後にも積分すべき入力信号UEに関する情報が出力電圧
UA内になおも完全に存在しており、出力信号UAの重
み付けを積分時間の変更に相当して変更することにより
全時間範囲にわたり電圧UAに各時点で比例する写像を
得ることができるという認識に立脚している。そのだめ
に双極性の電子式ゲート回路5がしきい値回路4の出力
信号aにより駆動される。切換スイッチとして作用する
ゲート回路5は、出力電圧UAが応動しきい値十〇sま
たは−Usを越えているときて占める位置で図示されて
いる。この場合、出力端子6には、混合回路7でしきい
値電圧Usに係数(V−1)/Vを乗算した電圧を積分
器lの出力電圧UAから差引いた電圧が与えられる。そ
れに対して、出力電圧UAがしきい値回路4の応動しき
い値内にある場合には、ゲート回路5が切換えられ、比
例回路8で増幅係数1/Vを積分器1の出力電圧UAに
乗算した電圧が出方端子6に与えられる。増幅係数1/
Vは積分器1の小さいほうの積分時間と大きいほうの積
分時間との比により定められ、第3図に示されている例
でldl/V=R1/(R1+R2)fある。コのよう
にして出力端子6に生ずる信号Uaは各瞬間において入
力電圧UEを高い位相忠実度および振幅忠実度で積分し
た信号となる。このことは、積分器1の出力電圧UAで
は、それがしきい値回路4の応動しきい値内にある作動
状態でしか保証されていない。このような作動状態を指
示し得るようK、しきい値回路4の出力信号aが1つの
出力端子から導き出されていることは目的にかなってい
る。
If integration with high amplitude fidelity of the input voltage is desired during the time when the response threshold +Us or -Us of the threshold circuit 4 is exceeded, an additional device as shown in FIG. 3 may be provided. . This is because even after increasing the integration time by opening s# of switch 3, the information about the input signal UE to be integrated is still fully present in the output voltage UA, and the weighting of the output signal UA is changed by changing the integration time. It is based on the recognition that by corresponding changes it is possible to obtain a mapping that is proportional to the voltage UA at each point in time over the entire time range. To that end, a bipolar electronic gate circuit 5 is driven by the output signal a of the threshold circuit 4. The gate circuit 5, which acts as a changeover switch, is shown in the position it occupies when the output voltage UA exceeds the response threshold 10s or -Us. In this case, the output terminal 6 is given a voltage obtained by subtracting the voltage obtained by multiplying the threshold voltage Us by the coefficient (V-1)/V by the mixing circuit 7 from the output voltage UA of the integrator l. On the other hand, if the output voltage UA is within the responsive threshold of the threshold circuit 4, the gate circuit 5 is switched and the proportional circuit 8 sets the amplification factor 1/V to the output voltage UA of the integrator 1. The multiplied voltage is applied to the output terminal 6. Amplification factor 1/
V is determined by the ratio of the smaller integration time and the larger integration time of the integrator 1, and in the example shown in FIG. 3, ldl/V=R1/(R1+R2)f. The signal Ua produced at the output terminal 6 as shown in FIG. 1 is a signal obtained by integrating the input voltage UE at each instant with high phase and amplitude fidelity. This is only guaranteed for the output voltage UA of the integrator 1 in the operating state in which it is within the response threshold of the threshold circuit 4. It is expedient that the output signal a of the threshold circuit 4 is derived from one output terminal in order to be able to indicate such an operating state.

第4図には、積分された電圧UEの写像U8の絵上記の
再構成が図解されている。tlがら12までの時間中は
入力電圧はtoから11まで、またはt2からT/2ま
で(ここにTは正弦波の周期)の時間中の積分時間より
も係数V−(R1+’R2)/R1だけ大きい積分時間
で積分される。従って、to−Hおよびt2〜T/2の
時間中の電圧Uaは積分器lの出力電圧UAに係数1/
Vを掛けて小さくした電圧である。大きいほうの積分時
間で積分が行なわれる11〜t2の時間中は、信号Ua
は電圧UAとしきい値電圧Usとの間の差如一定の大き
さの電圧U s /Vを加えたものである。それにより
出力電圧Uaの曲線は平滑となる0すなわち、時点t1
およびt2でUA/Vの値に折れ点が生ぜず、tQから
T/2iでの全範囲で関係式Ua=UA/■が成り立つ
FIG. 4 illustrates the above-mentioned reconstruction of the map U8 of the integrated voltage UE. During the time from tl to 12, the input voltage is by a factor V-(R1+'R2)/ Integration is performed with an integration time larger by R1. Therefore, the voltage Ua during the time to-H and t2 to T/2 is the output voltage UA of the integrator l by a factor of 1/
This is the voltage reduced by multiplying by V. During the period from 11 to t2 when integration is performed using the larger integration time, the signal Ua
is the difference between the voltage UA and the threshold voltage Us plus a voltage U s /V of a constant magnitude. As a result, the curve of the output voltage Ua becomes smooth 0, that is, at the time t1
There is no breaking point in the value of UA/V at t2, and the relational expression Ua=UA/■ holds true over the entire range from tQ to T/2i.

しばしば、入力電圧UEの予想される振幅変動の処理装
置の駆動て十分な値に達せず、そのため良好に利用され
得ない。このような場合には、再構成された電圧Uaの
適応増幅を行なうのが有利である。第5図および第6図
には、それぞれ、電圧Uaを予め設定可能な一定の振幅
を有する電圧に常に増幅するために第3図による積分装
置に追加する回路が示されている。この一定振幅の電圧
は第4図中にUnで示されている。
Frequently, the expected amplitude fluctuations of the input voltage UE do not drive the processing device to a sufficient value and therefore cannot be utilized well. In such cases, it is advantageous to carry out an adaptive amplification of the reconstructed voltage Ua. 5 and 6 each show a circuit which is added to the integration device according to FIG. 3 in order to constantly amplify the voltage Ua to a voltage with a predeterminable constant amplitude. This constant amplitude voltage is indicated by Un in FIG.

第5図で乗算器9は、端子6から取出された電圧Uaと
積分特性を有する調節器10の出力信号Fnとを与えら
れる。乗算器lOの出力信号は振幅検出器11て与えら
れる。振幅検出器11は乗算器9の出力電圧Unのその
つどの最大値を検出して、出力端て相応の直流電圧信号
unを生ずる。
In FIG. 5, the multiplier 9 is supplied with the voltage Ua taken out from the terminal 6 and the output signal Fn of the regulator 10 having integral characteristics. The output signal of multiplier lO is provided to amplitude detector 11. An amplitude detector 11 detects the respective maximum value of the output voltage Un of the multiplier 9 and produces a corresponding DC voltage signal un at its output.

このような振幅検出器は、正弦波状の電圧では、最も簡
単な場合には、後段に低域通過フィルタを接続された整
流器から構成され得る。振幅検出器11の出力信号は振
幅調節器10の実際値として用いられ、一定の目標値た
とえば出力電圧制限値UAmと混合回路12で比較され
る。積分調節器10の出力量Fnは、乗算器9の出力端
に生ずる電圧Unが所定の目標値UAmに到達するまで
、乗算器9により電圧Uaを増大方向に変化させる。
For sinusoidal voltages, such an amplitude detector can in the simplest case consist of a rectifier followed by a low-pass filter. The output signal of the amplitude detector 11 is used as the actual value of the amplitude regulator 10 and is compared in a mixing circuit 12 with a certain setpoint value, for example an output voltage limit value UAm. The output quantity Fn of the integral regulator 10 causes the multiplier 9 to change the voltage Ua in the increasing direction until the voltage Un occurring at the output end of the multiplier 9 reaches a predetermined target value UAm.

第6図による装置では、同じ〈振幅検出器11が設けら
れており、また比率形成回路t3により比UAm/u1
aが形成される。比率形成回路13の出力信号Fnは同
じく乗算器14により、関係式un =UAm ’ここ
にunは乗算器の出カ端如生ずる交流電圧の振幅)が満
たされるまで、電圧Uaを増大方向に変化させる。第6
図による装置は、第5図による装置にくらべて、動的に
一層迅速に作動する。すなわちUaの電圧振幅の変化が
一層迅速に行なわれるという利点を有する。それて対し
て、第5図如よる装置の利点は、積分調節回路が用いら
れているので、平衡条件すなわちUAm”’Ω の条件
が特に擾乱生起の際に一層正確に満足され得ることであ
る。これらの装置により、正規化された振幅を有する出
力電圧Unが得られ、正規化係数Fnは係数Vと結び付
けられて関係式UA’ =U n −V/F n Kよ
り、積分された入力電圧UEの正確な値に通ずる。それ
により後段の処理装置の入力電圧範囲が一層良好に利用
され得る。
In the device according to FIG. 6, the same amplitude detector 11 is provided and a ratio forming circuit t3 provides a ratio UAm/u1.
a is formed. The output signal Fn of the ratio forming circuit 13 is also changed by the multiplier 14 to increase the voltage Ua until the relational expression un = UAm 'where un is the amplitude of the AC voltage generated at the output terminal of the multiplier) is satisfied. let 6th
The device according to the figure operates dynamically more quickly than the device according to FIG. That is, there is an advantage that the voltage amplitude of Ua changes more quickly. In contrast, the advantage of the device according to FIG. 5 is that, since an integral adjustment circuit is used, the equilibrium condition, that is, the condition of UAm'''Ω, can be satisfied more precisely, especially in the event of a disturbance. With these devices, an output voltage Un with a normalized amplitude is obtained, and the normalization factor Fn is combined with the factor V to obtain the integrated input voltage from the relation UA' = U n - V/F n K. The exact value of the voltage UE is reached, so that the input voltage range of the downstream processing device can be better utilized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は積分装置の接続図、第2図はオーバードライブ
に対する保護効果を説明するための波形図、第3図は高
い振幅忠実度を必要とする場合の積分装置の接続図、第
4図は第3図の積分装置の作動を説明するだめの波形図
、第5図および第6図はそれぞれ一定の大きさの出力信
号を必要とする場合の追加回路の接続図である。 ■、2・・・演算増幅器、 3・・・ゲート回路、 4
・・・しきい値回路、 5・・・ゲート回路、 9・・
・乗算器、 10・・・積分調節器、 11・・・振幅
検出器、12・・・混合回路、 13・・・比率形成回
路、 14・・・乗算器。
Fig. 1 is a connection diagram of the integrator, Fig. 2 is a waveform diagram to explain the protection effect against overdrive, Fig. 3 is a connection diagram of the integrator when high amplitude fidelity is required, and Fig. 4 3 is a waveform diagram for explaining the operation of the integrating device of FIG. 3, and FIGS. 5 and 6 are connection diagrams of additional circuits when an output signal of a certain magnitude is required, respectively. ■, 2... operational amplifier, 3... gate circuit, 4
... Threshold circuit, 5... Gate circuit, 9...
- Multiplier, 10... Integral regulator, 11... Amplitude detector, 12... Mixing circuit, 13... Ratio forming circuit, 14... Multiplier.

Claims (1)

【特許請求の範囲】 1)キャパシタンスを介して負帰還されておりかつ出力
が制限されている演算増幅器により交流電圧を積分する
だめの装置において、a)平滑回路がPI回路と直列に
積分器の追加的負帰還回路に設けられており、 b)  ff算増幅器の出力電圧が出力制限値よりも低
い予め設定可能なしきい値を越えるとき、積分時間を拡
大するため、しきい値回路により駆動可能な開閉手段が
設けられている ことを特徴とする交流電圧の積分装置。 2、特許請求の範囲第1項記載の装置において、開閉手
段として演算増幅器の入力抵抗を部分的に橋絡する双極
性電子式ゲート回路が設けられていることを特徴とする
交流電圧の積分装置。 3)特許請求の範囲第1項捷たけ第2項記載の装置にお
いて、ロゴウスキ・コイルの出力電圧の積分のだめに用
いられていることを特徴とする交流電圧の積分装置。 4)特許請求の範囲第1項ないし第3項のいずれかに記
載の装置において、積分器の出力電圧がしきい値回路の
出力信号に関係して、比例回路を介して増幅係数1/■
(ここに■は積分器の大きいほうの積分時間と小さいほ
うの積分時間との比)を乗算されて、もしくは混合回路
を介してしきい値に係数(V −1)/Vを乗算した値
に相当する電圧を差引かれて、出力端子に与えられるよ
うになっていることを特徴とする交流電圧の積分装置。 5)特許請求の範囲第4項記載の装置において、出力端
子に生ずる電圧が乗算器によりPI調節器の出力信号で
変調され、このPI調節器に目標値として一定値が、寸
だ実際値として振幅検出器により求められた被変調電圧
の振幅値が与えられていることを特徴とする交流電圧の
積分装置。 6)特許請求の範囲第4項記載の装置において、出力端
子如生ずる電圧が乗算器により一定値と振幅検出器によ
り求められたその振幅値との間の比で変調されることを
特徴□とする交流電圧の積分装置。
[Claims] 1) In a device for integrating an alternating current voltage using an operational amplifier which is negatively fed back through a capacitance and whose output is limited, a) a smoothing circuit connects an integrator in series with a PI circuit; an additional negative feedback circuit, b) driveable by the threshold circuit in order to extend the integration time when the output voltage of the FF amplifier exceeds a presettable threshold below the output limit value; 1. An alternating current voltage integrating device, characterized in that it is provided with a switching means. 2. An alternating current voltage integration device according to claim 1, characterized in that a bipolar electronic gate circuit for partially bridging the input resistance of an operational amplifier is provided as a switching means. . 3) An alternating current voltage integrating device, characterized in that it is used for integrating the output voltage of a Rogowski coil in the device according to claim 1 and claim 2. 4) In the device according to any one of claims 1 to 3, the output voltage of the integrator is related to the output signal of the threshold circuit and is amplified by an amplification factor of 1/■ through the proportional circuit.
(Here, ■ is the ratio of the larger integration time to the smaller integration time of the integrator) or the value obtained by multiplying the threshold value by the coefficient (V - 1)/V via a mixing circuit. An alternating current voltage integrator characterized in that a voltage corresponding to the subtracted voltage is applied to an output terminal. 5) In the device according to claim 4, the voltage occurring at the output terminal is modulated by the output signal of the PI regulator by the multiplier, and the PI regulator has a constant value as the target value and a constant value as the actual value. An alternating current voltage integration device characterized in that an amplitude value of a modulated voltage determined by an amplitude detector is provided. 6) The device according to claim 4, characterized in that the voltage appearing at the output terminal is modulated by a multiplier with a ratio between a constant value and its amplitude value determined by an amplitude detector. AC voltage integrator.
JP12599283A 1982-07-13 1983-07-11 Integrator for alternating current voltage Pending JPS5963571A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19823226168 DE3226168C2 (en) 1982-07-13 1982-07-13 Device for the integration of alternating voltages
DE32261683 1982-07-13

Publications (1)

Publication Number Publication Date
JPS5963571A true JPS5963571A (en) 1984-04-11

Family

ID=6168329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12599283A Pending JPS5963571A (en) 1982-07-13 1983-07-11 Integrator for alternating current voltage

Country Status (2)

Country Link
JP (1) JPS5963571A (en)
DE (1) DE3226168C2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0595285U (en) * 1992-05-26 1993-12-27 範介 市原 Fish head cutter

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990000741A1 (en) * 1988-07-05 1990-01-25 Omega Electric Limited Improvements relating to electric current measuring devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52134779A (en) * 1976-05-07 1977-11-11 Seiko Epson Corp Digital circuit meter
JPS5582058A (en) * 1978-12-18 1980-06-20 Toshiba Corp Initial setting method for plasma measuring integrator
JPS5682451A (en) * 1979-12-08 1981-07-06 Fujitsu Ltd Voltage measuring circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1337275A (en) * 1970-06-05 1973-11-14 Taylor Servomex Ltd Integrating amplifier circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52134779A (en) * 1976-05-07 1977-11-11 Seiko Epson Corp Digital circuit meter
JPS5582058A (en) * 1978-12-18 1980-06-20 Toshiba Corp Initial setting method for plasma measuring integrator
JPS5682451A (en) * 1979-12-08 1981-07-06 Fujitsu Ltd Voltage measuring circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0595285U (en) * 1992-05-26 1993-12-27 範介 市原 Fish head cutter

Also Published As

Publication number Publication date
DE3226168C2 (en) 1984-10-04
DE3226168A1 (en) 1984-02-23

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