JPS5963766A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obstruct the inflow of external charge to a memory array section, and to prevent the damping of memory charges by forming an impurity layer of the same conduction type as the source and drain of a memory transistor while surrounding the periphery of the memory array and forming a conductor layer connected to the impurity layer along the layer. CONSTITUTION:The source and drain regions 2, 3 of a semiconductor substrate 1 are diffused and formed, the regions are surrounded by a thick field oxide film 7, a floating gate 4 buried in an insulating film 6 is formed extending over the upper section of the film 7 from the regions 2, 3 and a control gate 5 is formed on the film 6. Consequently, a section containing the regions 2, 3 is used as the memory array 10, but the impurity introducing layer 18 of the same conduction type as the regions 2, 3 is further formed by utilizing an opening formed to the film 7 in the substrate 1 at that time, and the conductor layer 19 is applied on the layer 18. Accordingly, the array 10 is surrunded by an annular region 20 consisting of the layers 18 and 19, positive ions intending to intrude in the array 10 are obstructed by the region 20, and the ions are discharged to the ground reference potential of the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, and more particularly to floating gate avalanche injection metal oxide semiconductor devices.
ate Avalanche 1 injection M
etal Oxide Sem1conductor
This relates to the improvement of non-volatile semiconductor memory devices using field-effect transistors with a charge storage mechanism such as FAMO8). Field effect transistors are usually FAMO8 due to their structure and the physical phenomena they utilize.
It is called. This FAMO8 will be explained below as an example.

FIG. 1 is a sectional view showing the structure of this FAMO8. As shown in the figure, a source (2) and a drain (3) are formed on a semiconductor substrate +11, and a floating gate (4) and a control gate are formed on the substrate (1) astride the source (2) and drain (3). (5) is formed embedded in the insulating film (6). substrate(
1) and the source (2) are kept at ground potential, and the drain (
3) Apply a high frost pressure to the Oyohicon roll gate (5) to cause an avalanche breakdown phenomenon near the drain (3). Then, electrons are injected into the floating gate (4), and the threshold value of this FAMO 8 changes. Writing to FAMOEI is performed in this manner. The injected electrons are held in the floating gate (4) because it is surrounded by the insulating film (6). Erasing is performed by irradiating ultraviolet rays to give energy to electrons, causing them to be emitted and returning the abnormal value of FAMO8 to its original value.

I'll see it. Now, the potential of the control gate (5) is v
Co I The potential of the source (2) is vs, the potential of the drain (3) is 8. The potential of the floating gate (4) is V,
. .

Control Kate (5)
4) and the capacity between 02. floating gate (4)
The capacity of the song with and drain (3) is 03. The capacitance between the Frodeink game H4) and the substrate fi+ is set to 01. Let Q be the amount of charge on the floating y+41, then c,
(v, o-VS) +c2(v, o-v, .)-
1-03(V,, -Vo)-o,=o---[l] holds true. Here, V: 7.5V, V, =
When the IV is turned on, ■FO becomes about 0.3V, and the source (2
) and the drain (3), for example, C2=256.2X10”F,
C3=8.88X10-16F, C, -402
,4X1. If OF, Q=7.40 from the Cl3 formula!
+0.4G -0,60=183'7.692X
It becomes lO (coulomb) 2 3 1. If the charge of one electron is 1.602X10 coulombs, then N=1837.692X10 /1.602XIO
#1.15xxo((liD, that is, approximately 1.15 million electrons are accumulated in one floating gate (4). While these electrons are retained, the source (2) and drain (3) ), making it extremely difficult to form a channel between the control gate (5) and the control gate (5).
A channel will not be formed unless a voltage of W or higher is applied.

If there is a defect in the insulating film (6) surrounding the floating gate (4), electrons will escape from the defect and information will be lost.

There is another mechanism for information loss in FAMO8. It is because the 0 ions are attracted to the electrons held in the floating gate (4).
This is a mechanism that accumulates in the vicinity.

FIG. 2 is a cross-sectional view of the FAMO 8 in a plane perpendicular to the cross section of FIG. 1, and (7) is an insulating layer for isolation. FAMO8
[For example, in the board full, the isolation insulation J life (7
) above], it moves as shown by the dashed arrow in the figure due to the electric field created by the electrons in the floating gate (4), and the floating gate (4)
is accumulated near . The charge of this 3W ion at tV cancels the effect of the single floating gate. Therefore, although the charge in the floating gate +41 does not decrease, the overall effect is the same as that of the electrons escaping, leading to the loss of stored information.

FIG. 3 is a block diagram showing an example of a memory device using yAMos. (101 is a memory array in which F' A M OELs are arranged in a matrix, (11) is an address input terminal, and (lz) is an address Buffer, (+3) address decoder, H is data input/output circuit, (15) is data input/output terminal, (1ω is program control circuit, (1
η is a program control No. 46 input terminal.

In recent years, memory manufacturing technology has advanced and microfabrication has become possible, and as a result, the storage capacity of memory has increased to below t,C.
It's coming. That is, the memory array (11
The number of transistors included in +l has been increasing dramatically. As a result, the memory array (1
The number of beasts of electrons stored in 0) is also increasing. For example, if the aforementioned memory transistors are used in a 64 kilobit memory array, the maximum number of transistors is 1', 150,000 x '64,000 = 1.3
There are IO electrons, and the attractive force on the mobile ions is also enormous. Furthermore, if the memory capacity becomes even larger, this will become a bigger problem.

This invention was made in view of the above points. By blocking the progress of ■ ions from parts other than the IJ array, the memory retention time is extended and the @ axis degree is improved. The purpose is to provide a high quality semiconductor memory device.

FIG. 4 is a plan view showing an embodiment of the present invention, showing the l/i-aud of an integrated circuit chip when the memory device of FIG. 3 is constructed on a semiconductor substrate tli. Third
The same symbols as in the figures indicate equivalent parts.

H is a memory array (FAM in 101, OS
It is an impurity diffusion layer of the same conductivity type as the impurity forming the source and drain of (the rule is that it is a conductor layer such as aluminum or molybdenum that is electrically connected to the impurity diffusion layer (1@), and both memory arrays W ( 1 (++ is completely surrounded by a ring to form a cyclic valence region (gji).

Figure 5 shows the memory array (FAMO at the end of +01).
FIG.
be.

With this configuration, the memory array (1o)
The mobile O ions existing outside (to the right in Figure 6) move to the left due to the electric field created by the electrons θ of the floating gate (4), but they move to the left in the impurity diffusion layer (conductor layer Q9). is provided, and the mobile ions in the semiconductor substrate il are shielded by the impurity diffusion layer (1~), and the mobile ions on the surface' or the surface of the semiconductor substrate il+ are shielded by the conductor 76! (+9+). , the effect of the electric field from FAMOS to the left from this point becomes extremely small.
Maintaining the voltage at the memory device's reference potential (usually ground potential) is effective in quickly ejecting mobile ions.

When moving ions are supplied from the outside of the annular region 1), the effect of the structure of the above embodiment is very large, and FIG. 6 is a characteristic diagram showing the effect. As shown by the broken line t'fflA, the threshold voltage of the memory transistor is proportional to the voltage (the amount of electrons in the floating gate (4)). ] is 200 hours
In contrast, in this example, there is almost no attenuation even after 500 hours, as shown in Laugh Suite +MB.

In the above embodiment, a floating gate type memory device was explained, but for example, MNOS (Metal Nitr
ide Oxi+ie 5erniconductor
The present invention can be widely applied to memory devices capable of accumulating charges such as Since the conductor layer and the conductive layer formed along the layer and electrically connected are provided, the attenuation of the stored charge due to the inflow of charge from the outside into the memory array section is prevented, and the axial degree can be increased.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing the structure of FAMOS, Figure 2 is F
A sectional view of the AMOS in a plane perpendicular to the cross section of FIG. 1, FIG. 3 is a block configuration diagram showing an example of a mesos device using FAMOS, and FIG. 4 is an embodiment of the present invention. FIG. 5 is an enlarged partial sectional view showing the structure near the end of the memory array in this embodiment, and FIG. 6 is a characteristic diagram showing the effects of the present invention. In the figure, (1) is the semiconductor substrate, (2) is the source, (
3) is the drain, (4) is the floating gate, (5
) is control game 1-. 101 is a memory array, 0
2) is an address buffer, (1m is an address decoder,
(14) is a data output buffer, (1~ is an impurity introduced layer, θ9) is a conductor layer, and a ring is an annular region. In addition, the same reference numerals in the figures indicate the same or equivalent parts. ) Commissioner of the Japan Patent Office 1, Indication of the case, Patent Application No. 175551/1982 2
, Title of the invention Semiconductor memory device 3, Person making the amendment 5, Claims column 6 of the specification to be amended, Contents of the amendment fi+ The claims of the specification are corrected as stated in the attached appendix. 7. A document showing the scope of claims after the list of attached documents has been corrected. One or more copies of claims + l) A document that includes a source, a train, a control gate, and a charge retention mechanism provided in an insulating film directly under the control gate. and a memory array in which a plurality of field effect transistors are arranged in a matrix to store information by holding or not holding charge in the charge holding mechanism, and a peripheral circuit having at least an address selection circuit and a data input/output circuit. an impurity-introduced layer formed on the surface of the semiconductor substrate to surround the memory array and separate it from the peripheral circuit and having the same conductivity type as the source and drain; A semiconductor memory device comprising: a conductor layer formed on the surface of the semiconductor substrate along the impurity introduction layer and electrically connected to the impurity introduction layer. (2) an impurity introduction layer; The semiconductor memory device according to claim 1, characterized in that the conductor layer is connected to a reference potential point of the memory device. (3) The reference potential of the memory device is a ground potential. A semiconductor memory device according to claim 2.

Claims (1)

[Claims] (1) Source, drain, control gate and ≠
≠In a device in which a peripheral circuit including a plurality of field effect transistors that store information by retaining or not retaining electric charge on a single semiconductor substrate,
an impurity-introduced layer formed on the surface of the semiconductor substrate to surround the memory array and separate it from the peripheral circuit, and having the same conductivity type as the source and drain; 1. A semiconductor memory device comprising: a conductive layer formed thereon and electrically connected to the impurity J-. (21) The semiconductor memory device according to claim 1, characterized in that the impurity-introduced layer and the conductor layer are connected to a reference potential point of the memory device. (3) The reference potential of the memory device is a ground potential. A semiconductor memory device according to claim 2, characterized in that: