JPS5963894A - Receiver of pushbutton dialing signal - Google Patents

Abstract

PURPOSE:To suppress echo independently of the delay time of the echo by inhibiting the detection of a PB signal during the continuation of the echo. CONSTITUTION:If a received signal is detected as an effective signal of a PB signal when an echo is included in the trailing edge of a received signal, a signal (d) is outputted from an AND circuit 31, a rectifier circuit 9 is conducted and a DC voltage proportional to the peak value of the received signal is outputted. If the trailing edge of the received signal is correctly detected, an echo detecting circuit 32 sends an output (e) in a part including the echo after the detection, AND circuits 20-27 are closed and discriminating circuits 5-8, 11- 14 are inhibited from outputting. Therefore, the output (f) of the PB receiver is a signal having no influence of the echo.

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a push-button dial signal (
Hereinafter referred to as the r rPB signal. ) receiver. In particular, F B arriving via a transmission path where echoes occur
(Regarding the improvement of the i-th receiver.

[Description of prior art]

The PB signal i is transmitted as a selection signal from a push-button dial telephone and is also used as a data signal between terminals. In addition, the method used as the FB signal control signal is highly reliable as a data signal method that uses a communication network that transmits audio frequencies, and is an excellent method because it can be used with simple terminals such as telephones. There is. Particularly in recent years, as communication networks have improved and long-distance communication has become possible, simple data communication using PB signals has come to be carried out.

However, when a voice band signal passes through a long transmission path, reflection is unavoidable due to impedance mismatching that occurs at a two-wire/four-wire conversion point, resulting in so-called echo. Echo, which was not a big problem in voice calls, becomes unclear in data communication using PB double signals, making the trailing edge of the received signal unclear.■ Multiple FB double signals cannot be individually identified.
This caused inconveniences such as the inability to correctly determine the duration of a signal.

In order to eliminate the inconvenience caused by echoes as described above, conventional data communication F B '< signal equipment uses an 11iIl gain control 1tl (AGC) method, a pad control method, and 1 (
An echo suppression method such as a d variable threshold limiter method is used.

The AGO method automatically adjusts the amplifier gain so that the level of the incoming signal reaches a preset and specified level.
This method suppresses the influence of echoes by lowering the level of echoes that are weaker than the normal signal below the minimum receivable level. However, the AGO method is inconvenient because the received signal is distorted when the gain is changed to receive the FB multiplied signal, and there is a drawback that the gain may change inadvertently due to noise such as voice, resulting in erroneous reception.

' Also, the pad control method is a method in which the level of an incoming received signal is compared with a preset specified level, and if the level is higher than the specified level, a pad is inserted and control is performed so that no echo is received.

However, since it is necessary to provide four or five pads and level comparators each, the structure becomes complicated, and the device becomes large and expensive.

The variable threshold type limiter method is a method in which echoes are not received by changing the threshold of the FB reception signal limiter according to the level of the incoming reception signal. However, the variable threshold type limiter method has the disadvantage that the threshold value changes inadvertently due to a pseudo signal such as a voice, making it impossible to receive a regular signal.

In addition, the echo suppression method described above has a suppression effect only for values below a preset echo suppression time (for example, 20 to 40 mθ), which varies depending on the distance of the transmission path. It could not be applied to communication networks that have large variations in echo delay time, such as communication networks that involve communications.

[Detailed description of the invention]

The present invention improves on this point. It does not distort the received signal, has less influence from shoe sounds, is not affected by the echo delay time that changes depending on the distance of the transmission path, is small, inexpensive, and has a small size. The purpose is to provide a 1) B receiver that can suppress

[Structure of the invention]

The present invention provides a first means for detecting that a received signal arriving from a transmission path is an FB multiplied signal and a valid signal, and a second means for generating a DC voltage proportional to the peak value of the received signal level. and a third means for detecting the trailing edge of the received signal by comparing the DC voltage by the second means with the received signal v''''; a fourth means for prohibiting the detection of an echo of a received signal as an FB multiplied signal while the echo continues; and a fifth means for lifting the prohibition of detection.

[Detailed description of the invention]

An embodiment of the present invention will be described based on the drawings.

FIG. 1 is a diagram showing the main circuit configuration of an embodiment of the present invention.

Input terminal IN is the FB receiver input. A received signal input from input terminal IN is passed through buffer amplifier 1 to F.
B-fold signal low IIl to separate low group and high group frequencies
2. to the input of filter 2 for high group and filter 2' for high group.・4 It's broken. The output of the low group filter 2 is passed through a limiter circuit 3 to two low group discriminating circuits 5 to 8, respectively. The output a of the high group filter 2' is connected to a limiter circuit 3', a rectifier circuit 9 that generates a DC voltage proportional to the peak value of the received signal level, and a rectifier circuit 9 that compares the DC voltage with the received signal level to detect the trailing edge of the received signal. The signals are branched and led to respective comparison circuits IO.

The outputs of the limiter circuit 3' are led to high group discrimination circuits 11-14, respectively. The low group discriminating circuits 5 to 8 and the high group discriminating circuits 11 to 14 are each known circuits, each detecting the presence or absence of four received signals, and outputting the output from the OR circuit 15, 15' and the AND circuit 20. ~27 input terminals. The outputs of the AND circuits 20 to 27 are led to a control circuit 30. The control circuit 30 is a known circuit that controls the FB reception signal guard time and output time.

Furthermore, the output of the OR circuits 15 and 15' is output from the AND circuit 31.
The output thereof is led to one input terminal of the rectifier circuit 9 and the echo detection circuit 32. This rectifier circuit 9
The output of is led to a resistive attenuator 33, whose output is led to the other input terminal of the comparator circuit IO. This comparison circuit 1
The output C of 0 is led to the other input terminal of the echo detection circuit 32. The output e of this echo detection circuit 32 is connected via an inverter 34 to the other input terminals of the AND circuits 20-27.

In order to detect the arrival of the next received signal, the resistance attenuator 33 is set to a value slightly lower (approximately -saB) than the peak value of the first received signal level, taking into consideration the level fluctuation of the next received signal. This is to ensure reliable detection. Also,
Prevents malfunctions due to level fluctuations and noise superimposition while receiving signals continue.

FIG. 2 is an operation time chart of the input or output waveforms at the points indicated by the X marks in FIG.

With this circuit configuration, the received signal from the input terminal 1N is frequency-separated by the low group filter 2 and the high group filter 2', and is sent to the low group function circuits 5 to 8 and the high group discrimination circuits 11 to 14, respectively. input. This output is the logical sum circuit 15.
15' to the AND circuit 31, and the received signal is P
If the B signal is valid, the output d is sent out.

Further, a DC voltage proportional to the peak value of the received signal level is generated from the rectifier circuit 9, and the voltage is slightly reduced (-6 dB in this case) by the resistive attenuator 32 and input to the comparator circuit 10. Comparison circuit for this DC voltage and high group filter 2'
The received signal output a is compared, and output C is sent out while the received signal is being input. The echo detection circuit 32 receives (
i If the signal after @ is detected and the output d continues from the AND circuit 31, it determines that the subsequent received signal is an echo and sends out the output e. This output θ is inverted by the inverter. AND circuit 20~
27, completely prohibiting the transmission of the FB reception signal output signal while the echo is continuing. When the echo disappears and the output d stops, the current circuit 9 is reset and the output θ of the echo detection circuit 32 is also released, and the system enters a waiting state for the next reception signal of the PB reception signal.

This will be explained in more detail. FIG. 3 is a detailed diagram of the rectifier circuit 9, the resistive attenuator 33, the comparison circuit 10 and the echo detection circuit 32.

The rectifier circuit 9 includes an operational amplifier ■o8, a third diode D4,
Reset transistor TR1, smoothing resistor R1, capacitor C4, bias resistor R2, and inverter 35
The resistance attenuator 33 consists of an operational amplifier lc2, a diode D7, resistors R5, R4, and a fixed threshold voltage F1.
The comparison circuit 10 includes an operational amplifier No., a diode D5, a capacitor C2, and a resistor R5, and the echo detection circuit 32 includes an inverter 36 and an AND circuit 37.

With this circuit configuration, the output a of the high group filter 2' is detected by the operational amplifier io and the diode D1, and smoothed by the resistor R1 and capacitor C1 to become a DC signal. The rise time constant of capacitor C1 and resistor R1 is FB
Impulse noise is absorbed by setting the reception signal guard time to about 60 to 40 mθ.

This DC signal has a value proportional to the peak value of the received signal and is input to the resistance attenuator 33. By setting R3=R4, the attenuator can output a signal (kl) with a value of 6 dB below the peak value of the received signal. The operational amplifier ■C3 of the comparator circuit IO compares the signal (a) and the signal (b) and outputs the signal (c) when the signal (g) is present. At this time,
Diode D3, capacitor C2, and resistor R5 smooth the output of operational amplifier IC3 into a DC signal. The fixed threshold voltage vFIx (DC voltage corresponding to the received signal level -40 dE]m) is for preventing the comparator circuit 10 from making false detections due to noise or the like.

The signal (e) is input to the AND circuit 37 via the inverter 36, and the signal (a+) is input to the other input of the logic circuit 37.The output (θ) of the logic circuit 37 is the valid time of the PB times signal. The time t obtained by subtracting the time t of the received signal from t2
, is sent during . Also, the transistor TR is connected to the signal (d
) becomes conductive and short-circuits the DC signal across the capacitor C1.

Now, to explain the operation when the incoming received signal has a level of -10 dBm and is accompanied by an echo of -50 dBm, the PB received signal for data communication has a lower limit of the received signal level. Since it is specified that the signal can be received up to -46.5 dBm, it is impossible to distinguish between the received signal and the echo if this signal remains as it is. In the present invention, when this -10 dBm signal is received, it is multiplied by PB, and it is detected as a valid signal, the AND circuit 31 outputs the signal (d), and the transistor TR of the rectifier circuit 9 becomes non-conductive. .

When transistor TR becomes non-conductive, rectifier circuit 9 operates to output a DC voltage proportional to the peak value of the received signal. The comparison circuit 10 compares the DC voltage attenuated by -6 dB by the resistance attenuator 33 and the signal (a). Comparison circuit l
The output of O is output while the received signal continues, but in the echo part, a DC voltage proportional to (-10 dBm) -6 dB = -16 dBm is maintained, so the echo signal is
This echo signal is not detected even if it arrives at 5 dBm.

This allows the trailing edge of the received signal to be detected correctly without being affected by echoes. When the trailing edge of the received signal is correctly detected, the echo detection circuit 32 sends out an output (e) for the echo portion that exists after that, and the AND circuits 20 to
27 is closed to inhibit the outputs of the identification circuits 5-8 and 11-14. Therefore, the PB reception signal output f is not affected by the echo (it becomes the i number).

When the echo ends, the signal (a) also disappears, and the transistor TR becomes conductive, so that the rectifier circuit 9 is reset to its initial state.

The above shows that echoes are suppressed regardless of the echo delay time. However, as a matter of course, the delay time of the echo needs to be shorter than the duration of the received signal. However, if the echo delay time is abnormally long, the FB received signal of the present invention can be used by further lengthening the duration of transmitting the FB double signal. Also, if the next received signal arrives in a time shorter than the echo delay time, the echo and received signal will be partially superimposed, but the next received signal will be sent from the same terminal as the first signal. Therefore, the mutual level difference is about 6 dB. Therefore, since it is detected by the comparison circuit IO, the output of the echo detection circuit 32 is interrupted and the prohibition of FB multiple signal detection is canceled, so that the next reception signal can be received.

Although the above embodiment shows an example in which the output of the high group filter 2' is used, the output of the low group filter 2 is used by the rectifier circuit 9,
It may also be led to a comparison circuit IO.

[Detailed description of the invention]

As described above, according to the present invention, it is possible to prohibit the FB multiple signal detection while the echo continues, and it is possible to suppress the echo regardless of the delay time of the echo.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of an embodiment of the present invention. FIG. 2 is an operation time chart showing signal waveforms at points indicated by X marks in FIG. FIG. 3 is a detailed diagram of the rectifier circuit, resistive attenuator, comparator circuit and echo detection circuit. 1...Buffer amplifier, 2...Low group fill, 2
'...High group filter, 3.3'...Limit' vine circuit, 5-8...Low group identification circuit, 9...Rectifier circuit, 1
0... Comparison circuit, 11-14... High group discrimination circuit, 3
0... Control circuit, 32... Echo detection circuit, 33.
...Resistance attenuator. Watch applicant: NEC Corporation Representative: Naotaka Ide, patent attorney

Claims (1)

[Scope of Claims] circuit means; comparison circuit means for comparing the output of the rectifier circuit means with the received signal level and detecting the received signal and its rear end; and after the comparison circuit means detects the rear end, the first means and second means for prohibiting transmission of the receiver output when the output continues.