JPS5965480A - Semicnductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MO8 integrated circuit having a silicon gate structure, and particularly to an integrated circuit having a structure in which aluminum serving as a wiring conductor does not produce aluminum spikes 1 in a silicon diffusion layer.

MO8 integrated circuits always include a step of connecting an aluminum (A/) wiring layer to a diffusion layer in a silicon (Si) substrate. Heat treatment is performed at a temperature below the melting point of AI, and the Si melts into the AI, forming a 5i-A1 alloy and completing the contact. However, in some cases, the alloy may locally proceed, forming a so-called "alloy spike 1" in which the alloy passes through the diffusion layer. FIG. 1 shows a typical example of this. When the wiring of the A1 layer 6 is connected to the diffusion layer region 2 provided in the substrate 1, the diffusion layer 8i and Al pass through the 6 diffusion layer region 2, which has elongated spikes due to local heating or other causes. When reaching the substrate 1, the contact characteristics are lost. Even if the temperature is not reached, the current concentration and heating will deteriorate the characteristics.

Methods for preventing such alloy spikes include +1) adding a small amount of Si to Al in advance to prevent the Si from melting beyond a certain level; How to put it or (
3) A method has been considered in which a polycrystalline silicon wiring layer is used for contact with the substrate, and aluminum wiring is used only to connect this polycrystalline silicon wiring layer to the outside.

FIG. 2 shows the result of method (3) above, where the contact region is divided into a direct contact region 8 and an indirect contact region 8'.
Since layer 4 and diffusion layer 2 of the substrate are connected and method (2) is used to connect aluminum wiring layer 6 and polycrystalline Si layer 4 in indirect contact region 8', alloy spikes are connected from A/layer 6. does not occur.

The above method is not preferable because (1) requires the use of a special Si material (1) All, and (2) and (3) require special manufacturing steps. Further, in the example (3) of FIG. 2, the contact resistance becomes large because the electrical conductivity of the polycrystalline layer 4 is low.

The purpose of the present invention is to eliminate the above-mentioned drawbacks and to improve silicon gate MO
8. Alloy spikes can be produced very easily by simply modifying the diffusion mask and reshaping the contact area of the substrate diffusion layer without making any changes to the manufacturing process that is most commonly used in integrated circuits. Our goal is to provide a device with a structure that is unlike any other.

The MO8 integrated circuit according to the present invention has one or more polycrystalline silicon portions formed in the diffusion layer of the substrate in the contact region forming the electrical connection with the Al wiring to form the gate electrode part of the MO8 integrated circuit. It is characterized by being provided within the same process.

Embodiments according to the present invention will be described in detail below with reference to the drawings. FIG. 3 is a plan view of one embodiment of the present invention. A sectional view taken along the line AA' in FIG. 3 is shown in FIG. 4. Figure 3,
As shown in FIG. 4, in the same process as the gate generation process of the MO8 integrated circuit, a plurality of island-shaped polycrystalline silicon 9,
And the in-substrate diffusion region 2a is separated and generated around it. Note that the direct contact regions 8 are separated from each other in the portions immediately below the island-shaped polycrystalline silicon 9, but the other portions are adjacent to each other and are integrated. This island-like polycrystalline silicon 9 forms a gate oxide film 10. Although it is made up of two layers of polycrystalline silicon 11, it has a polycrystalline silicon gate structure using a normal self-alignment technique. Because of this structure, if heat treatment is performed below the melting point of A7, Si from the polycrystalline silicon will dissolve into A4, and once it reaches a saturated state, no more 5i-A1 alloy will be produced, and the diffusion layer 2a and The vertically directed alloy between A l++u in direct contact, the spikes do not advance.

As detailed above, in the present invention, the 8i calculated by A[Km reaches saturation, the growth of the Al-8i alloy stops, and no alloy bidandruff occurs in the diffusion layer of the substrate. Moreover, the polycrystalline silicon portion 9 in the contact region which provides such an effect has the effect that there is no need to add a special process in manufacturing the MO8 collector circuit.

In addition, in Figure 4, the diffusion layer 2a is drawn as if it were separated into six islands, but as shown in Figure 5, by utilizing the property of spreading the diffusion in the horizontal direction, the part directly below each height is also a single diffusion layer. Needless to say, there are no scales in the area.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views showing the connecting portion between the substrate diffusion region and the aluminum wiring of an MO8 integrated circuit according to the conventional method, and FIG. 3 is a plan view of the contact region showing one embodiment of the present invention. 4 is a sectional view taken along line AA' in FIG. 3, and FIG. 5 is a diagram showing another embodiment of the present invention. 1... Substrate, 2, 2a... Diffusion layer, 3
...field oxide film, 5 ... interlayer insulator, 6 ... A1 layer, 7 ... surface protection film, 8 ... contact Region, 9... Island-like polycrystalline silicon, 10... Gate oxide film, 1
1... Polycrystalline silicon.

Claims (1)

[Claims] In a silicon gate type MO8 integrated circuit, one or more pieces of polycrystalline silicon are deposited at predetermined positions in a substrate diffusion region that forms an electrical connection with an aluminum wiring in the same process as the gate electrode part forming process of the MO8 integrated circuit. A semiconductor device characterized by the provision of a portion.