JPS596573A - Lateral bi-polar transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bipolar I-type transistor, and more particularly to a lateral bipolar transistor that can reduce the rate of decrease in current amplification in a high injection region.

Increased speed and lower power consumption of bipolar semiconductor integrated circuits,
With the trend toward lower voltage driving, PIPs have been developed that have performance comparable to NPN (NPN) Lancistors, that is, have high withstand voltage, high current amplification factor, and high frequency characteristics with a simple manufacturing process, and are suitable for high density.
) Demand for Runcissta has increased.

However, with the miniaturization of patterns, it has become difficult to form a PNP transistor whose current amplification factor (hereinafter referred to as hFlc) has a small dependence on current. Figure 1 shows a horizontal PNP (transistor) transistor, where Figure 1 shows a mask pattern and Figure B shows its cross-sectional structure along line A'. In the figure, 11 is a P-type emitter region, 12 is an N-type base region, 13 is a P-type collector region, 14 is a base contact region, 5 is an LP-type substrate, 16 is an N-type epitaxial region, and 17 is an N-type buried region. It is an area. The epitaxial region 16 has a specific resistance of 1 Ω-cm, and the P-type emitter region 11 and the P-type collector region 13 are formed simultaneously during boron diffusion to form the active base region of the NPN transistor, and have a resistivity of about 0.7 μm. has a diffusion depth of

Now, we will focus on the area between the emitter region 11 and the collector region 13, which is the most important part of the PNP, ) run transistor.
Figure 2 shows the main parts. In the figure, the distance WB from the end of the emitter region 11 to the end of the collector region 13 is the base width, and the distance WB from the end of the emitter region 11 to the end of the collector region 13 is the base width. It is smaller than the membrane 180 width plate due to the influence of lateral diffusion of boron. When WB' is 4 μm, wB is approximately 3 μm. In such a structure, the distance between the emitter region 11 and the collector region 13 is smallest at the surface of the epitaxial layer 160, so that in the operating state, current is concentrated on the surface of the base region 12, and the cross-sectional area of the current path is small. Therefore, the density of holes, which are chiaria, increases in this portion, resulting in a decrease in emitter efficiency and an increase in recombination in the base region, resulting in a decrease in the current amplification factor hFE-.

FIG. 3 is a graph showing emitter current dependence of hFK, and shows the results for each transistor in the PNP transistor shown in FIG. 1 with the base width Wd on the mask pattern varied from 4 μm to 7 μm. hFE reaches its maximum when the emitter current is about 60 μA, and decreases sharply as the emitter current increases. This development is controlled by the impurity concentration in the base region and the current density, and as the current density becomes higher than the impurity concentration, hFK decreases. This is because the smaller the distance WB between the emitter and the collector, the more the emitter current is concentrated near the surface.

On the other hand, as the base width WB' increases, the emitter current at which hFK becomes maximum increases, but the disadvantage is that hFE is small.

Conventionally, even if Wd is small, as a means to maintain high hFE up to the high current region, it has been possible to increase the planar area of the current path and increase the facing area of the emitter and collector in order to reduce the current density. It has been done. However, this method has the disadvantage that the area becomes extremely small. As the area becomes too large, it is not only unsuitable for application to high-density integrated circuits, but also speed increases are limited by capacity.

The present invention has been made in view of the above drawbacks, and an object of the present invention is to provide a high-density bipolar transistor that can maintain high hFE even in a high current region.

FIG. 4 shows a photomask pattern diagram showing the first embodiment of the present invention. Emitter region 11 and collector region 1 in the figure
3 are formed at the same time, and the base width is predominantly determined by the gap 12 between the emitter region 11 and the collector region 13. In FIG. 4, the same numbers as in FIG. 1 indicate the same parts. Now, the base widths on the mask pattern defined for each side of the square emitter region 11 are a and b, respectively.
'.

FIG. 6 shows the emitter current dependence of hFE when c and d are set as, for example, a24μm b2d25μm c ==6μm. In the figure, the curve a in the figure is the curve a in Figure 3,! l
: Curve 8 shows the characteristics of the transistor shown in the first embodiment of the present invention.

According to this embodiment, the current amplification factor is improved in a region where the emitter current is large and exceeds 100 μm. The improvement rate is approximately 3Q% for hFE when the emitter current is 200μA.
, at 500 μA, it reaches over 100 factors. this is,
When the emitter current is small, a narrow base width of 4 μm acts on the mask pattern to provide high hFIC, and as the current increases, a wide base width acts to prevent a sudden drop in hFE. .

As described above, according to the embodiments of the present invention, the area increase is small through simple steps, and hFE is high in the low current region due to the effect of the narrow base width, and in the high current region, the hFE is high. The decrease in hFK can be ameliorated by the effect of this drug.

Next, as an application example of the present invention, some planar patterns of emitter and collector regions of a lateral PNP l-transistor are shown. FIG. 6 is a mask pattern showing a second embodiment of the present invention, in which the outer periphery of the emitter 11 and the inner periphery of the collector 13 are circles, with diameters of 10 μm and 20 μm, respectively.・1μ without matching
It is eccentric by m. Therefore, the distance between the outer circumferential circle of the emitter 11 and the inner circumferential circle of the collector 13, that is, the base width, changes continuously. This structure also has the same effects as the first embodiment.

FIG. 7 is a mask pattern showing a third embodiment of the present invention, in which the emitter region is divided into 11a and 11b, each emitter region 11a.

11 bits, respectively 4μm and 5μm on the mask
A collector 13 surrounds the bases 12a, 12b with m different widths between them.

This structure also has the same effects as the first embodiment.

As described above, the lateral bipolar transistor according to the present invention not only makes it possible to increase the density and speed of bipolar integrated circuits, but also reduces distortion due to impedance changes by using it in circuits with large current amplitudes. It can also contribute to improving the characteristics of integrated circuits.

[Brief explanation of the drawing]

Figure 1A is a plan view of a conventional horizontal PNP Runcistor.
Figure B is a sectional view taken along line A-A', Figure 2 is a cross-sectional view of the main part of Figure 1B, Figure 3 is a characteristic diagram showing the emitter current dependence of hFE of a conventional lateral PNP transistor, and Figure 4. 5 is a plan view of a lateral PNP transistor according to an embodiment of the present invention, and FIG.
Characteristic diagrams showing emitter current dependence of FE, Figures 6 and 7
The figure is a plan view showing another embodiment of the present invention. 11...Emitter area, 12...Base area, 13...Collector area 0 Name of agent Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 Figure 3 Figure 4 Figure 5

Claims (2)

[Claims] (1) Planarly, it includes at least a hollow collector region and an emitter region formed in the hollow portion of the collector region, and the distance between the opposing surfaces of the emitter and collector regions varies depending on the location. A lateral bipolar transistor comprising: (2) The lateral bipolar transistor according to claim 1, wherein a collector region and an emitter region are formed at the same time.