JPS5969933A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To etch only a desired region, and to prevent the generation of undesired corrosion by coating all surfaces of a semiconductor board except one surface with a protective insulating film having etching-resisting property. CONSTITUTION:The back 23 and side surface 24 except a main surface 22, which must be treated by etching, of the silicon board 21 are coated with the insulating protective film 25 consisting of a substance such as pitch, which resists an etching liquid used, or a corrosion-resisting organic material. Etching is enabled in order to form a wiring or an electrode or bore a window to a glass layer on the wiring regardless of element structure in the silicon board because battery action generated between a metallic layer to be etched or a metallic layer being in contact with the etching liquid and the silicon board is obstructed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a process for manufacturing a semiconductor device that includes an etching process for forming holes in a metal layer provided on a semiconductor substrate for forming wiring and electrodes.

When etching away the metal remaining in the field after forming bump electrodes and electrodes in flip chips, or when removing glass such as phosphor glass provided by CVD on multilayer wiring, bumps are removed. Abnormal corrosion of electrodes, M wiring, etc. may occur. For example, a flip-chip IC has a ground electrode section on a separation layer as shown in FIG. 1(a), and an emitter electrode section as shown in FIG. 1(b). In FIG. 1(a).

A P-type separation layer 3 is present between and between N-type epitaxial scraps 2 on a P-type silicon substrate 1, and a P-type space layer 4 is present therein. On the other hand, in FIG. 1(b), there is a P-type layer 5 inside the N-type epitaxial layer 2. Furthermore, an N-type layer 6 is provided inside. The window part of the 8102 layer 7 covering the surface has A
A passivation film 7 is provided surrounding the 1 film 8 . Rose 7 The first base metal layer 9 covers the scivation film 8.

Furthermore, solder bumps 11 are formed directly above the P-type layers 4 and 6 with a second base metal layer 10 interposed therebetween. When forming bump electrodes by electroplating, the first base metal layer 9 is used to ensure that each electrode part has an equal potential and the bump height is equal, and is left on the entire surface of the silicon plate 1 until the bump electrodes are formed. It is. However, after that, etching removed the first base metal other than the lower layer of the bump electrode 11! ′
The f4 layer 9 needs to be removed. At that time, the bump electrode 11
Depending on the element structure on the lower side, a battery may be formed between the solder bump 11 and the silicon plate l, and the solder may corrode.

There are drawbacks such as elution and irregularities in the height of the bump electrodes. In other words, during etching, a current flows in the region of the separation layer 3 shown in FIG. 1(a) because there is no PN junction, so that the solder is eluted, but in the transistor region shown in FIG. 1(b), there is no PN junction.
Since the N-junction exists and blocks the current that dissolves the solder, the height of the bump at the ground electrode portion is lower than the height of the bump at the emitter electrode portion.

FIG. 2 shows a cross-sectional structure of a multilayer wiring, in which an N-type epitaxial layer 2 on a P-type silicon substrate 1 is separated by a P-type isolation layer 3, and a P-type layer 5 and an N-type layer 6 are formed inside it. ing. The window portion of the aluminum 7ij 121i 5i02 scrap 7 that covers the upper surface of the S s 02 N7 film is in contact with the separation layer 3, the base layer 5, and the emitter layer 6. It is covered with a phosphor glass layer 13. A window is opened in this glass layer 13 to connect the M wiring 1.
When forming the contact hole 14 with the base layer 5 and the emitter layer 6 by etching, the current that dissolves the M wiring on the base layer 5 and the emitter layer 6 is PN.
Although the 1M wiring is prevented by the bonding and is not corroded, a current flows to elute the M wiring on the 1st separation layer 3 or the M wiring in contact with the collector layer 2 (not shown), so the M wiring 12 in this area is corroded by the etching solution. There is a drawback that

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, performs etching only in desired areas, and does not cause undesirable corrosion.

The purpose of this is to remove a predetermined area of a metal layer provided on one surface of a semiconductor board or another layer on the metal layer in a method of manufacturing a semiconductor device. This is achieved by coating all surfaces of the plate with a protective insulating film having etching resistance.

That is, to explain with reference to FIG. 3, the back surface 23 and side surfaces 24, excluding the main surface 22 to be etched, of the silicon plate 21 having the structure shown in FIG. For example, it is covered with an insulating protective film 25 made of pitch or a corrosion-resistant organic material. This prevents the battery action that occurs between the metal layer to be etched or the metal layer that comes into contact with the etching solution and the silicon plate, so it is possible to form wiring and electrodes or open windows in the glass layer on the wiring, regardless of the element structure of the silicon plate. This has the advantage that etching is possible. In addition, it is also useful for preventing etching or mechanical damage to the back surface of the semiconductor board.

As described above, the present invention covers all surfaces that are not subject to etching with a protective film in order to prevent battery action during etching for forming wiring and electrode structures on a semiconductor board. It is extremely effective for forming wiring and electrode structures, and has great effects in manufacturing semiconductor devices.

[Brief explanation of the drawing]

1(a) and 1(b) are cross-sectional views of the ground electrode portion and emitter electrode portion of a 7-lip chip to which the present invention is applied, and FIG. 2 is a cross-sectional view of a multilayer wiring structure to which the present invention is similarly applied. FIG. 3 is a sectional view showing one embodiment of the present invention. 21... Silicon plate, 25... Insulating protective film. (a> tb) 131-

Claims (1)

[Claims] 1) When etching and removing a predetermined area of gold 84M provided on one surface of a semiconductor board or another layer on a metal layer, all sides of the semiconductor board except for said one surface are etched. 1. A method of manufacturing a semiconductor device, comprising covering the device with a protective insulating film having etching resistance.