JPS5969968A - Embedded gate type gate turn-off thyristor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to buried gate gate turn-off (GTO) thyristors.

This type of GTO thyristor is a conventional canned split type GTO thyristor.
Compared to TO thyristors, it has many advantages, such as easier insulation between the gate and cathode, better efficiency in single area utilization, and better thermal resistance characteristics. The utilization efficiency of this turn-on gate current will be explained with reference to FIGS. 1 and 2.

FIG. 1(A) shows a cross-sectional view of the cathode split type GTO silisk, and the cathode N1 layer divided into one layer is p.

It is configured with a step difference from the base layer, and the divided cathode 'Wf pole Kd (!: P, gate electrode G on the layer) is formed on the N9 layer.
/ is step-insulated. In the figure, numeral 1 indicates a canned electrode which is collectively connected to the divided cathode electrodes Kd, and numeral A indicates an anode electrode. In this GTO thyristor, the gate current required to turn on the divided cathode N.

It flows from the gate electrode G/ surrounding the layer to each cathode N1 layer (emitter), and is distributed in each divided cathode N1 layer with a peak at the adjacent boundary as shown in the enlarged view in No. 19 (B). It flows as a current, and the "1 + Ns * Ps r Ns thyristor part under the projection of the N9 emitter starts to turn on from this part near the gate.The buried gate type GTO zyristor shown in Fig. 2 is as follows.
A lattice-like or strip-like high concentration impurity layer p in the Pg base layer,
+ Fully embedded, applicable? Gate electrode G with the layer as gate
, with an ohm connection. The on-gate current in this thyristor flows from the connected buried gate P*+ layer toward the single emitter 87 layer as shown by the arrow.

At this time.

The effective thyristor portion that turns on is the region S where there is no buried portion P9+ layer, and N in this projection region S.

Only the gate current component flowing into the emitter layer becomes effective as an on-gate current. That is, among the distributed gate current components, N above the buried gate.

Even if electrons are injected from the N emitter due to the gate current component flowing into the region, these are trapped in the heavily doped buried layer P,+ and become an invalid component that does not induce injection from the P, base layer. Therefore, the gate turn-on current of the buried gate type GTO thyristor is less efficient than that of the split cathode type.

An object of the present invention is to provide an entire thyristor structure that can efficiently supply the turn-on gate current of a buried gate type GTO thyristor.

Figure 3 shows a buried gate type GTO showing one embodiment of the present invention.
FIG. 3 is a cross-sectional view of a thyristor. The difference between this figure and Figure 2 is that N faces the P9+ buried gate layer, which becomes a high concentration impurity layer, the emitter layer region is formed shallowly, and N does not face the Pt layer, and the region is formed deep. be. The Pt layer is formed by selective impurity diffusion into the 21st layer as shown in the figure.
A low concentration impurity layer p, - is formed above the layer. p, +
The layers are formed in a predetermined pattern as described above, and the edges are formed with G! is formed by an ohmink connection. N.

The layer is provided on the p, ″″ layer and becomes an N emitter layer.

This N9 layer is a single structure that is not divided.

Its depth is selectively chosen, shallow in the projection area of the P layer,
A region outside the projection area of the P,+ layer is formed deeply. The depth of this non-projection area is selected to be 200μ to 400μ, and the depth of the projection area is selected to be less than half (100μ to ?00μ).

This N9 layer formation begins with P as shown in the fourth section (A).
Then, a non-projection region N2 layer is formed by selectively diffusing phosphorus on one layer, and then, as shown in FIG. 4(B), phosphorus is diffused over the entire surface to form a projection region.

Due to this structure, when the turn-on gate current flows from the P, region to the N1 layer, this current distribution is such that the current density is high at the end of the deep region of the N2 layer (non-projected region of P, l+), and the current density is high at the end of the deep region of the N2 layer (non-projection region of P, (projected region), the current density is low because the N2 layer is shallow. Therefore, injection of electrons from the bird layer in the effective thyristor section that is turned on is not easily induced, and it is possible to improve the utilization efficiency of the gate current and reduce the minimum firing current. In the experiment of this embodiment, the minimum ignition current was reduced to about 1/10 compared to the conventional buried gate type.

As described above, according to the present invention, without impairing the characteristics of the buried gate type GTO thyristor, the utilization efficiency of the on-gate current is increased, the minimum ignition current is reduced, and the current spreading speed is increased. It is possible to completely improve the withstand capacity of a.

In the example, the width of the shallow region of the 41st layer is p.

It is not necessary that the widths of the projected areas of the layers match each other, and the same effect can be obtained even when there is a difference in the size of one width.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional split cathode type G,TO thyristor, FIG. 2 is a sectional view of a conventional buried gate type GTO thyristor, FIG. 3 is a sectional view showing an embodiment of the present invention, and FIG.
The figure is a cross-sectional diagram showing the formation process of the N and cathode layers in FIG. 3. K...Cathode electrode, A...Anode electrode, G/1
-02...Gate 1M pole, P9+...Buried gate layer, N,...Cathode electrode. Figure 1 (B) d Figure 2 and Figure 3 are procedural amendments (voluntary) 1. Indication of fact A'1 1988 Patent Application No. 180488 2 Name of the invention Embedded gate type gate turn-off thyristor Relationship with the case of the person making the 3° correction Applicant (610) Meidensha Co., Ltd. 4, Agent 1-29 Akashi-cho, Chuo-ku, Tokyo 104, Suiseikai Building (1)
Contents of amendment in column a of the specification “Detailed Description of the Invention” 300-

Claims (1)

[Claims] In the buried gate type gate turn-off thyristor, the buried gate type gate turn-off thyristor includes four layers of J, N, P, and N, and a middle layer of high concentration impurity P, which is formed in a predetermined pattern in the 21 layers and connected to the gate electrode. The 89th layer is a buried gate type gate turn-off thyristor characterized by a structure in which the region where the P and middle layers are projected is shallow (P and the region where the middle layers are not projected is deep).