JPS5969973A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To expand the limited memory holding hours of an MNOS FET at least up to 10<5>hr or more, and to obtain the new MNOS FET sufficient to be called as the non volatile semiconductor memory device by a method wherein impurities as to compensate density of a trapping center to electrons or holes in an Si3N4 layer of charge accumulation layer are added into the Si3N4 layer. CONSTITUTION:An SiO2 layer 2 of 20Angstrom thickness generated according to thermal oxidation is formed on the surface of an N type Si substrate 1, and hydrogen atoms 4 are added as the impurity in the surface of the SiO2 layer 2. The Si3N4 layer 3 (thickness is 500-700Angstrom ) generated according to the CVD method is formed, and moreover an Al gate electrode 5 is formed on the surface of the Si3N4 layer 3. Moreover, source and drain regions, etc., are omitted in the figure. When this method is applied to the MNOS FET using an alumina (Al2O3) layer as a second dielectric layer, the same effect can be obtained. Moreover, as the impurity to be added, F (fluorine), etc., are also favorable.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the memory retention characteristics of a semiconductor device, particularly a non-volatile semiconductor memory device comprising an insulated gate field effect transistor having a 21st layer as a gate insulating layer. .

A nonvolatile memory device consisting of an insulated gate field effect transistor whose gate insulating layer has a double dielectric structure is resistant to ultraviolet rays, while a nonvolatile memory device consisting of an insulated gate field effect transistor whose gate insulating layer has a double dielectric structure is resistant to ultraviolet rays. Although it is only possible to erase all pits at the same time, it is extremely useful because it is possible to manually rewrite each bit or word.

Here, the 21 dielectric insulating layer refers to a first dielectric layer having an extremely low density of trapping centers for electrons or holes formed on the surface of a semiconductor substrate, and a surface of the first dielectric layer. A second dielectric layer is formed in a diagonal manner and has a large density of trapping centers for electrons or holes.
The dielectric N acts as an electrical (electron or hole) storage and retention layer, and the first dielectric layer acts as a barrier between the semiconductor substrate, which is a source and sink of charges, and the second dielectric layer. Working. The thickness of the first barrier 1b, the body layer (barrier), is
The material is extremely thin, usually 15 to 3 degrees, so that charges can directly pass through it by tunneling effect.

Namono I is the most common insulated gate type military effect red transistor with the above double dielectric layer as a gate insulating layer.
d,, MNO8FB'J', JIIpchi, 5in2 layer by thermal oxidation as the first electric layer of the gate insulation layer, and 84. by CVD method as the second dielectric layer. N.

These are field-effect transistors that use films.

Furthermore, although there are two types of FETs, P-channel type and N-channel type, the P-channel type MNO8FE'L' will be explained in detail below as an example.

When a negative voltage pulse of sufficient magnitude is applied to the gate electrode (Al) of the P-channel type MNO8FET with respect to the substrate (N-type Si), the surface of the N-type Si substrate is inverted to the P type, and the P
The holes, which are majority carriers in the type inversion layer, are thin in 8i0. Si3N is injected into the layer by direct tunneling through the layer and trapped δ in the trapping center for the stop hole in the Si3N4 layer. As a result, a positive electric charge j is accumulated in the gate insulation Tfr4, and l! 'The threshold voltage of ET changes in the negative direction. The density of trapping centers for holes in the S i,N layer can be considered to be spatially uniform, but in this case, the density distribution of trapped holes immediately after the application of a negative voltage pulse is shown in Figure 1. So S 1o2-8 i, N,
The curved force peaks slightly into the Si, N, and J acids, and gradually decreases toward the gate and pole (Al). As long as this captured hole'&1 degree distribution is 7'L, the threshold value will not change,
Forever memory & talent.

However, 5isN, the number of holes trapped in the layer actually decreases with time. The reason for this decrease is that holes emitted from the trapping center are S
i, N, the hopping transfer between the empty capture centers in the layer, flows to the gate power source j by 4, or S io,
-S i, N, Sin after reaching the world ■.

flows through the layers to the N mSi substrate. As a result, MN
The threshold voltage of the O8FET changes in the positive direction with time and eventually becomes equal to the threshold voltage before the application of the negative voltage pulse. In other words, the memory retention time of MNO8FET is limited,
Usually it is on the order of 10' to 105 seconds.

The purpose of the present invention is to expand the finite memory retention time of MNO8FET to at least 105 hours or more (~10 years or more), and to make MNO8FET a suitable MNO8FET as a non-volatile semiconductor memory device.
8FET''f: %.

According to the present invention, it is preferable that an impurity is added to the Si, N layer to compensate for the trapping center density for electrons and holes in the charge storage layer 5isN. A better MI'JO8FET can be obtained.

The density of trapping centers for electrons or holes in the Si, N, layer formed by the CVD method is several orders of magnitude larger than the number of electrons or holes that are sufficient to change the threshold voltage of MNO8FhiT. It's bigger than that. Therefore, in the 8i,N layer in the charge storage state, there is a much larger density of empty trap centers than the amount of charge stored in the storage layer. On the other hand, since the amount of charge flowing due to hopping conduction between empty trap centers is proportional to the empty trap center density, the normal M
The short memory retention time of the NO8FET, 104 to 105 seconds, is due to the presence of empty trap centers in the Si3N4 layer, which are much larger than the required storage charge.

In other words, to extend the memory retention time of MNO8FET, s
i,N.

It is necessary to set the density of trapping centers for electrons and holes in the layer to a necessary and sufficient level.

In the structure of the present invention, rrl [MNO8 as described above]
Impurities that provide trapping centers for electrons and holes in the S's NA layer of F'ET are Si3N,
It is characterized by being added into the layer. That is, S
By adding impurities (
As a result, an MNO8FET can be obtained in which the number of empty trap centers in the charge accumulation state is reduced as much as possible by reducing the amount of trapping charge to a level equal to or slightly exceeding the required trapping charge.

Impurities can be added into the Si3N layer by the CVD method, by flowing a gas containing the necessary impurity elements at the same time as the raw material gas during layer formation, or by ion implantation after the Si, N layer is formed. The necessary impurity elements are 8i,
N.

It can be easily coupled by injecting it into the layer. On the other hand, no,
Impurities that can be easily added into the 8i, N layer by such a manufacturing method are preferred. As for such impurities for the capture center axis 01, regarding the capture center for the stop hole,
Since hydrogen is a hole or a positive charge, chlorine is a gas in a hole state and can be easily implanted. Each one has a spear based on what it can do.

FIG. 2 is a sectional view showing an embodiment of the present invention,
Si is deposited on the surface of the N-type St substrate 1 by thermal oxidation at ~20A.
0,702 is formed, SiO, and the surface of layer 2 is doped with hydrogen atoms 4 as impurities.
! A layer of Si, N, 43 (thickness 500 to 700A) is formed, and an Al layer is formed on the surface of 8i, N, i3.
ll, Miserable 5 has been formed. Note that in FIG. 2, the source and drain regions, etc. are omitted.

Figure 3 shows the memory retention characteristics of a P-channel MNO8FET compared to a conventional MNO8FHT in which no hydrogen atoms are added.
The difference between the single value ``red pressure change 11'' and the case value pressure change 12 of the MNO8FET according to the present invention shown in Fig. 2 is O. As is clear from FIG. 3, the memory retention characteristics of the 1NO8FET incorporating the present invention are much improved compared to the conventional ones, and it is clear that the memory retention characteristics are longer than 105 hours. .

As mentioned above, according to the present invention, the MN08FET
Note 1. The effect of the reform on retention characteristics is quite striking.

In addition, in the above explanation, MNO8FE'l' is limited to MNO8FE'l' as an absolute gate type field effect transistor that has a gate insulating layer having a box structure. Toshi 1 Alumina (A,llt On)
Similar effects can be obtained even when the present invention is applied to tsiN 08 FET using skin. Further, as the impurity to be added, one of the above-mentioned impurities may be F (purple fluoride) or the like.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the trapped hole density distribution in 5i3N4) & of a P-channel MN OS FjruT immediately after the application of a negative voltage. FIG. A cross-sectional view showing the structure, FIG. 3, is a diagram in which the memory retention characteristics of the P-channel MNO8FET are destroyed by limiting the threshold voltage, and 11 is a conventional MN08FET. 12 shows the threshold value and pressure change of the MNO8FET according to the present invention, respectively. 1... N-type Si substrate, 2... Thermal oxidation S
in, layer, 3...S import N4 layer by CVD method,
4...Added hydrogen atom, 5...A
l gate electrode. No. / Figure ↓ @ 7) 岨1壬”JL goose, l forcep゛ (I (Jn, 1U41γ) thickness direction

Claims (1)

[Claims] 1. Gate insulation between a first dielectric layer formed on the surface of a semiconductor substrate and a second dielectric layer formed to cover the surface of the first dielectric layer. In the insulated gate field effect transistor trap provided as a layer, an impurity is added to the second dielectric layer to compensate for trapping centers for electrons or holes existing in the second dielectric layer. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the impurity added to the second dielectric layer is hydrogen. 3. The semiconductor device according to claim 1, wherein the impurity added to the second dielectric layer is chlorine.