JPS5975491A - Integrated circuit device incorporated with memory control circuit - Google Patents

Abstract

PURPOSE:To reduce the number of components for system constitution, by multiplexing an address corresponding to mode information representing types of RAMs. CONSTITUTION:This system consists of an integrated circuit 30, a clock generator 11 and a memory 14. A timing signal generator 31 generates a control signal and an address selecting signal of a dynamic RAM by an external reference clock CLK. An address multiplexer 32 inputs a memory address in 16-bit and a refresh address in 8-bit, then, the address is switched and controlled response to the timing of the address selecting signal and outputs them to terminals X0-7. Further, a mode register 33 decides the multiplex form of the address and a refresh address counter 34 manages a refresh address 8-bit of the RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an integrated circuit device, and particularly to an integrated circuit device with a built-in memory control circuit that can directly drive a dynamic RAM.

[Prior art]

FIG. 1 shows the configuration of a system that uses a dynamic f(, AM) as a storage device. The integrated circuit device 10 controls a large capacity memory fd via a 16-bit address bus and an 8-bit data path.Representative integrated circuit devices that handle such a large capacity memory include each ( A microprocessor, CR, T control device, etc. A clock generator 11 generates a reference clock for each part. A timing signal generator 12 generates a dynamic RAM control signal and a RAM address multiplexer.
Generates timing signals, etc. The address multiplexer 13 converts the 16-bit address signal into dynamic R, A
M row and column addresses are multiplexed and 8 RA
The memory 14 outputs eight 6's on the M address line.
It consists of 4 kilobit dynamic R and AM.

FIG. 2 shows an operation time chart of dynamic R and AM. A row address (R, A,) and a column address (CA) are time-divisionally loaded multiple times M f on the address line. As a control signal, a row address strobe (R,As),
Column address strobe (cAs), write control signal (
The timing of the control 141 signal that requires WE) differs depending on the type of R and AM used.

In this way, by using highly integrated dynamic RAM, the number of memory chips can be reduced.
Timing signal generator 12 and address multiplexer 1
A circuit such as 3 is required. .

Conventionally, these circuits were prepared using individual parts, which had the disadvantage of increasing the number of parts and making the system complex.

Another disadvantage of dynamic RAM is that the storage is temporary and must be refreshed within a certain period of time. For this reason, refresh
It is necessary to provide an address counter and refresh timing control circuit. Conventionally, integrated circuit devices [10] that have a built-in refresh address counter and devices that integrate a refresh address counter and an address multiplexer have been announced. ,Also,
R, AM with built-in refresh address counter
There are also elements. However, in either case, since only a refresh address counter is built in, an external circuit for controlling the refresh timing is required.

[Purpose of the invention]

The purpose of this research is to provide an integrated circuit device with a built-in memory control circuit that can be directly connected to various dynamic RAMs and RAMs in order to limit the number of system components.

[Summary of the invention]

A feature of the present invention is that addresses are multiplexed in accordance with mode information indicating the type of dynamic RAM to be connected.

Embodiments Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 shows an integrated circuit device 30 according to an embodiment of the present invention and a dynamic F1. An example of a system configuration with 11 AMs is shown. The integrated circuit device 30 includes a timing signal generator 31, an address multiplexer 32, a mode register 33, and a refresh address counter 34. The system includes a quadruple integrated circuit device 30, a clock generator 11. It has a simple configuration consisting of a memory 14. The timing signal generator 31 generates l'inamik'fc from a reference clock signal (CLK) inputted from the outside.
Generates AM control signals and address selection signals. The dynamic RAM control signals include a row address metronome (R, As) and a column address strobe (CAB).

There is a write control signal (WE), which is output from the output terminal of the integrated circuit device 30.Address selection signals include a row address selection signal (A), a column address selection signal (CA), and a refresh address selection signal. Signal (R
The address multiplexer 32 (EF) inputs a 16-bit memory address (AO to 15) and an 8-bit refresh address (FLO to 7), and switches the address according to the timing of address selection signals RA, CA, and REF. The mode register 33 is a register that determines the address multiplex format, and in this implementation, the mode for connecting 16 kilobits R and AM and the mode for connecting 64 kilobits RAM are used. This is a 1-bit register that specifies all modes. Refresh address counter 3
4 is the dynamic RAM refresh address 8
It manages bits and has the function of incrementing bits by 1 each time a refresh address selection signal (RE F ) is input.

According to this embodiment, the timing generation circuit 31, address multiplexer 32, and refresh address counter 34 are built into the integrated circuit device 30, so that the number of system parts can be significantly reduced. In addition, since the function of the address multiplexer 32 is switched by the mode register 33 and its output signal (M), multiple types (16 kilobits in this implementation ff1J) of RA
Dynamic R (2 types: M and 64 kilobit RAM)
Can support AM.

FIG. 4 shows the dynamic R, A in the implementation row of FIG.
The timing of the row address signal (RAS), column address signal (CAB), fill-in control signal (WE), and RAM address (XO to 7) showing the time chart of the M it control signal is compared with the reference clock (CLK). Shown in parallel. Parameter a shown in the figure.

By using b, c, and d, the timing can be set programmably in units of the period of the reference clock (CLK). Therefore, various dynamic R's with different operation timings,
A monkey that corresponds to A.M.

FIG. 5 shows the address multiplexer 320 circuit in detail. Address selection timing signals RA, CA, R,
The addresses output to the output terminals (XO-7) are appropriately selected by EF, and the 2-Okegawa multiplex mode is selected by the mode signal (M). 1st
The table summarizes the address bits that are output at each timing.

At the timing of RA=1, row address -&E, CA=1
At the timing of REF=1, the column address is outputted, and at the timing of REF=1, i(, A=0.CA20, and 7 retrieval addresses (R, 0 to 7) are output;, terminals XO, - For X5, AO to A5 are selected as row addresses and A8 to A13 are selected as column addresses, regardless of the 1st position of M., M=0 (64KRAM mode)
In this case, A6 and A14 are connected to terminal X6, and A6 and A14 are connected to terminal X7.
7 and A15 are each output as multiplex.
= 1 (16KRA, M mode), terminal X6 has A
6 and A7 are multiplexed output, and terminal X7 has rows,
A14 is output at both timings of the column. In this embodiment, a mode register is provided to hold the mode signal, but there is also a method of directly supplying the signal M from an external terminal. As mentioned above, in this embodiment, 64KRAM
Is the mode j Karasu from XO to X7? , L6KB, and in the case of AM mode, X O-X 6 can be directly connected to the address terminals of the RAM, respectively.

〔Effect of the invention〕

According to the present invention, the number of parts for the system configuration can be reduced by using an integrated circuit device with a built-in memory control circuit that can support a plurality of dynamic R and AM systems.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of a system configuration using Juto's dynamic R and AM, and Figure 2 is a block diagram showing an example of a system configuration using Juto's dynamic RA.
FIG. 3 is a block diagram of one embodiment of the present invention, FIG. 4 is an operation time chart of FIG. 3, and FIG. 5 is a circuit diagram of the address multiplexer of the present invention. 30...' Tosei circuit device, 31... Timing signal generator, 32... Address multiplexer, 33...
・Mode register, 34... Refresh address number 12 2nd figure LM attribution = ×
Figure RAM Atoms

Claims (1)

[Claims] 1. Address information generated within an integrated circuit device or given from another source in a device that switches and outputs information of a plurality of address pits to one output terminal or input/output terminal. means for inputting 3 or more bits of and selectively outputting them to one terminal; 1. An integrated circuit device with a built-in memory control circuit, comprising means for multiplexing at least two of the bits in a time division manner and outputting the multiplexed signal to one terminal. 2. The integrated circuit device with a built-in memory control circuit as set forth in claim 1, further comprising means for counting dynamic R and AM refresh addresses. 3. An integrated circuit device with a built-in memory control circuit according to claim 1, further comprising means for generating a row address strobe signal and a column address strobe signal of a dynamic AM.