JPS5979486A - Sense amplifier - Google Patents

Abstract

PURPOSE:To obtain a high speed as well as a wide dynamic range and at the same time to ensure a latching function by using two differential sense amplifiers and applying a positive feedback between these two sense amplifiers. CONSTITUTION:It is supposed that digit lines D and D' are precharged. In such a case, the potential of an output terminal O is decided by the ON resistance ratio between a PchMOSFET11 and NchMOSFET13 and 15. So is with a terminal O'. Here NchMOSFET25 and 15 function as constant current sources respectively. If an address is selected and a difference of potential is produced between lines D and D', either one of these two lines is changed to a high level with the other changed to a low level respectively. The sensitivity of a sense amplifier is increased since the working points of both FET15 and 25 are at a saturated region. In such a way, a positive feedback is applied to two differential amplifiers to invert the output at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a static random access memory (
(hereinafter referred to as SRAM), and particularly relates to sense amplifiers used in readout circuits thereof.

Conventional SRAM readout circuits have included a differential sense amplifier shown in FIG. 1 or an F/F type latch circuit shown in FIG. Comparing the two, the differential sense amplifier is superior in terms of sensitivity, and this type of sense amplifier is often used in recent 8RAMs. However, in the case of this differential sense amplifier, the output amplitude is VDD or GND-
j, and a gate for waveform shaping was required.0 Now, to explain the operation of the sense amplifier shown in Fig. 1, which is composed of CMO8, first, the gate connected to the input gates 3 and 4 of the sense amplifier is Assume that the true complementary digit line D is precharged to a certain voltage level Vc.

Next, when one address is selected by the address enable signal, the potential of one digit line decreases in accordance with the information stored in the selected E and AM cells. At this time, the voltage difference that occurs at the differential input of the sense amplifier is amplified, and the output is at a high ()4high) level or a low (Lo) level.
w) Become a level. At this time, the points to be poured are that the output at point A in Figure 1 swings from VDD to 7M, but the output at point B is Vp.
It can only swing from to 7M.

Here, 7M is the potential at point M, and CVp is approximately from VDD to Pc
h It is the value obtained by subtracting ■T of MOSFET 2.

When extracting output only from the fiA point, the output voltage does not drop to O volts, and when extracting differential output, the differential output will be VDD depending on whether the read data is 111 or 101.
Both the cases of vMO and V, -VM are possible. From the viewpoint of access time, this results in that the access time differs depending on whether the data to be read is Jf or 101.

The present invention eliminates the above drawbacks and provides a sense amplifier that is high speed and has a large dynamic range.

The present invention relates to a MOSFET of a first conductivity type and a MOSFET of a second conductivity type in which a source electrode is connected to a first power supply terminal and whose gate electrodes and one drain terminal are interconnected. The electrode is the MO8
MO8'FET connected to the drain electrode of FET 1
3 and a MOSFET 4 whose drain electrode is connected to the drain electrode of the MO8FET 2;
8FET 3. A first differential amplifier consisting of interconnecting the source electrodes of 4 and a MOSFET of a second conductivity type connected in series between this terminal and a second power supply, and a second differential amplifier having exactly the same structure. MOSFE of the first differential amplifier.
Connect one digit line to T3 and the gate electrode of MOSFET4 of the second differential amplifier, and connect one digit line to the gate electrode of MOSFET4 of the second differential amplifier.
OSFET4 and second differential amplifier MO8F'ET3
, connect the output of the first differential amplifier to the gate of MOSFET 5 of the second differential amplifier, and connect the output of the second differential amplifier to the gate of MOSFET 5 of the first differential amplifier.
This is a static RAM sense amplifier connected to FET5.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 shows an embodiment of the present invention. The diagram shows the Oitetijit line! :D is charged up to a certain precharge level Vc.

At this time, the potential of the output terminal O is Pch MO8FB'l"
11 and the on-resistance of Nch MOSFETs 13 and 15. The same goes for the season. 0 here
and 0 potential as gate 1[j pressure
FET25.15 is in the saturation region and operates as a constant current source. D and D due to the address being selected now.
If a potential difference occurs between them, one of the 0.0's will start to move to high level and the other will start to move to low level. Since the operating point of MOSFET15.25 is in the saturation region, it is used as a sense amplifier and has high teno sensitivity.

For the sake of simplicity, if we assume that V[D)>V(D), the potential of 0 starts to rise and the potential of the stone starts to fall accordingly. As the potential of 0 increases, the potential of the terminal (2M) further pushes down the potential of the lower terminal. On the other hand, since the potential of σ has decreased, the potential of the terminal (IM) further pushes up the potential of the upper terminal (IM). As described above, positive feedback is applied to the two differential amplifiers, and the output is inverted at high speed.

Further, release from the latched state is performed by precharging the digit line. Well, the potential of 9D rises to V(
D)=V(5), MO8FE'l'24
When the on-resistance of the terminal (2B) decreases, the potential of the terminal (2B) decreases. As a result, the on-resistance of M, 08FE't''21 increases the potential of the lower terminals (2 people), turns on MOS FET' 15, and decreases the potential of the terminal (IA). After the above process, the initial state is reached. will be set up.

As explained above, the present invention uses two differential sense amplifiers and applies positive feedback between them to realize a sense amplifier that is fast, has a wide dynamic range, and also has a latch function. It is something to do.

[Brief explanation of drawings]

Figure 1 shows a conventionally used differential sense amplifier.
FIG. 2 shows an F/F type sense amplifier, and FIG. 3 shows an embodiment of the present invention. D, D...Tigit line. Figure 1 Figure 2 Oθ 3rd session

Claims (1)

[Claims] A diode-connected MOSFET is used as a load for one input transistor, and the gate electrode thereof is interconnected with the gate electrode of the diode-connected MOSFET.
Mouse 1 with 08FET as the load of the other input transistor
and a second differential amplifier having exactly the same structure as the first differential amplifier, one digit S of the memory is input to the first input of the first differential amplifier,
the other digit line is connected to the second input of the first differential amplifier and the first input of the second differential amplifier; A sense amplifier characterized in that the outputs of the differential amplifiers are connected to gate electrodes of constant current sources M08FE'l'' of the second and first differential amplifiers, respectively.