JPS5980929A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5980929A
JPS5980929A JP57191558A JP19155882A JPS5980929A JP S5980929 A JPS5980929 A JP S5980929A JP 57191558 A JP57191558 A JP 57191558A JP 19155882 A JP19155882 A JP 19155882A JP S5980929 A JPS5980929 A JP S5980929A
Authority
JP
Japan
Prior art keywords
film
aluminum
layer
wiring layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57191558A
Other languages
Japanese (ja)
Inventor
Masahiro Kuwagata
桑形 正博
Hirotsugu Hattori
服部 裕嗣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP57191558A priority Critical patent/JPS5980929A/en
Publication of JPS5980929A publication Critical patent/JPS5980929A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To form the surface to a curved surface shape, and to prevent the generation of a defect such as a crack in the end section of the wiring of a passivation film by etching an aluminum film formed on a substrate to a predetermined electrode shape and thermally treating the whole under vacuum or in an inert gas through a high-speed heating method. CONSTITUTION:A silicon dioxide film 2 is formed to the surface of the silicon substrate 1 through a thermal oxidation method. A predetermined opening section is formed, and an impurity forming a P-N junction to the silicon substrate 1 is diffused and introduced through the opening section to form a diffusion region 3. An electrode wiring layer 4 consisting of the aluminum film is formed on the diffusion region 3, and the aluminum-film electrode wiring layer 4 is changed into a gentle curved-surface shape by melting through heat treatment by quick heating in a short time under vacuum or in the inert gas. The layer 4 is coated with a silicon dioxide film 6 consisting of the passivation film.

Description

【発明の詳細な説明】 産業上の利用分野 この発明は半導体装置の製造方法、とくに、半導体基板
上に設けられるアルミニウム膜電極配線層の処理工程を
含む製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a step of treating an aluminum film electrode wiring layer provided on a semiconductor substrate.

従来例の構成とその問題点 半導体基板内に所望の機能素子をそなえた半導体装置は
、配線用電極を設けたのち、これらを被覆するパシベー
ション膜を付設する構造がしばしば用いられる。このパ
シベーション膜は、通常、酸化シリコン膜や窒化シリコ
ン膜が気相蒸着法(以下、CvDと略称する)で形成さ
れるが、製造工程の最終の段階で設けられるので、この
被膜にクラックなどの欠陥が存在すると、以降の工程で
復修することがほとんどできず、経時不良の要因になる
Conventional Structures and Their Problems Semiconductor devices in which desired functional elements are provided in a semiconductor substrate often have a structure in which wiring electrodes are provided and then a passivation film is provided to cover these electrodes. This passivation film is usually formed using a silicon oxide film or a silicon nitride film using a vapor phase deposition method (hereinafter abbreviated as CvD), but since it is provided at the final stage of the manufacturing process, cracks etc. may occur in this film. If a defect exists, it is almost impossible to repair it in subsequent steps, which causes defects over time.

第1図示の従来例半導体装置で詳しくみると、半導体基
板1の表面に選択拡散用の絶縁膜として酸化シリコン膜
2を設け、これに所定の開孔部を形成し、ついでぐこの
開孔部を通じて、基板1とは反対導電型の拡散領域3を
形成し、これにオーミックコンタクトをなすアルミニウ
ム金属配線層4を設けたのち、これらを被覆して、全面
に酸化シリコン膜によるパシベーション膜5を形成した
ものでは、アルミニウム金属配線層4の端部、すなわち
、パターン加工の食刻面と平坦な表面との交差先端6が
鋭くとがっており、これを覆う部分にクラック7が入り
易い。また、り′ラックが入らない首でも、その部分の
厚さが薄くなり、パシベーション膜5はその先端部分に
欠陥ができ易く、信頼性を損なう原因をもっているとも
言える。
Looking at the conventional semiconductor device shown in FIG. 1 in detail, a silicon oxide film 2 is provided on the surface of a semiconductor substrate 1 as an insulating film for selective diffusion, a predetermined opening is formed in this, and then the opening is A diffusion region 3 of a conductivity type opposite to that of the substrate 1 is formed through the substrate 1, and an aluminum metal wiring layer 4 forming an ohmic contact is provided thereon, and then a passivation film 5 made of a silicon oxide film is formed over the entire surface. In this case, the end portion of the aluminum metal wiring layer 4, that is, the intersection tip 6 of the etched surface of the pattern and the flat surface is sharp, and cracks 7 are likely to occur in the portion covering this. Furthermore, even in the case where the rack does not fit into the neck, the thickness of that part becomes thinner, and the passivation film 5 is more likely to have defects at its tip, causing a loss of reliability.

発明の目的 この発明は、上述のような半導体装置でパシベーション
膜に欠陥の生じないような処理方法を提供するものであ
り、これによって(半導体装置の信頼性の向上をはかる
ことを主たる目的としたものである。
Purpose of the Invention The present invention provides a processing method that does not cause defects in the passivation film of a semiconductor device such as the one described above. It is something.

発明の構成 この発明は、半導体基板上に形成されたアルミニウム膜
を所定電極形状に食刻したのち、真空または不活性ガス
中で高速加熱法によシ熱処理する工程を有する半導体装
置の製造方法を与えるものであり、これによシ、アルミ
ニウム膜は最表面層を瞬間的に溶融状態にし、とがった
先端部分をなだらかな曲面状にすることができ、したが
って、この電極層上にパシベーション膜を形成したとき
に、同パシベーション膜を一様な厚みで付設することが
できる。
Structure of the Invention The present invention provides a method for manufacturing a semiconductor device, which includes a step of etching an aluminum film formed on a semiconductor substrate into a predetermined electrode shape, and then heat-treating it by a high-speed heating method in a vacuum or an inert gas. As a result, the outermost layer of the aluminum film can be melted instantaneously, and the sharp tip can be made into a gently curved surface. Therefore, a passivation film can be formed on this electrode layer. In this case, the passivation film can be applied with a uniform thickness.

実施例の説明 以下に、この発明を実施例により詳しくのべる。Description of examples The present invention will be described in detail below with reference to Examples.

第2図は、この発明の実施例を工程順に示した半導体装
置要部の断面図である。まず、第2図(a)のように、
シリコン基板1の表面に、通常の熱酸化法によって、厚
さ約8ooO入の二酸化シリコン膜2を形成する。そし
て、この二酸化シリコン膜2に周知のホトリソグラフィ
技術で所定の開孔部を設け、ついで、この開孔部を通じ
て、シリコン基板1に対してPN接合を形成するような
不純物を拡散導入し、拡散領域3を形成する。この後、
拡散領域3上にアルミニウム膜の電極配線層4を形成す
る。この段階では、アルミニウム膜電極配線層4は食刻
加工直後で端部6がほぼ直角であり、鋭くとがったまま
の状態である。そこで、次に、このアルミニウム膜に対
して高速加熱法による熱処理を施す。この熱処理として
は、真空中あるいは窒素、アルゴンなどび不活性ガス中
で、カーボン発熱体あるいはキセノンランプから赤外線
(熱線)を発生させ、この熱源で、10秒〜30秒間加
熱する方式が有効である。真空中ないしは不活性ガス中
であれば、アルミニウムの酸化が防止でき、また、短時
間の急速加熱により、半導体基板1内での不純物拡散面
の変動もほとんど起らない。
FIG. 2 is a sectional view of a main part of a semiconductor device showing an embodiment of the present invention in the order of steps. First, as shown in Figure 2(a),
A silicon dioxide film 2 having a thickness of approximately 800 mm is formed on the surface of a silicon substrate 1 by a normal thermal oxidation method. Then, predetermined openings are formed in this silicon dioxide film 2 using a well-known photolithography technique, and then impurities that form a PN junction with the silicon substrate 1 are diffused and introduced through the openings. Region 3 is formed. After this,
An electrode wiring layer 4 of an aluminum film is formed on the diffusion region 3 . At this stage, the ends 6 of the aluminum film electrode wiring layer 4 are almost right-angled and remain sharp immediately after the etching process. Therefore, next, this aluminum film is subjected to heat treatment using a high-speed heating method. An effective method for this heat treatment is to generate infrared rays (heat rays) from a carbon heating element or xenon lamp in a vacuum or in an inert gas such as nitrogen or argon, and heat the material for 10 to 30 seconds with this heat source. . In a vacuum or inert gas, oxidation of aluminum can be prevented, and rapid heating for a short time causes almost no change in the impurity diffusion surface within the semiconductor substrate 1.

この熱処理を施すと、第2図(b)のように、アルミニ
ウム膜電極配線層4は溶融によりなだらかな曲面形状に
なる。第2図(C)は、その上にパシベーション膜の二
酸化シリコン膜6を周知のCVD技術によって被設した
ものであシ、このパシベーション膜は、クラワクなどの
欠陥が発生せず、はぼ均一な厚みのものになっている。
When this heat treatment is performed, the aluminum film electrode wiring layer 4 is melted into a gently curved shape as shown in FIG. 2(b). In FIG. 2(C), a silicon dioxide film 6, which is a passivation film, is deposited on top of the passivation film using the well-known CVD technique. It is thick.

第3図および第4図はこの発明の実施によって得られた
他の半導体装置例を示す電極形状の平面図およびそのA
−A’断面図である。この場合、電極配線層が下地層8
と上層のアルミニウム電極層4とで構成されたものであ
る。たとえば、高密度集積回路のように、電極配線層の
間隔Wが小さいと、隣接する両電極線層間で短絡の不良
を起すことがある。そのような不良発生を避ける手段と
して、配線層を二層構造になし、下地層8には食刻加工
性のよい金属を用い、この上にアルミニウム膜電極層4
を形成すると、好適な配線層が形成できる。この場合、
下地層8には、タングステン、チタン、モリブデン、白
金、あるいはタングステン−チタン合金が選ばれる。そ
して、この下地層8に対してアルミニウム膜を積ねて形
成し、これを上述の実施例のように高速加熱法で熱処理
すると、上層のアルミニウム膜のみが溶融し、下地層8
とよくなじみ、また、アルミニウム膜4による配線層間
の短絡不良も起りにくい。しかも、配線層の上層側アル
ミニウム膜表面は急速な加熱処理によってなだらかな曲
面形状になるので、これらの表面にパシベーション膜を
形成したとき、同パシベーション膜の段切れは起らない
3 and 4 are plan views of electrode shapes showing other examples of semiconductor devices obtained by implementing the present invention, and FIG.
-A' sectional view. In this case, the electrode wiring layer is the base layer 8
and an upper aluminum electrode layer 4. For example, if the interval W between the electrode wiring layers is small as in a high-density integrated circuit, a short circuit may occur between adjacent electrode wiring layers. As a means to avoid the occurrence of such defects, the wiring layer has a two-layer structure, the base layer 8 is made of a metal with good etching properties, and the aluminum film electrode layer 4 is placed on top of this.
By forming this, a suitable wiring layer can be formed. in this case,
For the base layer 8, tungsten, titanium, molybdenum, platinum, or a tungsten-titanium alloy is selected. Then, when an aluminum film is laminated and formed on this base layer 8 and this is heat-treated by a high-speed heating method as in the above-mentioned embodiment, only the upper aluminum film melts, and the base layer 8 is heated.
In addition, short-circuit failures between wiring layers due to the aluminum film 4 are less likely to occur. Furthermore, since the surface of the upper aluminum film of the wiring layer is formed into a gently curved surface by rapid heat treatment, when a passivation film is formed on these surfaces, breakage of the passivation film does not occur.

発明の効果 以上に詳しくのべたように、この発明によれば、半導体
基板上に形成されたアルジニウム膜を所定電極形状に食
刻したのち、真空または不活性ガス中で高速加熱法によ
り熱処理する工程で、アルミニウム膜電極配線層の表面
がなだらかな曲面形状[;l)、この上にパシベーショ
ン膜を設けたとき、同パシベーション膜はその配線端部
でクラ・ンク等の欠陥が発生せず、半導体装置の信頼性
は顕著に向上する。
Effects of the Invention As described in detail above, according to the present invention, there is a step of etching an aldinium film formed on a semiconductor substrate into a predetermined electrode shape, and then heat-treating it by a high-speed heating method in a vacuum or an inert gas. Therefore, when the surface of the aluminum film electrode wiring layer has a gently curved shape [;l), and a passivation film is provided on top of this, the passivation film does not cause cracks or other defects at the ends of the wiring, and the semiconductor The reliability of the device is significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例半導体装置の要部断面図、第2図(a)
〜(C)はこの発明の実施例を示す工程順断面図、第3
図および第4図はこの発明の他の実施例で得られる半導
体装置の要部平面図およびそのA−A’断面図である。 1・・・・・・半導体基板、2・・・・・・絶縁膜、3
・・・・・・拡散領域、4・・・・・・アルミニウム膜
電極層、5・・・・・パシベーション膜、6・・・・・
・電極層端部、7・・・・・・クラック、8・・・・・
・下地層。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第3図 第4図
Figure 1 is a sectional view of the main parts of a conventional semiconductor device, Figure 2 (a)
~(C) is a process order sectional view showing an example of this invention, No. 3
FIG. 4 is a plan view of a main part of a semiconductor device obtained in another embodiment of the present invention, and a sectional view thereof taken along line AA'. 1... Semiconductor substrate, 2... Insulating film, 3
... Diffusion region, 4 ... Aluminum film electrode layer, 5 ... Passivation film, 6 ...
・Edge of electrode layer, 7...Crack, 8...
・Substrate layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に形成されたアルミニウム膜を所定
電極形状に食刻したのち、真空または不活性ガス中で高
速加熱法によシ熱処理する工程を有する半導体装置の製
造方法。
(1) A method for manufacturing a semiconductor device, which includes a step of etching an aluminum film formed on a semiconductor substrate into a predetermined electrode shape, and then heat-treating it by a high-speed heating method in a vacuum or an inert gas.
(2)アルミニウム膜が半導体基板上に絶縁膜を介して
設けられたタングステン、チタン、モリブデン、白金か
ら選ばれた金属層上に形成される特許請求の範囲第1項
に記載の半導体装置の製造方法。
(2) Manufacturing the semiconductor device according to claim 1, wherein the aluminum film is formed on a metal layer selected from tungsten, titanium, molybdenum, and platinum provided on the semiconductor substrate with an insulating film interposed therebetween. Method.
JP57191558A 1982-10-29 1982-10-29 Manufacture of semiconductor device Pending JPS5980929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57191558A JPS5980929A (en) 1982-10-29 1982-10-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57191558A JPS5980929A (en) 1982-10-29 1982-10-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5980929A true JPS5980929A (en) 1984-05-10

Family

ID=16276667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57191558A Pending JPS5980929A (en) 1982-10-29 1982-10-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5980929A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7811160B2 (en) 2003-09-24 2010-10-12 Kabushiki Kaisha Tokai Rika Denki Seisakusho Operating device of vehicle air conditioner

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7811160B2 (en) 2003-09-24 2010-10-12 Kabushiki Kaisha Tokai Rika Denki Seisakusho Operating device of vehicle air conditioner

Similar Documents

Publication Publication Date Title
US5093710A (en) Semiconductor device having a layer of titanium nitride on the side walls of contact holes and method of fabricating same
JPS61142739A (en) Manufacture of semiconductor device
JP2502269B2 (en) Method for forming a corrosion resistant multilayer metal structure
JPS6213819B2 (en)
JPS6364057B2 (en)
JPS5980929A (en) Manufacture of semiconductor device
US3748543A (en) Hermetically sealed semiconductor package and method of manufacture
JPS61225837A (en) Layer connection of semiconductor device
JPS61156872A (en) Semiconductor device
JPH0143458B2 (en)
JPH02260535A (en) Manufacturing method of semiconductor device
KR100199526B1 (en) Semiconductor device and manufacturing method thereof
JPH01272138A (en) Manufacture of wiring
JPS59227119A (en) Silicon semiconductor device
JPS62291146A (en) Manufacture of semiconductor device
JPH01192140A (en) Semiconductor integrated circuit device
JPH01235253A (en) Manufacture of semiconductor device
JPH02249273A (en) Semiconductor device
JPH0586666B2 (en)
JPH028463B2 (en)
JPS6213053A (en) Semiconductor device
JPS62163345A (en) Manufacture of semiconductor device
JPS61226958A (en) Semiconductor device and manufacture thereof
JPH01154532A (en) Semiconductor device
JPH03157925A (en) Manufacture of semiconductor device