JPS5980941A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of a parasitic channel by forming a groove section by etching an element isolation region is tapered manner and implanting the ions of an impurity of the same conduction type as a substrate to the peripheral section of the groove section. CONSTITUTION:A mask material 32 is used as a mask, the ions of the impurity 33 of the same conduction type are implanted into the element isolation region of the silicon substrate 31, and the whole is thermally treated, thus controlling the profile of the impurity 33 going around from the periphery. The groove section 34 is formed through anisotropic etching at an angle theta, the ions of the impurity 35 of the same conduction type as the substrate are implanted, the mask material 32 is removed, and an oxide film 36 is buried flatly. A gate oxide film 37 and a gate electrode 38 are formed, and source-drain diffusion layers are formed. Accordingly, an inversion preventive layer having desired profiles in a corner section 40 and a side surface 39 is formed, and the generation of the parasitic channel can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in an element isolation method for isolating each element on a semiconductor substrate.

[Technical background of the invention and its problems]

In semiconductor devices manufactured using silicon semiconductor substrates, especially MO8 type semiconductor devices, in order to eliminate insulation defects due to parasitic channels and reduce parasitic capacitance, the required field regions (element isolation regions) between elements are Forming a thick oxide film is being practiced. Conventionally, oxidation f
As one of the element isolation methods used in lKt-, a trench is formed by partially etching the silicon substrate in the field region.
CVD technology is used to form this trench, and the dimensions of the field isolation region are determined by the dimensions of the trench that is formed with high precision.This technology is extremely useful in manufacturing highly integrated semiconductor devices. .

The conventional element isolation method will be briefly explained with reference to Fig. 1 (-) to (@) t''. First, as shown in Fig. 1 (,), an op type (100) A silicon substrate 11 is prepared, and a mask material 12 is entirely formed on the element formation region of this substrate 11. Next, as shown in FIG. Then, a groove 13 having a depth of, for example, about 0.6 [μm] is formed.

Thereafter, as shown in FIG. 3C, ions of the substrate 11 and a corridor-shaped impurity 14 are implanted into the surface of the silicon substrate 11. Subsequently, as shown in FIG. 2D, an insulating film 15f is buried in the trench 13, and its surface is planarized. Furthermore, the same figure (,)
A dirt oxide film 16 and a dirt electrode 17 are formed as shown in FIG. 2, and thereafter, for example, a MOS transistor is fabricated by a well-known method.

However, this type of conventional method has the following problems. That is, when a voltage is applied to the dirt electrode 17, electric field concentration occurs at the corner portion 18 shown in FIG. By applying the voltage D, l'-), a parasitic channel is formed in the silicon corner portion 18 at a dart voltage lower than the original dark value voltage of the MOS transistor. FIG. 2 shows this state. Figure 2 shows the sub-threshold characteristics (log ID-V, %) of the prototype MOS transistor. (Curve Q) are superimposed, so a kink characteristic as shown by the dotted line in the figure appears. In this way, the parasitic transistor formed in the corner portion 18 causes leakage current in the OFF state, and becomes a major factor in deteriorating device characteristics.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent the occurrence of parasitic channels and improve device characteristics.

[Summary of the invention]

The gist of the present invention is to form a groove by etching the element isolation region FF-PA of a semiconductor substrate, and to implant ions of impurities of the same conductivity type as the substrate into the peripheral portion of the groove, thereby preventing the generation of parasitic channels in the corner portions described above. The purpose is to prevent it.

That is, in the present invention, when a semiconductor device is completely manufactured using an element isolation method in which an insulating film gold ingot is inserted into an element isolation region, a mask material is formed on the element formation region of a semiconductor substrate, and then this masking material is used. Impurities of the same conductivity type as the substrate are ion-implanted into the element isolation region of the semiconductor substrate, and then the element isolation region is etched at a desired angle using the mask to form a groove. Then, ions of impurities of the same conductivity type as the substrate are again implanted into the groove.
In this method, an insulating film is then filled in the trench, and then all desired elements are formed on the element formation region.

〔Effect of the invention〕

According to the present invention, impurity ions for preventing inversion can also be ion-implanted into the corner portions of the element formation region, so that generation of parasitic channels in the corner portions can be reliably prevented. Therefore, leakage current etc. in the OFF state can be eliminated and device characteristics can be significantly improved.

[Embodiments of the invention]

FIG. 3(,) to (f) are MOs according to an embodiment of the present invention.
S) It is a sectional view showing a transistor manufacturing process.

First, as shown in Figure 3 (,), the specific resistance is 5 to 50 [Ωcm
-' ) P-type (1oo) silicon substrate (semiconductor substrate)
31 is prepared, and an oxide film 'e0.4Cμ is formed on this substrate 31.
m] by applying the normal photo engraving process,
Mask material 32t is left behind only on the element formation region.
- form. Next, as shown in FIG. 3B, using the mask material 321c as a mask, an impurity 33 having the same conductivity type as that of the substrate 31, such as B, is added to the element isolation region of the silicon substrate 31.
i ion implantation. At this time, the impurity 33 is removed from the mask material 3.
It also partially extends into the element formation region under 2 from the periphery.

Thereafter, by performing heat treatment, for example, the profile of the impurities 33 coming from the periphery can be controlled.

Next, as shown in FIG. 3C, using the same mask cutter 32, the silicon substrate 31 is anisotropically etched at an angle .theta. to form a groove 34. Typically, when etching is performed using a mixture of KOH and isozorobyl alcohol, θ is 54.7 degrees. At this time, a portion of the impurity 33 remains in the etched side surface of the substrate. Then the third
As shown in Figure (d), impurity 35 having the same conductivity type as the substrate is ion-implanted into the groove 34 formed by the etching process using the same mask material 32. Thereafter, as shown in FIG. 3(a), the mask material 32 is removed, and an oxide film (insulating film for element isolation) 36 is flattened in the trench 34. Note that this element isolation insulating film 36F! , it may be formed by selectively thermally oxidizing the substrate 31, or it may be filled with a CVD 8102 film using oxide film lift-off processing, oxide film planarization technology, etc. Next, using a well-known method, <? -) Form an oxide film 37 and a dirt electrode 38.

Further, by forming source/drain diffusion layers (not shown), a transistor 9M08) is completed.

Thus, according to this embodiment, the impurity concentration at the side surface 39 is the sum of the impurity concentration COS θ times the impurity concentration implanted in the second time and the impurity 33 left in advance, and can be adjusted by controlling the impurity profile. , an anti-inversion layer having a desired profile can be formed on the corner portion 40 and side surface 39.

Therefore, it is possible to prevent the generation of parasitic channels.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, as the mask material, in addition to a silicon oxide film, a silicon nitride film, an aluminum film, or a multilayer film of these materials can be used.

Furthermore, it goes without saying that the present invention can be applied not only to N-channel MOS transistors but also to various semiconductor devices.

[Brief explanation of drawings]

Figures 1 (,) to (,) are process cross-sectional views for explaining the conventional element isolation method, and Figure 2 is a diagram showing the A'OgID-vG characteristics of a MOS transistor formed by the conventional method.
FIG. 3(,) to (f) are MOs according to an embodiment of the present invention.
S) It is a sectional view showing a transistor manufacturing process. 3 No.... Silicon substrate (semiconductor substrate), 32... Mask material (silicon oxide film), ss, ss... Impurity (
? 34... Groove portion, 36... Oxide film (insulating film for element isolation), 37... f-) Oxide film, 38... Dirt electrode, 39... Side surface, 40... Corner part. Applicant's agent Patent attorney Takehiko Suzue 2

Claims (1)

[Claims] a step of forming a mask material on an element formation region of a semiconductor substrate; and a step of ion-implanting an impurity of the same conductivity type as that of the substrate into an element isolation region of the semiconductor substrate using the mask material;
Next, using the mask material, etching the element isolation region at a desired angle to form a groove portion;
Next, a step of implanting all ions of impurities of the same conductivity type as the substrate into the groove using the mask material, a step of embedding an insulating film in the groove, and a step of forming a desired element on the element formation region. A method for manufacturing a semiconductor device, comprising: