JPS5980948A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5980948A JPS5980948A JP58157809A JP15780983A JPS5980948A JP S5980948 A JPS5980948 A JP S5980948A JP 58157809 A JP58157809 A JP 58157809A JP 15780983 A JP15780983 A JP 15780983A JP S5980948 A JPS5980948 A JP S5980948A
- Authority
- JP
- Japan
- Prior art keywords
- base
- heat dissipation
- cap
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/12—Containers or parts thereof characterised by their shape
- H10W76/13—Containers comprising a conductive base serving as an interconnection
- H10W76/134—Containers comprising a conductive base serving as an interconnection having other interconnections parallel to the conductive base
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は集積回路等の半導体装置のパッケージ構造の改
良に関するう
半導体装置のパッケージにおける放熱特性の良否は素子
や回路の設計に重要な係りを持つ、特にアルミナその他
のセラミックス糸の材料をパッケージのベース、キャッ
プ等忙用いた場合、金属製のパッケージよりも放熱特性
が劣るために半導体素子や回路における熱発生を極力抑
えねばならず・このことによって素子設計に大きな制約
があった。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the package structure of semiconductor devices such as integrated circuits. When thread materials are used for package bases, caps, etc., the heat dissipation properties are inferior to those of metal packages, so it is necessary to suppress heat generation in semiconductor devices and circuits as much as possible.This places major constraints on device design. there were.
本発明の目的は、良好な放熱特性を有する半導体装置の
パッケージ構造を提供することにある。An object of the present invention is to provide a package structure for a semiconductor device that has good heat dissipation characteristics.
本発明のパッケージ構造は、半導体ペレットを固定すべ
きベース側からの放熱を促進するようにしたこと′４！
：特徴としており、以下１本発明を実施例を参照してさ
らに詳細に説明するつ
第１図ないし第３図は、いずれも本発明の実施例による
集積回路用デュアルイン・ライン型パッケージ構造の概
略縦断面図である。これらの図において÷１、はパッケ
ージのキャップ、２はベース。The package structure of the present invention promotes heat dissipation from the base side to which the semiconductor pellet is fixed '4!
Hereinafter, the present invention will be explained in more detail with reference to embodiments. Figures 1 to 3 each show a dual-in-line package structure for integrated circuits according to embodiments of the present invention. It is a schematic longitudinal cross-sectional view. In these figures, ÷1 is the cap of the package, and 2 is the base.
３は接着用低融点ガラス、４は外部リード、５は半導体
ペレット、６はリードワイヤ、７はベース２に設けられ
た放熱フィンである。3 is a low melting point glass for bonding, 4 is an external lead, 5 is a semiconductor pellet, 6 is a lead wire, and 7 is a heat dissipation fin provided on the base 2.
第１図の例においては、半導体ペレット５は。In the example of FIG. 1, the semiconductor pellet 5 is.
金めつきが施されたコバール、モリブデン等の熱膨張係
数の小さい金属からなるベース２ＫＡｕ−８ｉ共晶合金
等で固着せしめられ、半導体ペレット５と外部リード４
とはリードワイヤ６によって電気的に接続され、それら
は、ベース１とキャップ２とを低融点ガラス３で丁きま
なく封着することによってパッケージされている。この
ような構成においては、半導体ベレット５で発生した熱
の大部分は金属製のベース２を通して外気中に効率的忙
放散される。A base 2 made of a metal with a small coefficient of thermal expansion, such as gold-plated Kovar or molybdenum, is fixed with a KAu-8i eutectic alloy, etc., and a semiconductor pellet 5 and an external lead 4 are attached.
are electrically connected to each other by lead wires 6, and they are packaged by seamlessly sealing the base 1 and cap 2 with low melting point glass 3. In such a configuration, most of the heat generated by the semiconductor pellet 5 is efficiently dissipated into the outside air through the metal base 2.
また、ベースをセラミックにより構成した場合にも、基
板へ取付けた時、ベースが上側になるので１強制空冷、
金属フィンの接着等の２次的冷却手段を簡単に適用する
ことができる。Also, even if the base is made of ceramic, the base will be on the top side when attached to the board, so 1 forced air cooling,
Secondary cooling means such as bonding metal fins can be easily applied.
第２図の例は、第１図のものをさらに改良したもので、
ベース２の外側面に放熱フィン７を設けてあろうこのよ
うにすると、ベース部分での放熱特性を飛躍的に向上さ
せ５る。The example in Figure 2 is a further improvement of the one in Figure 1.
By providing the heat dissipation fins 7 on the outer surface of the base 2, the heat dissipation characteristics at the base portion are dramatically improved.
ここで、放熱フィン７は、ベース２から外気への放熱面
積を高める形状であれば特に制約をうけることはないが
あまり大きなスペースを要しない形状とすることが望ま
しい。また上記放熱フィンは、ベース２をセラミックス
）形成する場合には。Here, the heat dissipation fins 7 are not particularly limited as long as they have a shape that increases the heat dissipation area from the base 2 to the outside air, but it is desirable that the heat dissipation fins 7 have a shape that does not require a very large space. Further, in the case where the base 2 of the heat dissipation fin is formed of ceramics.
あとで第３図について説明するように予め型を用いて焼
結前に一体成型することもできるし、あるいはより高い
熱伝導性を有する材料でフィン部分を別に形成しておき
、これをベースに密着して接合せしめるなどの方法によ
ってベースに取付けてやることもできる。As explained later with reference to Figure 3, it is possible to use a mold in advance and integrally mold the material before sintering, or alternatively, the fin portion can be formed separately from a material with higher thermal conductivity and this can be used as a base. It can also be attached to the base by a method such as closely bonding.
第３図は１本発明の他の実施り様を示したもので、この
例では、セラミックス製のベース２に一体的に図示の形
状のセラミックス製放熱フィン７を形成しである。この
ようなパッケージ構造も前述例と同様に、放熱効果をよ
り高めることができると同時九半導体装置を回路基板等
に実装する時にフィン部分が邪魔にならないなどの効果
を有する。FIG. 3 shows another embodiment of the present invention, in which a ceramic base 2 is integrally formed with a ceramic heat dissipation fin 7 having the shape shown. Similar to the above-mentioned example, such a package structure also has the advantage that the heat dissipation effect can be further enhanced and at the same time, the fin portion does not get in the way when the semiconductor device is mounted on a circuit board or the like.
以上述べた如き本発明によれば、パッケージの放熱特性
を飛躍的に高めることができ、セラミックス系の比較的
熱伝導性の低い材料をパッケージに用いた場合でも半導
体装置における素子設計。According to the present invention as described above, the heat dissipation characteristics of the package can be dramatically improved, and even when a ceramic-based material with relatively low thermal conductivity is used for the package, it is possible to design an element in a semiconductor device.
回路設計上の制約を大巾に減少せしめることが可能とな
り１本発明の工業的効果は極めて大である。It is possible to greatly reduce restrictions on circuit design, and the industrial effects of the present invention are extremely large.
第１図ないし第３図は、いずれも本発明の実施例による
パッケージの縦断面図であろう符号の説明
１・・・キャップ、２・・・ベース、３・・・低融点ガ
ラス。
４・・・外部リード、５・・・半導体ベレット、６・・
・リードワイヤ、７・・・放熱フィン。
第 １ 図
第 ２ 図
第 ３ 図
２５９1 to 3 are longitudinal cross-sectional views of packages according to embodiments of the present invention. Explanation of the symbols 1: cap, 2: base, 3: low melting point glass. 4... External lead, 5... Semiconductor pellet, 6...
-Lead wire, 7...radiating fin. Figure 1 Figure 2 Figure 3 Figure 259
Claims (1)
たベースと、このベース上に前記半導体ペレットをおお
って重ね合されるセラミックキャップと、前記ベース及
び前記キャップの間に介在されて両者に密着することに
より前記半導体ペレットを封止するためのガラス層と、
前記ペレットを収容した内部空間から外方へ突出部よ、
１うに前・記ガ・ラス層を貫血して配置されたリードと
をそなえた半導体装置において、前記リードの外方突出
部を前記キャップ側へ折曲することを特徴とする半導体
装置。1. c! A base to which a conductor pellet is fixed to the bottom surface of the bottom plate of the J section, a ceramic cap superimposed on the base to cover the semiconductor pellet, and a ceramic cap that is interposed between the base and the cap and is in close contact with both. a glass layer for sealing the semiconductor pellet;
a portion protruding outward from the internal space containing the pellets;
1. A semiconductor device comprising: (1) a lead disposed by penetrating the glass layer, wherein an outwardly protruding portion of the lead is bent toward the cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157809A JPS5980948A (en) | 1983-08-31 | 1983-08-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157809A JPS5980948A (en) | 1983-08-31 | 1983-08-31 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP394677A Division JPS5389664A (en) | 1977-01-19 | 1977-01-19 | Package structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5980948A true JPS5980948A (en) | 1984-05-10 |
Family
ID=15657759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58157809A Pending JPS5980948A (en) | 1983-08-31 | 1983-08-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5980948A (en) |
-
1983
- 1983-08-31 JP JP58157809A patent/JPS5980948A/en active Pending
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