JPS5980962A - Manufacturing method of MIS type semiconductor device - Google Patents

Abstract

PURPOSE:To enable to obtain the titled semiconductor device having high efficiency and high degree of integration as an E/DMOSLSI or ROM of various specifications by a method wherein impurities to be used for formation of a depletion are selectively introduced in advance into the part where a depletion type MIS transitor, having semiconductor substrate surface, will be formed and subsequently, a gate electrode is formed thereon. CONSTITUTION:A field silicon oxide film 12 is formed by performing a thermal oxidization on the whole surface of the silicon wafer 11 of P type or N type conductive type, a gate silicon oxide film is formed on the silicon wafer 11, the surface of which is exposed by removing said film 12, and a region of the conductive type reverse to that of the silicon wafer is formed on the above channel regions by ion-implanting the impurites of the conductive type reverse to that of the silicon wafer 11. Then, a gate electrode pattern is formed by selectively removing the polycrystalline silicon film 14 provided on the whole surface, and after the surface of the silicon wafer 11 of the region other than the above gate electrode pattern has been exposed, the gate electrode pattern of the second silicon gate type MOS transistor is formed.

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing an MIS type semiconductor device.

For more details, see the new RQM (Read Only Memory)
The present invention relates to a method for manufacturing a highly integrated E/DM I S LSI including a circuit.

E/D equipped with a ROM circuit applied to the information processing field
MISLSI is required to have a high degree of integration in order to improve reliability, reduce costs, and operate at high speed.

Conventionally, E/Ds equipped with this type of highly integrated ROM circuit
MISLSI (hereinafter abbreviated as RQME/DMISLSI) consists of MIS type transistors Qll arranged in a matrix as shown in FIG. 1 and FIGS. 2(a) to (CIK).
~ A part of Q3m is depleted type (
QIID + Q+ap + Q12D + Qssp
) and the rest as enhancement type (QI
2E * QHE # QtsE+ Qs+E+ Qs
tz). In addition, in Figure 1,
1 to Xs are output signal wirings, and Y1 to Y3 are address wirings. This ROME/DMI SLS I is shown in Fig. 2(a) as a plan view, as shown in Fig. 2(b3) as a vertical cross-sectional view taken along arrow AA' in the same figure (al), as shown in Fig. 2(c). )
As shown in the vertical cross-sectional view taken in the direction of the arrow B B' in FIG.
It has a structure in which the N+ type layer 4 formed by the self-alignment method using this gate electrode pattern serves as a source or drain. In the same figure, N under the gate electrode
The type layer 5 is a diffusion layer in a depletion type MIS transistor, and 6 is a field silicon oxide film.

This type of RQME/DMQSLS I has the following structure:
Although the element size is kept as small as possible and the degree of integration is high, since the N+ type layer 4, which becomes the source or drain of each MIS type transistor Qll to Qss, is formed on the surface of the silicon substrate 1, the lateral Multi-bit ROME/DMI SLS with considerably larger directional element size
In order to obtain I, the chip size becomes large.

Therefore, an object of the present invention is to provide an MI device such as ROME/DMI SLS■ which has a novel structure and has an extremely small element size.
An object of the present invention is to provide a method for manufacturing an S-type semiconductor device.

In the present invention, a plurality of first Ml5 type transistors each having a gate electrode on a part of the surface of a semiconductor substrate with a first insulating film interposed therebetween are provided in a matrix at regular intervals; A gate electrode is provided on the semiconductor substrate between the second insulating layer provided on the entire surface of the electrode and the entire surface of the semiconductor substrate whose surface is exposed, and the semiconductor substrate between each of the first Ml5 type transistors with a second insulating film interposed therebetween. one second MIS type transistor is provided between each of the first MIS type transistors, a part of the first or second MIS type transistor is a depletion type, and the remaining A method for manufacturing an MIS type semiconductor device in which a depletion type MIS type transistor is to be formed on the surface of a semiconductor substrate, which selectively introduces impurities for depletion in advance into a portion of the semiconductor substrate surface where a depletion type MIS type transistor is to be formed. Then, the gate electrode is formed.

Hereinafter, ROM E/D MQS which is an embodiment of the present invention
The LSI manufacturing method will be specifically explained. RQ according to the present invention
The main features of ME/DMO8LSI are MO8LSI
MQ with extremely high integration by utilizing multilayer wiring technology in K
S-type transistors are arranged in a matrix, and an impurity of the opposite conductivity type to that of the substrate is ion-implanted into the channel region of the enhancement-type MQS-type transistor, which serves as the eye of the ROM, to transform the transistor into a depletion-type transistor. It is something that has been transformed into something.

The distance between the gate electrodes of each MO8 type transistor is made as small as possible, and the conventional ROMM of this type
It has a structure that achieves about twice the degree of integration compared to O8LSI.

Note that FIG. 3 is a schematic diagram showing a part of the RQM circuit according to the present invention, where X and -X3 are output signal wirings, and Y1 to Y
Reference numeral 6 indicates an address wiring, Q and 1 to Q36 indicate silicon gate type MO8 type transistors, the index D added thereto indicates a depletion type, and the index E indicates an enhancement type.

Now, the RQM E/DMOS L SI according to the present invention
and its manufacturing method will be explained in detail in the order of steps using drawings.

(7) A silicon wafer 11 having a conductivity type of P type or N type is prepared as a starting material, and its entire surface is thermally oxidized to form a field silicon oxide film 12 of about 1 μm. Next, the field silicon oxide film 12 is selectively removed by photoetching or the like so as to expose the surface of the silicon wafer 11 which will become the device active area (FIG. 4).

A gate silicon oxide film 13 is formed by about 1000 layers on the silicon wafer 11 whose surface is exposed (Fig. 5), and then, in order to form a depletion type MQS transistor, a film of the opposite conductivity type to that of the silicon wafer 11 is formed at that location. A region 11 of a conductivity type opposite to that of the silicon wafer 11 is formed by ion-implanting impurities into these channel regions.
form a. For example, if the silicon wafer 11 is
In the case of the MQS type transistor, ions of N-type conductivity type impurities such as phosphorus are selectively implanted into the channel region of the depletion type MQS transistor using a photoresist or the like as a mask, and the ions are removed by subsequent heat treatment. The implanted impurity is diffused into the silicon wafer 11 to form an N-type layer 11a. When using an N-type conductivity type silicon wafer 11, a P-type conductivity type impurity such as boron may be used as the impurity to be ion-implanted to form the P-type layer 11a. This depletion type MO8 type transistor QI2DIQ14D
+ Qtso e Qstp + Q35D Yu, FLO
This is M's eye. Furthermore, a conductive polycrystalline silicon film 14 having a thickness of 3500 to 5000 Å is formed on the entire surface by CVD or the like (FIG. 6). The broken line shown in FIG. 6(a)K indicates the boundary between the field silicon oxide film 12 and the gate silicon oxide film 13.

(a) Selectively remove the polycrystalline silicon film 14 to form a gate electrode pattern, use this as a mask to remove unnecessary portions of the gate silicon oxide film 13, and expose the surface of the silicon wafer 11 at that location (FIG. 7) . The polycrystalline silicon film 14 of this gate electrode pattern and the gate oxide silicon 13° silicon wafer 11 underneath can constitute a large number of first silicon gate type MO8 type transistors, and these transistors are arranged in rows and columns at regular intervals. shall be arranged in the form of

(1) Next, a silicon oxide film 15 of about 100 OA is formed over the entire surface in order to provide a silicon gate type MO8 transistor between the first MO8O8 tetransistors 2 (FIG. 8). This silicon oxide film 15 becomes the gate silicon oxide film of the second silicon gate type MO8 type transistor, and also serves to electrically insulate the first and second transistors. In addition, in order to make the characteristics of the first and second transistors the same, the gate silicon oxide film 13 is formed to have the same film properties and thickness as the gate silicon oxide film 13 in the first transistor, and the first and second transistors are sufficiently electrically connected. Select the required film thickness. Note that the two-dot chain line in the figure indicates the boundary line of the polycrystalline silicon film 13.

2) A conductive polycrystalline silicon film 16 of 3500 to 5000 A is formed on the entire surface by CVD or the like, and a gate electrode pattern for the second silicon gate MO8 transistor is formed by etching or the like (FIG. 9). . Note that FIG. 10 shows indices in the jRQM circuit configuration shown in FIG. 3.

Note that the channel region in the depletion type MO8O8 type transistor, which is the eye of this ROM, is formed by selectively implanting impurity ions into the silicon wafer 11 in the (supporting) process (FIGS. 4 to 6). This is what has been done.

(9) Next, although not shown, the entire surface is coated with a phosphosilicate glass film as a passivation film.

As mentioned above, RQME/DM□5L according to the present invention
SI uses a silicon wafer 11 as a starting material and uses a conductive polycrystalline silicon film thereon to form first and second silicon gate MO8 type transistors Q+I- by a two-layer wiring method. Since Qse is formed in a matrix, it has an extremely high degree of integration with a simple manufacturing process. For example, if the line width that can be formed by current photoetching is 8 μm,
The first and second MOs have an active region of 8 μm width.
8O8 type resistor can be formed using conventional source.

In ROME/DMO3LSI having a drain diffusion layer, each element active region has a width of about 16 μm or more, so the IC chip area can be more than twice as small.

The present invention is a silicon-gauge type M with extremely small element dimensions.
O8 type transistors are arranged in a matrix with the distance between them as small as possible, and any of these transistors can be configured as an enhancement type or a depletion type, so it can be used as a ROM. Or E/DMOS L S with various specifications
Various types of MIS type semiconductor devices can be obtained by using I with high performance and high degree of integration.

Note that the RQME/DM□5LS according to the present invention described above
During the manufacturing process of I, an insulating film (silicon oxide film, etc.) is used as a mask for selective etching when forming the polycrystalline silicon film 14 into a gate electrode pattern, and it is left as is in subsequent steps. , the thickness of the insulating film on the polycrystalline silicon film 14 as a gate electrode pattern (the superimposition of the insulating film as a mask and the newly formed silicon oxide film 15) increases, and the thickness of the first and second transistors increases. The parasitic capacitance between the two can be reduced. As described above, the MIS type semiconductor device according to the present invention is not limited to the above-mentioned embodiments, and can be applied to various embodiments.

[Brief explanation of drawings]

Figures 1 and 2 (a) to (c) show conventional RQME/
A circuit diagram of DMQSLSI, a plan view and a vertical cross-sectional view showing its structure, and FIG.
The circuit diagrams of a part of ME/DM□SLS I, FIGS. 4(a) to (C) to FIGS. FIG. 2 is a plan view and a vertical cross-sectional view showing the manufacturing method in the order of steps. 1.11... silicon wafer, 2,13.15...
・Gate silicon oxide film, 3.14.16... Polycrystalline silicon film for gate electrode, 4... N+ type layer, 5...
N-type layer, 6, 12... field silicon oxide film, 1
1a...A region of a conductivity type opposite to that of the silicon wafer 11. Figure 1 Figure 2 (a-), -〇°9 Figure 4 (0-) (A) Figure 5 (C) (C) -1 Figure 6 (of) B, (C) (b) Figure 7 (mi) (C) (b) Figure 8 C system (c> October Figure 9 (a-) (C) (b) 1st ( (a-) (b) //f7-

Claims (1)

[Claims] 1. A first conductor layer formed to extend across the element active region set on the surface of the semiconductor substrate with an insulating film interposed therebetween; and a second conductor layer formed on the bare hand active region so as to overlap at least a portion of the first conductor layer.
an MIS type transistor connected in series by at least a conductor layer and each of the first and second conductor layers on the element active region serving as a gate electrode of an MIS type transistor;
The MIS forming an S-type transistor and connected in series
A part of the type transistor is depletion type, Y type, and the rest is enhancement type.
A method for manufacturing an IS type semiconductor device, comprising introducing impurities into a selected portion of a surface of a device active region to make it a diploid type, and then forming the first and second conductive layers. Characteristic manufacturing method of MIS type semiconductor device.