JPS59814A - Ac switch circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AC switch circuit interposed between an AC power source and a load to prevent arcing between contacts that open and close.

In the prior art, depending on the timing at which the level of the input signal for turning the load on and off changes, there is a possibility that the output of the off-time detection circuit and the on-time detection circuit will match the input signal twice. Therefore, there was a risk of malfunction.

The purpose of this invention is to provide an AC switch circuit that solves all of the above-mentioned technical problems and prevents malfunctions.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is an electrical circuit diagram of an embodiment of the present invention.

An AC power supply 1 and a load 2 are connected in series through terminals 3 and 4 in the AC switch circuit of the present invention. A diode 5 and a first relay switch 6 connected in series with the diode 5 are connected between the lines 13 and 14 connected to the terminals 3 and 4.
A series circuit consisting of and is connected. This series circuit has
A second relay switch 7 is connected in parallel. Further, a third relay switch 8 is connected in parallel to the diode 5.

1st relay switch 6V'i, 1st latching relay I
This is related to the UK. This first latching relay 10fl is a so-called single-winding latching relay,
゛It has a relay coil 52. When the relay coil 52 is temporarily excited in the direction of the arrow 57, the first relay switch 6ri is brought into conduction, and the current condition is mechanically maintained. The twisted relay coil 52 temporarily moves to the opposite arrow 5.
When excited in the direction 8, the first relay switch 6 becomes OFF state and maintains the OFF state by itself.

In order to drive the relay coil 52 of the first latching relay 10, an eleventh J relay drive circuit 61 is provided. In this first relay drive circuit 61, a transistor TR1 and a transistor TR, which serve as semiconductor switching elements.
2 are connected in series, so n.

53 connection points of 1 latching relay lO1 are connected to one terminal of relay coil 52. transistor TR
3 and transistor TR4 are connected in series nl, and their connection point 54 is connected to the other terminal of relay coil 52.

Zener diodes 59 and 60 are connected in series in opposite directions to the connection points 53 and 54 to prevent back electromotive force and gravity of the relay coil 52.

The output of AND gate G3 is an inverting transistor TR5.
as well as the aforementioned transistor'
1' Given to the base of R4. transistor TR5
The collector of the transistor TR1 is connected to the base of the transistor TR1. Output of AND gate G4, transistor 'rR6
With the base of the transistor TR
Based on the base of 2, t et al. The collector of transistor TR6 is connected to the base of transistor TR3.

When the output of AND gate G3 becomes high level, transistors TR4 and TR5 become conductive, and transistor TRI becomes conductive. The output of AND gate G4 is at a low level, so transistors TR2 and TR6 are cut off. Therefore, transistor TR3 is cut off. In this way, transistor TR1, connection point 53, and relay coil 5
2. A current path is formed through the connection point 54 and the transistor TR4, and a current flows through the relay coil 52 between the arrows 57. Therefore, the first relay switch 6 becomes conductive and self-maintained.

When the output from G4 becomes high level, transistors TR2 and TR6 become conductive and transistor TR3 becomes conductive. AND game) The output of G3 is
It is at a low level, transistors TR4 and TR5 are cut off, and transistor TRI is cut off. In this way, a current path is formed that passes through the transistor TR3, the connection point 54, the relay coil 52, the connection point 53, and the transistor TR2. -I can do it. At this time, the first relay switch 6 is cut off and self-maintained.

The second latching relay 11 associated with the second relay switch 7 is also a single-winding latching relay like the first latching relay 10, and the @2 relay drive circuit 63 for U*Jing the relay coil 62 is provided. The second relay drive circuit 63 is configured in the same manner as the first relay drive circuit 61, and includes transistors TR7 to TR12 and a Zener diode (1), and a transistor TR
IL).

The output of the AND gate G5 is applied to the base of TR11, and the output of the fdAND gate G6 is applied to the bases of transistors TR8 and TR12.

When the output of AND gate 65 reaches a high level, transistors TRl0. TRII goes through the fence, transistor TR
711- is conducted. The output of AND gate G6 is at a low level, so transistor 71'R8, TR
12 is blocking it. Therefore, transistor TR9 is cut off. Thus transistor TR7, connection point 6
4, relay coil 62, connection point 65 and transistor TR1 (1-A current path is formed through n, relay coil 6
2Vc current flows in the direction of arrow 66. Therefore, the second
Relay switch 7 becomes conductive and self-maintained.

When the output from AND gate 1-G6 becomes high level, transistors I''R8 and TR12 are connected, and transistor TR9 becomes conductive.The output of AND gate G5 is low level, and transistor TR10 becomes conductive.
．． TRII is cut off and transistor TR7 is cut off. Thus, transistor 'rR9, connection point 65, relay coil 62, connection point 64 and transistor TR8
′-current path form through! 67 times of the excitation current flows in the relay coil 62 in the opposite direction to the above. This causes the second relay switch 7 to shut off and become self-holding.

The third latching relay 12 associated with the third relay switch 8 is also connected to the first and '%2 latching relays 10.11.
! : Similarly, it is a single-winding latching relay, and a third relay drive circuit 71 for driving the relay coil 70.
is provided. This third relay drive circuit 71 is configured similarly to the first and second relay drive circuits 61 and 62, and includes transistors TR13 to TR18 and a Zener diode 7.
2,73. The bases of the transistors TR16 and TR17 are supplied with the output of the AND gate G7, and the bases of the transistors TR14 and TR18 are supplied with the output of the AND gate G8.

When the output of ANIJ gate G7 becomes high level, transistors TR16 and 'rR17 become conductive, and transistor TR13 becomes conductive. AND game) The output of G8 is low level, so the transistors TR14 and TR1
8 is blocking it. Therefore, transistor TR15 is cut off. In this way, transistor TR13, connection point 7
4. A current path passing through the relay coil 70, the connection point 75, and the transistor TRl6 is formed, and the relay coil 70
Current flows in the direction of arrow 76. Therefore, the third relay switch 8 becomes conductive and self-maintains.

When the output from AND gate G8 becomes high level, transistors TR14 and TR18 become conductive, and transistor TR15 becomes conductive. The output of AND gate G7 is low level, and transistors TR16 and TRL7
is cut off, and transistor TR13 is cut off. In this way, a current path passing through the transistor TR15, the connection point 75, the relay coil 70, the connection point 74, and the transistor 1'R14 is formed, and a current flows in the relay coil 70 in the direction of the arrow 77, which is the opposite direction to the above. . The third relay switch 8 is cut off and self-maintained by this flVC.

When the current flowing through the relay coil 52, 62.70 is interrupted, a voltage exceeding the supply voltage Vcct is generated in the relay coil 52, 62.70, and the transistor TRl-T
R18' (f-zener diode to avoid destruction)? 5
9, 60, 68, 69, 72.73 are provided t'L stones.

A supply voltage VCC is applied to each terminal 100K. Here Zenadio F59, 60.68, 69, 72.73
The pre-emptive voltage is a value exceeding the voltage of the supply voltage Vcc and a value below the voltage at which the transistors TR1 to TR18 are destroyed.

AND game) When the output of 63 to G8 changes from high level to low level, relay coil 52.112
, 70, a μ back electromotive force is generated. At this time, the relay coil 52 → connection point 53 → Zener guide A-de 59 → Zener diode 60 → connection point 54 → relay coil 52, relay
Coil 62 → Connection point 64 → Zener diode A-Dro 8 → Tsuner diode 69 → Connection point 65 → Relay coil 62, relay coil 70 → Connection point 74 → Zener diode I! 72
→ Zenaguio F73 → Connection point 75 → Relay coil 7
0, or vice versa, and the Zener diode 59I60I68, 69, 72°73 breaks down. Zener diode 59.60.6g, 69,
The back electromotive force is absorbed by the breakdown of 72 and 73, and therefore the transistors 'rR1~TR1
8 will never be destroyed.

At the off-time detection circuit 16Vc, the second relay switch 7
A series circuit including the resistor 17 and the primary winding 18a of the transformer 18 is connected in parallel. A capacitor 19 and diodes 20 and 21 are connected in parallel with the secondary winding 18bVc of the transformer 18.

Note that the diodes 20 and 21 are connected to each other in the reverse direction Ilc. Capacitor 19 and diode 2U, 21
'& the output of the transformer 18 via the rectangular wave shaping circuit 22
is input. The positive rectangular pulse output from the rectangular wave shaping circuit 22 is derived every positive or negative half period as an off-state detection output. This OFF detection pulse ID,
The rising edge differential circuit 24 is provided with an AND gate G9 and an inversion circuit 23. This rising differential circuit 24
The output from the line l! is passed through the delay circuit DLI to the line l! It is given to l.

A current transformer 25 is provided on the line 13Vc between the terminal 3 and the connection point of the first relay switch 6. This current transformer 25
The output of the on-state detection circuit 26Vc is inputted to the on-state detection circuit 26Vc. The on-state detection circuit 26, like the off-state detection circuit 16 described above,
It includes a capacitor 27, diodes 28, 29 and a square wave shaping circuit 30.

The positive pulse from the OFF detection circuit 26 is an AND data)
Rising differential circuit 3 consisting of GIU and inversion circuit 31
2 and the volatilization circuit DL2, it is output as an on-state detection output every half cycle of a positive or negative force.

Line/l,! ! The signal via the control circuit 33v
It is applied to one input of the AND gates G1 and G2, which are provided with a gate c. Also, input K[ of each capability of AND gate) Gl, G2, AND gate G15... of the signal control circuit 34. G16
inputs are given individually.

OR gate GIIK is connected to the output of AND gates Gl and G2. given) 1. Ru. The output of this OR gate Gll is given to a monostable circuit 35Vc (JR
Game) Monostable circuit 361C4 gill fL via G14'
Ru.

Output of monostable circuit 35 ri A N D gate G3. G
8VC is applied, and AN via the inverting circuit 48.
I) Gate G4. G7 and differential rotation l@37 are given. This differentiating circuit 37 consists of an inverting circuit 38 and an ANI) gate Gl2. The output of the differentiating circuit 37 is applied to an OR gate G14Vc and also to a monostable circuit 39. The output of the monostable circuit 39 is an AND gate G
5, G 6Vc (n6 is given, and inverting circuit 4UVc is given.The output of this inverting circuit 40 is given to OR game via inverting circuit 41 and a differentiating circuit 42 contained in AND gate Gl3) G14Vc is given. . Further, the output of the inverting circuit 40 is AND gate 1-G4. G7vc
each is given. The output of the monostable circuit 36 is AND
Game 1-G3, G4. G5, G6, G7. G8v
C is given n each.

The signal control circuit 1@34Vcij is connected to an ON operation signal or an input terminal 43 for inputting an ON operation signal.

The signal from this input terminal 43 is applied to AND gate G3. G
5. G7, one input of the NOR gate G19, the inverting circuit 44, and the AND gate) G15. It is given to the manpower of one side of G18. The output of the inverting circuit 44 is given to the other input of the NOR gate G19 and the other input of the AND gate G1g at t'L, and is also given to the AND gate G8, and further to one input of the AND gate G16. Given. NO
The outputs of R gate G19 and AND gate 018 are OR
AND gate G15. They are respectively given to the other input of G16. Further ICAND gate 6
The output of 15 is given to HAND gate GIK, and the output of AND game) G16 (i') is given to AND gate) G2. Note that the AND gate 618 and the inverting circuit 44 are configured as a rising differentiation circuit 461. Also NOR game) Gl
9 and the inversion circuit 44 constitute a falling differentiation circuit 47.

The operation will be explained with reference to FIG. AC power having a voltage waveform shown in FIG. 2 111 is supplied from an AC power source 1 toward the terminal 3. When the first, second and third relay switches 6.7.8 are in the cutoff state, the transformer 18
An induced voltage is generated in the secondary winding 18b at each cycle of the voltage waveform, and due to the action of the diodes 20 and 21, the
), a waveform signal in which a voltage equal to or more than the inter-write voltage drop F has been cut is applied to the rectangular wave shaping circuit 22. An off-time detection signal having a waveform shown in FIG. 2(3) is derived from the rectangular wave shaping circuit 22. Since the output of the transformer 18 has a leading phase with respect to the load power supply, this off-state detection signal has a leading phase as well. Therefore, a positive tarok pulse is generated by the rising differentiation circuit 24 in response to the rise of the off-time detection signal gI; as shown in FIG. 2 (4), and furthermore, as shown in FIG. only to be delayed.

Thereby, a tarok pulse synchronized with the positive phase of the voltage waveform is obtained. From now on, this clock pulse will be referred to as a clock pulse. In addition, the rising differential circuit 24Vc
Alternatively, logical means may be used. The on-pulse H
In this state, the signal iL applied to the input terminal 43 changes from low level to high level at time t1 as shown in FIG. 2 (6). ``.Synchronizing with the rising edge of such an input signal, the rising differential circuit 46 outputs the second signal.
Tarock pulses as shown in Figure (7) are derived fl, O
R game) Monostable circuit 45Vc is applied via G17. In response to the input of this tarok pulse, the monostable circuit 45 outputs a pulse having a pulse width w4 as shown in FIG. 2(8).

This pulse width W4 is selected to a value corresponding to one cycle of the load power supply. This pulse with pulse width W4 also occurs when the input signal changes from high level to low level, so by ANDing it with the input signal in AND game G15,
As shown in FIG. 2 (9), a pulse with a pulse width W4 is
D game) Gl (7) Give to the input of Q game. Therefore, A
From the ND gate Gl, as shown in FIG. 2 (10),
A clock pulse corresponding to the on pulse is output. Moreover, since the pulse width W4 is selected corresponding to one cycle of the AC power supply, the clock pulse is output only once, thereby preventing pre-operation.

ANDG) Tarock pulse from Gl is monostable circuit 3
5 and also to the monostable circuit 36 via the VCOR gate G14. In the monostable circuit 35, the clock pulse input VcJ5 outputs a pulse II@Wl as shown in FIG. This value corresponds to the time from when the first relay switch 6 becomes conductive until when the second relay switch 7 becomes conductive.

The output of the monostable circuit 35 is applied to AND gates G3 and G8, and is inverted by an inverting circuit 48 as shown in FIG. is given to VcfI
The differential circuit 37 outputs a positive clock pulse in synchronization with the rise of the inverted signal. Note that logic means may be used in place of the differentiating circuit 37Vc. The clock pulse of the above voltage is applied to the monostable circuit 36Vc via the OR gate G14i, and is also applied to the monostable circuit 39. A pulse with width W3 is derived. This pulse width W3f'i is selected to be a value corresponding to approximately half a cycle of the AC power supply, and this value corresponds to the time from when the second relay switch 7 becomes conductive to when the third relay switch 8 becomes conductive.

The output of the monostable circuit 39 is the AND gate G5゜G6Vc
is input to AND gate G4, differentiation circuit 42 and AND gate G7Vc-! via inverting circuit 4o.
8g - seen. A positive tarok pulse is derived from the differentiating circuit 42 in response to the rise of the output of the inversion circuit 40, that is, the fall of the monostable circuit 39, and the positive clock pulse is applied to the 1dOR gate G14. Therefore, the OR gate G14 receives the tarok pulse from the OR gate Gll shown in FIG. 2 11UI, and the monostable circuit 3.
Tarock pulse synchronized with the rising edge of the pulse from 5,
A periodic tarok pulse is applied to the rise of the pulse from the monostable circuit 39, and clock pulses corresponding to three time series are applied to the monostable circuit 36. As a result, the monostable times W! 36 outputs three pulses having a pulse width W2 corresponding to each time series as shown in FIG. 2 (141). 6
．． The operating time has been selected to exceed 7.8, and the W
l) W2 and W3) W21C selected n.

This funeral stabilization circuit 36.7) Output HAND gate G 3~
G 5VC-tn-zon is given.

AND gates 63-G8 select the output of monostable circuit 36 into on/off signals for each relay switch 6-8.

First, regarding the first relay switch 6Vc,
G3Vc is supplied with the input signal from the input terminal 43, the output of the monostable circuit 35, and the output of the monostable circuit 36. Therefore, as shown in FIG. 2 (16), the output of the AND gate G3 is at a high level only during the time when the output of the monostable circuit 36 is at a high level. Also AND game) G4
Since the output of the monostable circuit 35 is inverted by the inverting circuit 36, it is at a low level. Therefore, as mentioned above, the first relay drive circuit 61 is connected to the AND gate).
As the output of G3 becomes high level, a current flows through relay coil 52Vc#- in the direction of arrow 57, and first relay switch 6 becomes conductive and is self-maintained. Moreover, the first
The relay switch 6 becomes conductive when the diode 5 becomes reverse biased as shown in FIG. 2 121.
That is, when the AC power source is in the negative phase.

Regarding the second relay switch 7, the output of the AND gate G5 becomes 71-level when the output of the monostable circuit 36 becomes high level for the second time, as shown in FIG. 2, 121c.
Correspondingly, a current flows through the relay coil 62 in the direction of the arrow 66, and the second relay switch 7 is made conductive and self-maintained. Furthermore, the second relay switch 7 becomes conductive when the diode 5 becomes forward biased, as shown in FIG. 2 (19), that is, when the AC power supply becomes in the positive phase.

Regarding the third relay switch 8, the output of the AND gate G7 becomes high level when the output of the monostable circuit 36 becomes high level for the third time, as shown in FIG. A current flows through the relay coil 70 in the direction of the arrow 76, and the third relay switch 8 is made conductive and self-maintained. Moreover, the third relay switch 8 becomes conductive when the diode 5 is biased in the reverse direction, that is, when the AC power supply is in the negative phase, as shown in FIG.

In this way, when power is applied, VCid, first relay switch 6, second relay switch 7, and third relay switch 8 are turned on in this order. Furthermore, since the first and third relay switches 6.8 conduct in the negative phase of the AC power supply, and the second relay switch 7Vi conducts in the positive phase of the AC power supply, power energization in an arc-free state is achieved. In response to the above-described power activation, a load current as shown in FIG. 2 (121) flows. The portion shown by diagonal lines in FIG. 2 121 flows to the diode 5. This load current does not flow through the primary winding 18aicfffin of the transformer 18, so no electromotive force is generated through the secondary winding 18bVc. The output generated by the current transformer 25Vc is transferred to the diode F28.29&? as shown in FIG. :Therefore, the signal is cut by the forward voltage drop and input to the rectangular wave shaping circuit 30. In response to the rising edge VC of the waveform shown in FIG. 2 +231 outputted from the rectangular wave shaping circuit 30, a clock pulse shown in FIG. The tarok pulse delayed by the time T2 is output on the line I! as shown in FIG. 2 (25). 2V
c is output. In this way, a tarlock pulse (referred to as an off pulse) synchronized with the positive phase of the load current is applied from line 12 to one input of AND gate G2.

Assume that the input signal to the input terminal 43 changes from a high level to a low level at time t2 on such a floor.

In response to this change in the input signal, a positive clock pulse is applied from the falling differentiation circuit 47 to the monostable circuit 45 as shown in FIG. A positive pulse causes AND gate G15, G161C4 gill f'L as shown in FIG. 2 (8). AN
Since the output inverted by the D gate G16V'cvi inversion circuit 44 is given, &'' is output from the AND gate G16.
i Fig. 2 (The pulse shown at 261 is the AND gate G2Vc
Given. Therefore, from the AND gate G2, as shown by θ in FIG. , G14 to provide a monostable circuit 36Vc. Therefore, from the monostable circuit 35, as shown in FIG.
The pulse of pulse [Wl is outputted as shown in Figure 2, and is inverted as shown in Figure 2, and the AND gate G4. It is applied to G7 and also to the rising differential circuit 37. Positive tarokku pulse HO from rising differential circuit 37
Provided to R gate G14 and monostable circuit 39V
c given. Therefore, from the monostable circuit 36, three pulses of 1% W2 corresponding to the three time series are outputted from the monostable circuit 36 as shown in FIG. It is given to gates 63-GB.

First, the third relay switch 81C1lJ is connected to the AND gate G8, and the signal from the input terminal 43 is connected to the inverting circuit 44.
The signal inverted by the output of the monostable circuit 35 and the monostable circuit #! The output of I36 is given.

Therefore, as shown in FIG.
The output becomes high level in response to the first pulse from the monostable circuit 36, and the output of the third relay 1 becomes high level in response to the first pulse from the monostable circuit 36.
A VC current flows through relay coil 70 in pivot circuit 71 in the direction of arrow 77 . Therefore, the third relay switch 8
Or block it. Moreover, as shown in FIG. 2B (2), the third relay switch 8V'i is cut off when the diode 5 is in the cutoff state, that is, when the load current is in the negative phase.

Regarding the second relay switch 7, the AND gate 66 receives the input signal inverted by the inverting circuit 44, and the input signal inverted by the monostable circuit 39.
and the output of the monostable circuit 36 are given.

Therefore, as shown in FIG. 2, the output of the AND gate (G6) suddenly goes to a high level in response to the second pulse from the monostable circuit 36, and the second relay drive circuit 63 responds to t'L, VC. One current flows through the relay coil 62 in the direction of the arrow 67. Therefore, the second relay switch 7 is cut off. Moreover, the second relay switch 7 has α9 shown in FIG.
), when the diode 5 is conductive, that is, when the load voltage is in the positive phase, it is cut off.

Furthermore, regarding the @1 relay switch 6Vc, the output of the inverting circuit 36, the output of the inverting circuit 40, the output of the inverting circuit 44, and the output of the monostable circuit 36 are applied to the AND game G4. Therefore, the output of G4 (AND game) is
As shown at t(f) in FIG. 2, the monostable circuit 360 becomes high level in response to the third pulse, and due to t'L, VC, the relay coil 5 in the 11th J relay circuit 61
2, a current flows in the direction of arrow 58. Therefore, the first relay switch 6 is cut off. In addition, the first relay switch 6e has a diode 5 as shown in Fig. 2 (181).
When is in the cutoff state, that is, when the load current is in the negative phase, VC is cut off.

In this way, when the power is turned off, the VC is cut off around 1 of the third relay switch 8, the second relay switch 7, and the first relay switch 6. Moreover, since the first and third relay switches 6j8 are cut off at the negative phase of the load current, and the second relay switch 7 is cut off at the positive phase of the load current, power extinction is achieved in an arc-free state.

Once power de-energization is achieved, the current transformer 25VcVi output force will be generated at the output of the transformer 18.

As described above, according to the present invention, the input signal is inputted to the input signal 9 through the signal control circuit which derives a pulse corresponding to one cycle of the AC power supply according to the rising or falling edge of the input signal.
Since it is applied to η1 and the second gate, malfunctions are prevented from occurring.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the production of Vi. DESCRIPTION OF SYMBOLS 1... AC power supply, 2... Negative, 5... Diode, 6... First relay switch, 7... Second relay switch, 16... OFF detection circuit, 26...・ON detection circuit, 34...Signal control circuit, 43...Input terminal agent Patent attorney Kei Nishi

Claims (1)

[Claims] A series circuit consisting of a first relay switch and a diode, and a second relay switch are connected in parallel to a series circuit of an AC power source and a load, and when the power is energized, the voltage waveform of the AC power source is the opposite of that of the diode. The first relay switch is turned on during the half period in the forward direction of the diode, and the second relay switch is turned on after a delay during the half period in the forward direction of the diode, and when the power is turned off, the voltage waveform is In an AC switch circuit in which the relay switch is cut off and the first relay switch is cut off during the half cycle in the opposite direction of the diode by M, the AC' @ source and load when the second relay switch is off in NfJ No. 11 It has an off-time detection circuit that detects electrical changes in the series circuit and outputs a rectangular wave every positive or negative half cycle, and turns on the output and load of this off-time detection circuit every half cycle. (first gate that outputs based on coincidence with the input signal) f, y7 absent, this gate output is
Control G1 of the first relay drive 11 circuit is necessary to turn on the relay switch when the reverse voltage of the diode is applied, and furthermore, after the first relay switch is turned on, the order of the diode is A control signal with a second relay drive circuit necessary to turn on the second relay switch when the directional voltage is applied, and then a control signal between the AC power supply and the load when the eleventh second relay switch is turned on. The on-time detection circuit detects the electrical change in the series circuit and outputs it every positive or negative half cycle.The on-time detection circuit's output every half cycle and the input signal that turns on the load are A second gate outputs an output when the forward pressure of the diode is reached, and this gate output is a control signal for the second relay drive circuit necessary to turn off the second relay switch when the forward pressure of the diode is high. and further, after this second relay switch has turned off and when the reverse voltage of the diode is present, the control signal for the first relay drive circuit that is necessary to turn off the relay switch @1, and the above-mentioned A pulse corresponding to one cycle of the AC power supply is derived from the input signal according to its rise or fall (characterized by being given to the first and second gates of gIJ through the control circuit a) AC switch circuit.