JPS598361A - Package of semiconductor integrated circuit device - Google Patents

Package of semiconductor integrated circuit device

Info

Publication number
JPS598361A
JPS598361A JP57117516A JP11751682A JPS598361A JP S598361 A JPS598361 A JP S598361A JP 57117516 A JP57117516 A JP 57117516A JP 11751682 A JP11751682 A JP 11751682A JP S598361 A JPS598361 A JP S598361A
Authority
JP
Japan
Prior art keywords
package
container
bump
lead
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57117516A
Other languages
Japanese (ja)
Inventor
Makoto Harigaya
針ケ谷　誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57117516A priority Critical patent/JPS598361A/en
Publication of JPS598361A publication Critical patent/JPS598361A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize multi-pin element without increasing the size of package and simultaneously reduce wiring resistance and wiring capacitance by providing the bump for external elecrode to both upper and lower surfaces of package. CONSTITUTION:A bump 2 for external lead is extracted to both upper and lower surfaces of package directly from the region 4 used as the internal lead pattern. The external lead bump can be extracted from desired position, other than the island, cap, and bonding stitch. Thereby, the internal lead 3 can be shortened and wiring resistance and wiring capacitance can also be reduced. Since the external lead bumps 2, 5 are provided in both sides, a number of pins can be increased up to two times under the same area as compared with the conventional plug-in type package or up to several times as compared with DIP and flat package.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置の容器に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a container for a semiconductor integrated circuit device.

通常、半導体集積回路装置は容器に入れて使用する場合
が多い。従来この場合の容器外部へのリードの引き出し
方法は容器内部にパターンを形成し、パターンとチップ
をボンティング線にて接続し外部リード１を容器端面（
第１図）、又は容器下面（第２図）よシ引き出していた
。Generally, semiconductor integrated circuit devices are often used in containers. Conventionally, the method of leading out the leads to the outside of the container in this case is to form a pattern inside the container, connect the pattern and the chip with a bonding wire, and connect the external lead 1 to the end surface of the container (
(Fig. 1) or from the bottom of the container (Fig. 2).

近年、半導体集積回路の集積度の向−ヒとともに外部ビ
ン数も増加する傾向にあシ、ＶＬＳＩ　の開発によシ数
百ピンというビン数が必要となυつつある。従来の方法
ではビン数が増加すると容器が大型化し、ＬＳＩ化の長
所である小型化に反する。In recent years, as the degree of integration of semiconductor integrated circuits has increased, the number of external pins has also increased, and the number of pins in the hundreds of pins is becoming necessary for the development of VLSI. In the conventional method, as the number of bottles increases, the container becomes larger, which goes against the advantage of miniaturization, which is an advantage of LSI.

また、容器が大型化することによシチッグから外部リー
ドまでの距離が増大し配線抵抗、配線容量の増加という
欠点が生じる。Furthermore, as the container becomes larger, the distance from the lead to the external lead increases, resulting in an increase in wiring resistance and wiring capacitance.

本発明は容器の上下両面に外部電極用のバンプを有する
ことにより容器を大型化することなく多ピン化を可能と
し、同時に配線抵抗、配線容量の減少を可能にする半導
体集積回路装置の容器を提供するものである。The present invention provides a container for a semiconductor integrated circuit device, which has bumps for external electrodes on both the upper and lower surfaces of the container, thereby making it possible to increase the number of pins without increasing the size of the container, and at the same time reducing wiring resistance and wiring capacitance. This is what we provide.

本発明の半導体集積回路装置の容器はたとえば第３図に
示すように、任意の位置にて容器の上下両面より、内部
リード３に接続ぜる上面バンプ２および下面バンプ５を
肩している。As shown in FIG. 3, for example, the container for the semiconductor integrated circuit device of the present invention has upper bumps 2 and lower bumps 5 connected to internal leads 3 shouldered from both upper and lower surfaces of the container at arbitrary positions.

第４図に従来の容器の例、第５図に本発明品を示す。FIG. 4 shows an example of a conventional container, and FIG. 5 shows the product of the present invention.

本発明は従来容器の内部リードパターンとして使用され
ている領域４から直に外部リード用バンプ２を容器上面
および下面に引き出すものである。In the present invention, the external lead bumps 2 are directly drawn out from the area 4 conventionally used as the internal lead pattern of the container to the top and bottom surfaces of the container.

外部リード用バンプの位置はアイランド、キャップ、ポ
ンディングステッチ以外であれば任意の位置で引き出し
可能である。このため内部リード３を短くし、配線抵抗
、配線容量を減少させることが可能である。両面に外部
リード用バンプ２，５を有するため従来のプラグインタ
イブに比べ同面積で約２倍、ＤＩＰ、フラットパッケー
ジに比べ数倍程度までビン数を増加させることが可能で
ある。The external lead bump can be pulled out at any position other than the island, cap, or pounding stitch. Therefore, it is possible to shorten the internal leads 3 and reduce wiring resistance and wiring capacitance. Since it has bumps 2 and 5 for external leads on both sides, it is possible to increase the number of bins by about twice as much in the same area as a conventional plug-in type and several times as compared to a DIP or flat package.

次に、本発明をセラミック容器に適用した場合の実施例
について説明する。Next, an example in which the present invention is applied to a ceramic container will be described.

従来のセラミック製の半導体容器は半導体チップを載置
する第１層、内部リードパターンを有する第２層、金属
蓋板を接合する為の第３１−ヲシート状態で組立て、こ
れを焼結して完成する。このようにして製造された容器
の断面図を第６図に示す。６は第１層目セラミックス、
７は第２層目セラミックス、８は第３層目セラミックス
、３は内部リードパターン、ｌは外部リードである。A conventional ceramic semiconductor container is assembled by assembling a first layer on which a semiconductor chip is placed, a second layer having an internal lead pattern, and a 31st layer for joining a metal lid plate, and then sintering these sheets to complete the process. do. A sectional view of the container manufactured in this manner is shown in FIG. 6 is the first layer ceramics,
7 is a second layer of ceramics, 8 is a third layer of ceramics, 3 is an internal lead pattern, and l is an external lead.

これに対し本発明を適用した場合のセラミック製の半導
体集積回路装置の容器は第７図〜第９図に示すようにな
シ以下に説明する。On the other hand, a container for a ceramic semiconductor integrated circuit device to which the present invention is applied will be described below as shown in FIGS. 7 to 9.

第１層目セラミックス６に下面に引き出したい任意の位
置にスルホール９をおける（第７図）。A through hole 9 can be placed in the first layer ceramic 6 at any position desired to be drawn out to the bottom surface (FIG. 7).

第２Ｎ目セラミツクス６に内部パターン３を形成し下面
に引き出しだいパターンの先端に第１１−目スルホール
９と同位置になるようにスルホールをあけ、組合せてＦ
面にバンプ２を形成する（第８図）。第３＃目セラミツ
ク８も同様にリードを引き出したい任意の位置にスルホ
ールをあけ第２層のパターンとあわぜバンプ５を形成す
る（第９図）。An internal pattern 3 is formed on the second N-th ceramic 6, and a through hole is drilled at the tip of the pattern on the bottom surface so that it is in the same position as the 11th through hole 9, and the F is assembled.
Bumps 2 are formed on the surface (FIG. 8). Similarly, in the third #3 ceramic 8, a through hole is made at an arbitrary position where a lead is to be drawn out, and a bump 5 is formed in the pattern of the second layer (FIG. 9).

以上のようにしてバンプを両面に形成すれば従来のリー
ド引き出し方法よシチップから端子までの距離が短くで
き、かつ両面にバンクを形成するため端子数を増加さぜ
ることが可能である。By forming bumps on both sides as described above, the distance from the chip to the terminal can be shortened compared to the conventional lead extraction method, and since banks are formed on both sides, the number of terminals can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第２図は従来の外部リード引き出し例を示す図
である。 第３図は本発明の実施例の断面図、第６図は従来技術に
よる容器の平断面図、第４図は第６図の平面を縮小して
示した平面図で必シ、第５図は年３図の平面を縮小して
示した平面図である。第７図乃至第９図は本発明をセラ
ミックに適用［７た実施例の製造工程を示す図であシ、
第７図は第ＩＮ４目セラミツクスにスルーホールをあけ
た平面図、第８図は第１鳩目セラミツクスと第２層目セ
ラミックスを組み合せバンクを形成した平面図、第９図
は完成品の断面図である。 尚、図において、ｌ・・・・・・外部リード、２・・・
・・・上面バンプ、３・・・・・・内部リードパターン
、４・・・・・・内部リードパターン１域、５・・・・
・・下面バンプ、６・・・・・・第１　ｌ＠目セジミッ
クス、７・・・・・・第２層目セラミックス、８・・・
・・・紺３Ｊ−目セラミックス、９・・・・・・スルー
ホールである。 ＃１　図　　　　　　手２　図 ３ 察３　巳 早４　聞　　　　　　　蒸５　図 第２６　閉 早　７　圀 ＃８　圓 范９目FIGS. 1 and 2 are diagrams showing examples of conventional external lead extraction. FIG. 3 is a sectional view of an embodiment of the present invention, FIG. 6 is a plan sectional view of a container according to the prior art, FIG. 4 is a plan view showing the plane of FIG. 6 on a reduced scale, and FIG. is a plan view showing a scaled-down version of the plan shown in Figure 3. FIG. 7 to FIG. 9 are diagrams showing the manufacturing process of the seventh embodiment in which the present invention is applied to ceramics.
Figure 7 is a plan view of a through hole drilled in the fourth IN ceramic, Figure 8 is a plan view of the first eyelet ceramic and second layer ceramics combined to form a bank, and Figure 9 is a cross-sectional view of the finished product. be. In the figure, l...external lead, 2...
...Top surface bump, 3...Internal lead pattern, 4...Internal lead pattern 1 area, 5...
...Bottom bump, 6...1st l@th Sedimix, 7...2nd layer ceramics, 8...
...Dark blue 3J-eye ceramics, 9...Through hole. #1 Diagram Hand 2 Diagram 3 Saku 3 Mihaya 4 Kun Steam 5 Diagram 26 Closing Haya 7 Gui #8 Enban 9th

Claims (1)

【特許請求の範囲】[Claims] 容器の両面に多数の外部配線引き出し用バンプ余有する
ことｒ特徴とする半導体集積回路装置の容器。A container for a semiconductor integrated circuit device, characterized by having a large number of bumps for drawing out external wiring on both sides of the container.
JP57117516A 1982-07-06 1982-07-06 Package of semiconductor integrated circuit device Pending JPS598361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57117516A JPS598361A (en) 1982-07-06 1982-07-06 Package of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57117516A JPS598361A (en) 1982-07-06 1982-07-06 Package of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS598361A true JPS598361A (en) 1984-01-17

Family

ID=14713695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57117516A Pending JPS598361A (en) 1982-07-06 1982-07-06 Package of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS598361A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923548A (en) * 1982-07-30 1984-02-07 Fujitsu Ltd Semiconductor device
JPS63258048A (en) * 1987-04-15 1988-10-25 Mitsubishi Electric Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619040B2 (en) * 1974-05-16 1981-05-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619040B2 (en) * 1974-05-16 1981-05-02

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923548A (en) * 1982-07-30 1984-02-07 Fujitsu Ltd Semiconductor device
JPS63258048A (en) * 1987-04-15 1988-10-25 Mitsubishi Electric Corp Semiconductor device

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