JPS5984547A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5984547A JPS5984547A JP57195774A JP19577482A JPS5984547A JP S5984547 A JPS5984547 A JP S5984547A JP 57195774 A JP57195774 A JP 57195774A JP 19577482 A JP19577482 A JP 19577482A JP S5984547 A JPS5984547 A JP S5984547A
- Authority
- JP
- Japan
- Prior art keywords
- input
- pads
- circuit
- power supply
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims 4
- 238000003491 array Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、一部マスク変更で作られるセミカスタムエ０
の、パッド形成に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semi-custom image created by partially changing a mask.
, regarding pad formation.
最近、ゲートアレーに代表されるマスタースライスセミ
カスタムエ０が広く使われ始めている。Recently, master slice semi-custom arrays, represented by gate arrays, have begun to be widely used.
通常ゲートアレー（以下ＧＡと略記）では、１層もしく
は２層程度の配線層マスクの切換えにより、ユーザー仕
様の回路を作り込んでいく。又入出力パッドは、各回路
に於いて必要最小数を使うのが普通であり、多くの場合
、数ないし数十のパッドは、不用となる。In a normal gate array (hereinafter abbreviated as GA), a user-specified circuit is created by switching one or two wiring layer masks. In addition, it is common to use the minimum number of input/output pads required for each circuit, and in many cases, several to several tens of pads are unnecessary.
第１図に一例として従来の０Ｍ０８ＧＡに於いて不用パ
ッドの処理例を示す。入力もしくは出力パッド１０１に
対し入出力回路１０３を接続することなく、入出力端子
１０２を、アースラインもしくは、電源電圧と同電位に
置く、これは特に入力端子が、アースラインもしくは、
電源位に接続しておかないと、入力端子１０２が中間電
位になり０ＭＯ８回路である入力回路１０３に多大な電
流が流れるこれを防ぐためである。１０４は内部回路で
ある。従来の方法に於いてはパッド１０１を全く形成し
ないか、形成しても入出力回路あるいは電源とも無接続
であった。これに対し、第二図、第三図に、本発明の実
施例を示す。実施例１として、第二図に示□すように、
入力パッド２０１と入力回路２０３の入力端子２０２を
接続し、アースラインもしくは、電源位とする。内部回
路は２０４である。実施例２として第三図の例は、入カ
パッド３０１を、アースラインもしくは、電源位とし、
入力回路３０６の入力端子６０２を、入力パッド３０１
と逆電位の電源ラインに接続する。６０４は内部回路で
ある。上記の二つの実施例で共通しているのが、回路的
に不用なパッドが電源パッ′ドとして使われていること
である。このことは、従来何ら役に立っていなかった不
用パッドが、電源パッドとして利用している点が本発明
の最もすぐれた利点であり、ＧＡに於いて、電源用パッ
ドが多く設置できるので、チップ実装時のワイヤーボン
ディングの自由度が非常に大きくなるFIG. 1 shows an example of processing of unnecessary pads in a conventional 0M08GA. The input/output terminal 102 is placed at the same potential as the ground line or the power supply voltage without connecting the input/output circuit 103 to the input or output pad 101. This is especially true if the input terminal is connected to the ground line or
This is to prevent the input terminal 102 from being at an intermediate potential if it is not connected to the power supply potential, causing a large amount of current to flow through the input circuit 103, which is an 0MO8 circuit. 104 is an internal circuit. In conventional methods, the pad 101 is not formed at all, or even if it is formed, it is not connected to the input/output circuit or the power source. In contrast, FIGS. 2 and 3 show embodiments of the present invention. As Example 1, as shown in Figure 2,
The input pad 201 and the input terminal 202 of the input circuit 203 are connected to the ground line or power supply level. The internal circuit is 204. In the example shown in FIG. 3 as the second embodiment, the input pad 301 is set to the ground line or power supply level,
The input terminal 602 of the input circuit 306 is connected to the input pad 301
Connect to a power line with the opposite potential. 604 is an internal circuit. What the above two embodiments have in common is that pads that are unnecessary in terms of circuitry are used as power supply pads. The most excellent advantage of the present invention is that unnecessary pads that were previously of no use are now used as power supply pads. The degree of freedom in wire bonding is greatly increased.
第１図が、従来の入出力パッドの取扱い例、第２図、第
３図が、本発明の実施例。
１０１．２０１，３０１が入力バッド、１０３．２０３
，３０３が入力回路である。FIG. 1 shows an example of how a conventional input/output pad is handled, and FIGS. 2 and 3 show an example of the present invention. 101.201, 301 are input bad, 103.203
, 303 is an input circuit.
Claims (1)
なセミカスタム半導体装置に於いて、外部端子をとり出
さない不使用なｉ！極パッドを、全てこの半導体装置の
電源用パッドとして用いることを特徴とする半導体装置
。In master slice semi-custom semiconductor devices made by switching wiring layer masks, there is an unused i! which does not take out external terminals. A semiconductor device characterized in that all pole pads are used as power supply pads of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57195774A JPS5984547A (en) | 1982-11-08 | 1982-11-08 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57195774A JPS5984547A (en) | 1982-11-08 | 1982-11-08 | semiconductor equipment |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21080190A Division JPH03241763A (en) | 1990-08-09 | 1990-08-09 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5984547A true JPS5984547A (en) | 1984-05-16 |
| JPH0416946B2 JPH0416946B2 (en) | 1992-03-25 |
Family
ID=16346738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57195774A Granted JPS5984547A (en) | 1982-11-08 | 1982-11-08 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984547A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61229103A (en) * | 1985-04-04 | 1986-10-13 | Canon Inc | Controller of copying machine or the like |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5561054A (en) * | 1978-10-30 | 1980-05-08 | Mitsubishi Electric Corp | Large scale integrated circuit |
| JPS58197746A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1982
- 1982-11-08 JP JP57195774A patent/JPS5984547A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5561054A (en) * | 1978-10-30 | 1980-05-08 | Mitsubishi Electric Corp | Large scale integrated circuit |
| JPS58197746A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61229103A (en) * | 1985-04-04 | 1986-10-13 | Canon Inc | Controller of copying machine or the like |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0416946B2 (en) | 1992-03-25 |
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