JPS5984548A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain the semiconductor device of high density by forming a conductive material or an insulating film to the surface of a substrate with a stepped difference and isolating wirings or boring a through-hole in a self-alignment manner in a stepped difference section. CONSTITUTION:The stepped difference of the silicon semiconductor substrate 1 is formed by a material different from the substrate 1 such as polycrystalline silicon 5 and a silicon oxide film 7. Silicon patterns 201, 203 can be formed in a self-alignment manner to the thickness of approximately 4,500Angstrom of the stepped difference. Consequently, the silicon 201, 203 can be formed on the same plane while being extremely brought close to the silicon 5, and silicon 202 changed into the same pattern as the silicon 5 can also be formed. Accordingly, the density of the wirings can be increased efficiently because other conductors 201, 203 can be formed brought close to the conductor 5 and a space between the conductors 201, 203 can be brought to 0.3mum or less.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having high-density conductive wiring and a device structure, and a method for manufacturing the same.

(Prior Art) Conventionally, in semiconductor integrated circuits, the wiring spacing and through-hole openings are determined by the fine pattern accuracy in photolithography and the mask alignment margin of each layer, and as this type of device increases in density and This was an impediment to higher integration.

(Objective of the Invention) In order to solve these drawbacks, the present invention uses a new basic principle to form a conductive material or an insulating film on one surface with a step, and to separate or separate the wiring in a self-aligned manner at the step. The purpose of this method is to obtain a high-density semiconductor device by forming through-holes.

(Structure of the Invention) In order to achieve the above object, the present invention has a vertical step on the surface of a semiconductor substrate, and conductive material or insulating material on the side wall of the step is removed in a rhombic shape so that separation occurs at the step. The gist of the invention is a semiconductor device which is characterized by the above-mentioned characteristics. Furthermore, the present invention deposits an insulating film or a conductive film on a surface having a step using a directional thin film deposition device such as a WAR plasma deposition device, a magnetron sputtering device, or an ion beam deposition device, and The method is characterized in that the insulating film or the conductive film deposited in a diamond shape is subjected to etching or oxidation treatment to separate the insulating film or the conductive film in a self-aligned manner with respect to the step. The gist of the invention is a method for manufacturing a semiconductor device.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. Note that the embodiment is merely an illustration, and it goes without saying that various changes and improvements may be made without departing from the AIi spirit of the present invention.

FIG. 1 is a structural sectional view showing the basic principle of the present invention. In the figure, 1 is a semiconductor substrate having a step on its surface, 2 is a deposited film having a dense film quality, and 2' is a deposited film having a brittle film quality, which is made of the same material as 1. As shown in FIG. 1, a film is deposited using a directional deposition method (e.g., EOR type plasma deposition method, magnetron sputtering method,
A conductive material (for example, Si, Mo, MoSi, etc.) or an insulating film (for example, Si, N4, Sin, etc.) with a film thickness of 1 μm is deposited using ion beam deposition paper, etc.). A dense film 2 is deposited on the flat part b[ of the substrate l, and a fragile film 2' is deposited on the stepped sidewall part a. In particular, 5 in 2. Si,
N, l, Si.

A film of Mo, MoSi, etc. can be deposited. The degree of vacuum at this time is 10 to 10 Torr. According to this method, the thickness of the deposited film on the stepped sidewall a increases to about 4/4 of that of the flat surface, and the fragile deposited film 2' is formed on the sidewall portion aK. This fragile deposited film is easily etched by light etching. (The etching rate of the brittle film deposited on the side wall a is the same as that of the dense film deposited on the flat surface.
The etching speed is more than 100 times that of the previous one. Therefore, 3%H
Etched with F solution in a few seconds. ) Also, S10. The film quality of the film, the 81 film, the Si3N4 film, etc. is comparable to that of the thermal oxide film and the CVZD film, respectively, and the interface characteristics with silicon can be obtained. moreover,
These films can be easily obtained with different compositions such as 5ixOy and Six'N; and the composition can be selected in consideration of the thermal stress difference with the substrate. For this reason, it is possible to select an abrasive with less stress even if high-temperature heat treatment is performed in a subsequent process step.

The basic principle of the present invention is to separate the deposited film 2 in a self-aligned manner at the step sidewall portion a shown in FIG. 1(A). 1st
Figure (B) shows the present invention realized by removing the fragile film 2' deposited on the step side wall a by etching and forming a groove C along the step side wall a.7-4. The angle θ between the groove C of c, that is, the deposited film and the stepped sidewall of the silicon substrate
runs about 30 degrees. This angle is determined by the thickness ratio of the film formed on the flat surface and the side wall portion during deposition. Also, Figure 1 (0)
The present invention was realized by changing the fragile deposited film 2' to another substance 3. In this case, it is desirable that the deposited film 2 be made of silicon, metal silicide, or other oxides, nitrides, etc. of stable quality. Further, when the deposited film 2 is conductive, it is desirable that the compound 3 changes to an insulating group. In this example, silicon was deposited and oxidized for 30 minutes at 900° C. in a wet 0□ atmosphere. At this time,
Only fragile films are oxidized; films deposited on flat surfaces are hardly oxidized.

Diagram M2 shows an embodiment of the invention. In the figure, l is a silicon semiconductor substrate, 201, 202, and 203 are a deposited film (silicon) with a dense and good quality, 2' is a deposited film (silicon) with a fragile film quality, 5 is a conductive material (silicon or metal), and 7 is an insulating material (S102). In this embodiment, the step is formed from a material different from that of the silicon semiconductor substrate 1, that is, polycrystalline silicon 5 and silicon oxide film 7.

The respective film thicknesses are 4500 A and 1000 A. It can be obtained by the same method as shown in FIG. 1 except for the method of forming the step. According to this structure, silicon patterns 201, 202, and 203 can be formed in a self-aligned manner for a step thickness of approximately 450 OA formed by polycrystalline silicon 5, which is a conductor, and silicon oxide film 7, which is an insulating material. .

This means that silicon 5 can be formed very close to silicon 5, silicon 201 and 203 can be formed on the same plane, and silicon 5 can be formed on the same plane.
Silicon 202 having the same pattern can also be formed.

Therefore, the other conductors 201 and 2 are placed close to the conductor 5.
03 can be formed and the interval between them can be made 0.3 μm or less, so the wiring density can be efficiently increased.

FIG. 3 shows another embodiment of the present invention, in which the principle of the present invention is applied to M
FIG. 3 is a diagram for explaining process steps when applied to an O8 integrated circuit. MrJ3 (A) is a cross-sectional view of the structure after the gate polycrystalline silicon has been processed in the MO8 integrated circuit manufacturing process. In the figure, 11 is a p-type silicon substrate, 9
5 indicates a field oxide film (film thickness 1 μIn), 4t gate oxide film (film thickness 5oon), and 5' gate polycrystalline silicon (film thickness 2000λ). The process up to this point is normal M
It can be manufactured using known methods for O8 integrated circuits. Next, as shown in FIG. 3(B), by the EOR type plasma deposition method! Silicon deposited film 2 containing 1lln type impurity (p)
01, 202, 203, and 2 are deposited to a thickness of 2000λ. Formation conditions are microwave power 150W, vacuum degree 5
X 10-'TOrr, 5in4 flow rate 20CO/
In this case, as shown in FIG. 1A, a silicon deposited film 2' having a brittle film quality is deposited on the side wall of the step. The deposition rate at this time was 360 A/via. Next, when heat treatment is performed at about 900°C and 230°C in a wet ozl atmosphere, the silicon 2 on the step sidewalls is easily oxidized and the silicon deposited films 201 and 202 are formed.

203 are separated by the silicon oxide film 3 at the stepped portions. During heat treatment at 900°C, silicon deposition &2
The N-type impurities contained in 01 and 203 form silicon substrate 1.
1 surface, and the source and drain f@601, '603 of a MOS transistor can be formed. Thereafter, the deposited silicon films 201, 202, and 203 are processed by photolithography and etching to obtain the structure shown in FIG. is deposited to a thickness of 5 mm by the OVD method, through holes are formed, and AJ-electrodes 211 and 213 are formed.As a result, an MO8 integrated circuit as shown in FIG. .

In this example, after the process shown in FIG. 3 CB), ML can also be performed by etching away the weak film 2' of the source and drain lead silicon for the gate electrode by oxidation in a wet 0□ atmosphere. Needless to say.

According to the above embodiment, compared to a normal MO8 integrated circuit, +px
However, there are three advantages:

(b) The feature of this structure is that the separation at the step part has a rhombic shape. According to this structure, the step is formed from the insulating film (G) and the gate polysilicon (S1), which is the conductor, and the silicon which becomes the source and drain lead electrodes is formed by the EOR type plasma deposition method. Ru. Since the separation at the step part becomes diamond-shaped, it is theoretically possible to separate the gate poly S1 from the source and drain lead electrodes only by the sidewalls of the gate oxide film, and it is possible to do so on the surface of the silicon substrate. The amount of separation seen can be reduced to zero.

In this embodiment as well, the separation between the gate electrodes 5 and 202 and the source and drain lead-out electrodes was made to be less than 1 μm.

Therefore, this structure is very advantageous for high density of denomination chairs.

(b) Source and drain diffusion Jii 601, 6
Since 03 is formed by diffusion of impurities contained in silicon 201 and 203, it is possible to form a very shallow junction (thickness of 0.1 μm or less) compared to the formation of a junction by ion implantation. This can reduce the short channel effect (the effect in which the threshold voltage becomes significantly lower as the channel length becomes smaller), which has become a problem with the miniaturization of MOS transistors.

(c) Deposited film 2 which is source/drain extraction electrode
By placing 01 and 203 on field oxide film 9, the area of source and drain diffusion layers 601 and 603 can be reduced. For this reason, the capacitance between the source and substrate can be reduced to 100%, making it possible to realize a high-speed MO8 integrated circuit.Also, since the area of the source and drain diffusion layers 601 and 603 is reduced, the circuit operation can be improved. It is also possible to reduce the influence of alpha rays that cause defects.

FIG. 4 shows another embodiment that is an improvement on the embodiment shown in FIG.

The difference from the embodiment shown in Fig. 3 is F in step 5 of Fig. 3 CB).
Silicon containing impurities was formed by OR type plasma deposition method, but in this example, E (E (ER type plasma deposition method) was used to form silicon containing impurities 21.21, followed by Mo 22.22).
The point is that it is accumulating. Each film thickness is 500~1
000 A, 1000-3000λ. According to this embodiment, the resistance of the gate electrodes 5, 21° 22, the source and drain lead electrodes 21, 22 can be reduced to 0.1Ω or less (approximately 20Ω to 50Ω when silicon is used only), and the resistance of the source and drain diffusion/i 601,
Since the depth of 603 can be made shallow to 0.1/Zm or less, a high-density and high-speed MO8 integrated circuit can be realized.

FIG. 5 shows another embodiment that is an improvement on the embodiment shown in FIG.

The difference from the embodiment shown in FIG. 3 is that in the step shown in FIG. 3(A), after processing the gate silicon 5 and the nitride film 4, relatively lightly concentrated source/drain layers 601' and 603' are formed.
It is located in the area where it forms. Specifically, when an n-type silicon substrate is used, As is heated to an energy of 100 KeV.
Ion implantation is performed under the condition of a dose of I x 10" crn-2. According to this embodiment, compared to the embodiment shown in FIG. The junction breakdown voltage can be greatly increased, and the short channel effect of the MOS transistor can be suppressed as in the embodiment shown in FIG.

Figure 6 shows the principle of the present invention as an oxidation mask with a semiconductor process width.
An example of application to a diffusion mask etc. will be shown.

In the figure, 11 is a silicon semiconductor substrate. Figure 1 (
A groove C is formed in the stepped portion of the silicon substrate 11 by the method described in B). Figure 6 shows the silicon substrate 11 and tj
, a different impurity (for example, 5 tO2) is diffused into the silicon substrate 11 through the groove C using a mask. It goes without saying that by using an oxidation-resistant film such as a silicon nitride film as the deposited film 2, the silicon substrate 11 can be selectively oxidized through the groove C using the deposited film 2 as a mask.

According to this embodiment, an impurity diffusion layer and a thermal oxide film can be easily formed selectively on the sidewalls of the step portion.

Further, the openings at the stepped portions are diamond-shaped, and according to the present structure, it is theoretically possible to expose only the surface of the stepped sidewall portions. The results of this example show that the exposure of the silicon flat part in the opening is less than 0,iμm.
No fog is coming out.

FIG. 7 shows another embodiment of the invention. In the figure 11)
A silicon semiconductor substrate, 2 is a silicon oxide substrate (thickness 5
000 A), 8 is an impurity diffusion layer, 91.

91' indicates silicon containing impurities. In FIG. 7(A), a cine thin material expanded 1rk layer 8 is formed by the method shown in FIG. , 1.300OA. According to these silicon forming methods, the groove C shown in FIG. 6 is easily filled with silicon. Here, the impurity diffusion layer 8 is formed using silicon 91 containing impurities.
Formation is also possible by diffusion from. Thereafter, the silicon 91 is etched by a directional etching method such as a parallel plate plasma etching method or an active ion etching (R-E+) method.
As shown in FIG. CB), the silicon in the flat portion can be removed while the trench is filled with silicon 91' containing impurities.

According to this embodiment, the extraction electrode 91' can be formed in a self-aligned manner from the diffusion layer 8 formed in the stepped portion of the silicon substrate 11, and a high-density integrated circuit can be realized.

FIG. 8 shows an example in which the embodiment shown in FIG. 7 is applied to a bipolar transistor. In the figure, 11 is a p-type silicon substrate, 8 and 8' are n-swelled diffusion layers, 6'' is a p-swelled diffusion layer, 2 is a silicon oxide film, 91' is silicon for the base extraction electrode, and 111 is silicon oxide M , 214, 215 are A.J.
It is an electrode. According to this embodiment, the embodiment shown in FIG. 7 is applied to the base forming portion of the bipolar transistor.
The base area has been drastically reduced.

(Effects of the Invention) As explained above, the present invention uses a new basic principle to form a conductive layer or an insulating material on a surface with a step, and to conduct wiring separation, through-hole formation, and diffusion in a self-aligned manner at the step.・Provides a semiconductor device with high density, high speed, and high integration density such as oxide mask formation. In the above explanation, MO8 integrated circuits have been mainly explained for the sake of simplicity, but it goes without saying that the present invention can also be implemented in integrated circuits such as bipolar integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a structural sectional view showing the basic principle of the present invention, FIG. 2 is an embodiment of the invention, and FIGS. 3 to 8 each show other embodiments of the invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Deposited film, 2... Deposited film, 3... Silicon oxide arm, 4... Gate oxide film, 5...
... Conductive material (silicon), 5'... Gate polycrystalline silicon, 7... Insulating Hamura (silicon oxide film), 8,8
. . . n-swelled diffusion layer, 9 . . . field oxide film, 11.
...p-type silicon substrate, 21.21'...silicon containing impurities, 22...MO191,91'...silicon, 111...silicon oxide group, 201, 202
, 203...Deposited film having dense film quality, 211,
213...A1 electrode, 214, 215...AV electrode, 601...MOS) Source diffusion 1 of transistor
'fd, 603...MOS) Drain diffusion layer of transistor Patent applicant Figure 4 Figure 6

Claims (3)

[Claims] (1) A semiconductor device having a vertical step on the surface of a semiconductor substrate, and a conductive material or an insulating material on the side wall of the step is removed in a rhombus shape and separated at the step. (2) The step formation is made of two or more different materials, and the gate electrode of the MOS transistor is self-aligned with the gate electrode and has a relatively low impurity concentration.
and a second diffusion layer having a relatively high degree of impurity, the depth of the first diffusion layer is also greater than the depth of the second diffusion layer. A semiconductor device according to scope 1. (3) Depositing an insulating film or a conductive film on a surface having a step using a device with directionality for thin film deposition such as an ECR plasma deposition device, a magnetrosis battering device, or an ion beam deposition device, and depositing an insulating film or a conductive film on the side wall of the step. A semiconductor characterized in that the insulating film or the conductive film is separated in a self-aligned manner with respect to the step by etching or oxidizing the fragile film of the insulating film or the conductive film deposited in a rhombus shape. Method of manufacturing the device.