JPS5984938U - noise reduction circuit - Google Patents
noise reduction circuitInfo
- Publication number
- JPS5984938U JPS5984938U JP13571483U JP13571483U JPS5984938U JP S5984938 U JPS5984938 U JP S5984938U JP 13571483 U JP13571483 U JP 13571483U JP 13571483 U JP13571483 U JP 13571483U JP S5984938 U JPS5984938 U JP S5984938U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- noise reduction
- reduction circuit
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Filters And Equalizers (AREA)
- Electronic Switches (AREA)
- Noise Elimination (AREA)
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す図、第２図及び第３図
は夫々本考案の他の実施例を示す図、第４図は本考案に
よる雑音低減効果を説明する特性曲線図である。
４．６・・−中間周波増幅器、７・・・検波回路、８・
・・ＭＰＸ回路、Ｄ、、 Ｄ２・・・倍電圧整流ダイオ
ード、Ｃ７・・・バイパスコンデンサ、Ｑ２・・・スイ
ッチングトランジスタ。FIG. 1 is a diagram showing one embodiment of the present invention, FIGS. 2 and 3 are diagrams each showing other embodiments of the present invention, and FIG. 4 is a characteristic curve diagram illustrating the noise reduction effect of the present invention. It is. 4.6... - intermediate frequency amplifier, 7... detection circuit, 8...
...MPX circuit, D, D2...voltage doubler rectifier diode, C7...bypass capacitor, Q2...switching transistor.
Claims (1)
の出力からＭＰＸ回路の内力に至る経路に、コンデンサ
を介してＰＮＰト沙ジスタのエミッタを接続し、該トラ
ンジスタのベースには前記受信機の中間周波信号のレベ
ルに応じた信号を与えると共に上記トランジスタめエミ
ッタには抵抗によって分圧されたバイアス電圧を与える
ことにより、上記トランジスタが上記コンデンサと接地
間のインピーダンスを変化させて前記検波回路からＭＰ
Ｘ回路に至る周波数特性を連続的に変化させるように構
成したことを特徴とする雑音低減回路。In an FM two-channel stereo receiver, the emitter of a PNP transistor is connected via a capacitor to the path from the output of the detection circuit to the internal power of the MPX circuit, and the base of the transistor is connected to the base of the receiver's intermediate frequency signal. By applying a signal according to the level and applying a bias voltage divided by a resistor to the emitter of the transistor, the transistor changes the impedance between the capacitor and the ground, and the MP from the detection circuit.
A noise reduction circuit characterized in that it is configured to continuously change frequency characteristics up to the X circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13571483U JPS6042534Y2 (en) | 1983-09-01 | 1983-09-01 | noise reduction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13571483U JPS6042534Y2 (en) | 1983-09-01 | 1983-09-01 | noise reduction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5984938U true JPS5984938U (en) | 1984-06-08 |
| JPS6042534Y2 JPS6042534Y2 (en) | 1985-12-27 |
Family
ID=30305381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13571483U Expired JPS6042534Y2 (en) | 1983-09-01 | 1983-09-01 | noise reduction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6042534Y2 (en) |
-
1983
- 1983-09-01 JP JP13571483U patent/JPS6042534Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6042534Y2 (en) | 1985-12-27 |
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